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stm32/rcc: unify f2 into f4/f7.

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This commit is contained in:
Dario Nieuwenhuis
2023-11-13 01:56:28 +01:00
parent 2376b3bdfa
commit ace5221080
6 changed files with 161 additions and 391 deletions
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21
tests/stm32/src/common.rs
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@ -236,24 +236,25 @@ pub fn config() -> Config {
{
use embassy_stm32::rcc::*;
// By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
config.rcc.hse = Some(HSEConfig {
frequency: Hertz(8_000_000),
source: HSESrc::Bypass,
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
});
// PLL uses HSE as the clock source
config.rcc.pll_mux = PllSource::HSE;
config.rcc.pll = Pll {
config.rcc.pll_src = PllSource::HSE;
config.rcc.pll = Some(Pll {
// 8 MHz clock source / 8 = 1 MHz PLL input
pre_div: unwrap!(PllPreDiv::try_from(8)),
prediv: unwrap!(PllPreDiv::try_from(8)),
// 1 MHz PLL input * 240 = 240 MHz PLL VCO
mul: unwrap!(PllMul::try_from(240)),
// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
divp: PllPDiv::DIV2,
divp: Some(PllPDiv::DIV2),
// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
divq: PllQDiv::DIV5,
};
divq: Some(PllQDiv::DIV5),
divr: None,
});
// System clock comes from PLL (= the 120 MHz main PLL output)
config.rcc.mux = ClockSrc::PLL;
config.rcc.sys = Sysclk::PLL1_P;
// 120 MHz / 4 = 30 MHz APB1 frequency
config.rcc.apb1_pre = APBPrescaler::DIV4;
// 120 MHz / 2 = 60 MHz APB2 frequency