Expose data transfer timeout and implement configuration for BusWidth one
This commit is contained in:
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359aaa5aeb
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ad720f83df
@ -24,12 +24,13 @@ embedded-sdmmc = { git = "https://github.com/thalesfragoso/embedded-sdmmc-rs", b
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regex = "1.4.6"
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[features]
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default = ["stm32h750vb", "defmt-debug", "defmt"]
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default = ["stm32h750vb", "defmt-debug", "defmt", "sdmmc-rs"]
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defmt-trace = [ ]
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defmt-debug = [ ]
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defmt-info = [ ]
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defmt-warn = [ ]
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defmt-error = [ ]
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sdmmc-rs = ["embedded-sdmmc"]
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# BEGIN GENERATED FEATURES
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stm32f401cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
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@ -5,7 +5,6 @@ use core::task::Poll;
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use embassy::interrupt::InterruptExt;
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use embassy::util::{AtomicWaker, OnDrop, Unborrow};
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use embassy_extras::unborrow;
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use embedded_sdmmc::{Block, BlockCount, BlockDevice, BlockIdx};
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use futures::future::poll_fn;
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use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID, CSD, OCR, SCR};
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@ -151,6 +150,8 @@ pub struct Sdmmc<'d, T: Instance, P: Pins<T>> {
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signalling: Signalling,
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/// Card
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card: Option<Card>,
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/// The timeout to be set for data transfers, in card bus clock periods
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data_transfer_timeout: u32,
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}
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impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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@ -164,6 +165,7 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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irq: impl Unborrow<Target = T::Interrupt>,
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hclk: Hertz,
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kernel_clk: Hertz,
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data_transfer_timeout: u32,
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) -> Self {
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unborrow!(irq, pins);
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pins.configure();
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@ -184,6 +186,7 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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clock,
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signalling: Default::default(),
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card: None,
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data_transfer_timeout,
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}
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}
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@ -202,6 +205,7 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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self.ker_ck,
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&mut self.clock,
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T::state(),
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self.data_transfer_timeout,
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)
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.await
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}
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@ -218,7 +222,15 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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// NOTE(unsafe) DataBlock uses align 4
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let buf = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) };
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inner.read_block(block_idx, buf, card_capacity, state).await
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inner
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.read_block(
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block_idx,
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buf,
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card_capacity,
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state,
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self.data_transfer_timeout,
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)
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.await
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}
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pub async fn write_block(&mut self, block_idx: u32, buffer: &DataBlock) -> Result<(), Error> {
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@ -228,7 +240,9 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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// NOTE(unsafe) DataBlock uses align 4
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let buf = unsafe { &*((&buffer.0) as *const [u8; 512] as *const [u32; 128]) };
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inner.write_block(block_idx, buf, card, state).await
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inner
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.write_block(block_idx, buf, card, state, self.data_transfer_timeout)
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.await
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}
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/// Get a reference to the initialized card
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@ -302,6 +316,7 @@ impl SdmmcInner {
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ker_ck: Hertz,
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clock: &mut Hertz,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<(), Error> {
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let regs = self.0;
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@ -371,7 +386,8 @@ impl SdmmcInner {
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card.csd = csd.into();
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self.select_card(Some(&card))?;
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self.get_scr(&mut card, waker_reg).await?;
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self.get_scr(&mut card, waker_reg, data_transfer_timeout)
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.await?;
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// Set bus width
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let (width, acmd_arg) = match bus_width {
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@ -404,12 +420,13 @@ impl SdmmcInner {
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}
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// Read status
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self.read_sd_status(&mut card, waker_reg).await?;
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self.read_sd_status(&mut card, waker_reg, data_transfer_timeout)
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.await?;
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if freq.0 > 25_000_000 {
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// Switch to SDR25
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*signalling = self
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.switch_signalling_mode(Signalling::SDR25, waker_reg)
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.switch_signalling_mode(Signalling::SDR25, waker_reg, data_transfer_timeout)
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.await?;
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if *signalling == Signalling::SDR25 {
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@ -422,7 +439,8 @@ impl SdmmcInner {
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}
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}
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// Read status after signalling change
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self.read_sd_status(&mut card, waker_reg).await?;
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self.read_sd_status(&mut card, waker_reg, data_transfer_timeout)
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.await?;
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old_card.replace(card);
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}
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@ -435,6 +453,7 @@ impl SdmmcInner {
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buffer: &mut [u32; 128],
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capacity: CardCapacity,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<(), Error> {
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// Always read 1 block of 512 bytes
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// SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
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@ -449,7 +468,13 @@ impl SdmmcInner {
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let buf_addr = buffer as *mut [u32; 128] as u32;
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unsafe {
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self.prepare_datapath_transfer(buf_addr, 512, 9, Dir::CardToHost);
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self.prepare_datapath_transfer(
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buf_addr,
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512,
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9,
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Dir::CardToHost,
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data_transfer_timeout,
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);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::read_single_block(address), true)?;
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@ -485,6 +510,7 @@ impl SdmmcInner {
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buffer: &[u32; 128],
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card: &mut Card,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<(), Error> {
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// Always read 1 block of 512 bytes
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// SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
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@ -499,7 +525,13 @@ impl SdmmcInner {
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let buf_addr = buffer as *const [u32; 128] as u32;
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unsafe {
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self.prepare_datapath_transfer(buf_addr, 512, 9, Dir::HostToCard);
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self.prepare_datapath_transfer(
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buf_addr,
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512,
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9,
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Dir::HostToCard,
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data_transfer_timeout,
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);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::write_single_block(address), true)?;
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@ -527,16 +559,18 @@ impl SdmmcInner {
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regs.idmactrlr().modify(|w| w.set_idmaen(false));
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}
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// TODO: Make this configurable
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let mut timeout: u32 = 0xFFFF_FFFF;
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let mut timeout: u32 = 0x00FF_FFFF;
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// Try to read card status (ACMD13)
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while timeout > 0 {
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match self.read_sd_status(card, waker_reg).await {
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match self
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.read_sd_status(card, waker_reg, data_transfer_timeout)
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.await
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{
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Ok(_) => return Ok(()),
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Err(Error::Timeout) => (), // Try again
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Err(e) => return Err(e),
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}
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timeout -= 1;
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}
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Err(Error::SoftwareTimeout)
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@ -573,6 +607,7 @@ impl SdmmcInner {
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length_bytes: u32,
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block_size: u8,
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direction: Dir,
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data_transfer_timeout: u32,
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) {
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self::assert!(block_size <= 14, "Block size up to 2^14 bytes");
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let regs = self.0;
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@ -588,8 +623,8 @@ impl SdmmcInner {
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// NOTE(unsafe) We have exclusive access to the regisers
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// TODO: Make this configurable
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regs.dtimer().write(|w| w.set_datatime(5_000_000));
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regs.dtimer()
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.write(|w| w.set_datatime(data_transfer_timeout));
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regs.dlenr().write(|w| w.set_datalength(length_bytes));
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regs.idmabase0r().write(|w| w.set_idmabase0(buffer_addr));
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@ -637,6 +672,7 @@ impl SdmmcInner {
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&self,
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signalling: Signalling,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<Signalling, Error> {
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// NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not
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// necessary"
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@ -659,7 +695,13 @@ impl SdmmcInner {
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let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
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unsafe {
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self.prepare_datapath_transfer(status_addr, 64, 6, Dir::CardToHost);
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self.prepare_datapath_transfer(
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status_addr,
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64,
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6,
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Dir::CardToHost,
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data_transfer_timeout,
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);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::cmd6(set_function), true)?; // CMD6
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@ -724,7 +766,12 @@ impl SdmmcInner {
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}
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/// Reads the SD Status (ACMD13)
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async fn read_sd_status(&self, card: &mut Card, waker_reg: &AtomicWaker) -> Result<(), Error> {
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async fn read_sd_status(
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&self,
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card: &mut Card,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<(), Error> {
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let rca = card.rca;
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self.cmd(Cmd::set_block_length(64), false)?; // CMD16
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self.cmd(Cmd::app_cmd(rca << 16), false)?; // APP
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@ -737,7 +784,13 @@ impl SdmmcInner {
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let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
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unsafe {
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self.prepare_datapath_transfer(status_addr, 64, 6, Dir::CardToHost);
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self.prepare_datapath_transfer(
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status_addr,
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64,
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6,
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Dir::CardToHost,
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data_transfer_timeout,
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);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::card_status(0), true)?;
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@ -832,7 +885,12 @@ impl SdmmcInner {
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}
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}
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async fn get_scr(&self, card: &mut Card, waker_reg: &AtomicWaker) -> Result<(), Error> {
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async fn get_scr(
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&self,
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card: &mut Card,
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waker_reg: &AtomicWaker,
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data_transfer_timeout: u32,
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) -> Result<(), Error> {
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// Read the the 64-bit SCR register
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self.cmd(Cmd::set_block_length(8), false)?; // CMD16
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self.cmd(Cmd::app_cmd(card.rca << 16), false)?;
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@ -845,7 +903,7 @@ impl SdmmcInner {
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let on_drop = OnDrop::new(move || unsafe { self.on_drop() });
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unsafe {
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self.prepare_datapath_transfer(scr_addr, 8, 3, Dir::CardToHost);
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self.prepare_datapath_transfer(scr_addr, 8, 3, Dir::CardToHost, data_transfer_timeout);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::cmd51(), true)?;
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@ -905,36 +963,26 @@ impl SdmmcInner {
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w.set_cmdtrans(data);
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});
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// TODO: Check if this timeout is necessary
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let mut timeout: u32 = 0xFFFF_FFFF;
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let mut status;
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if cmd.resp == Response::None {
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// Wait for CMDSENT or a timeout
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while {
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status = regs.star().read();
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!(status.ctimeout() || status.cmdsent()) && timeout > 0
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} {
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timeout -= 1;
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}
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!(status.ctimeout() || status.cmdsent())
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} {}
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} else {
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// Wait for CMDREND or CCRCFAIL or a timeout
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while {
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status = regs.star().read();
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!(status.ctimeout() || status.cmdrend() || status.ccrcfail()) && timeout > 0
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} {
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timeout -= 1;
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}
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!(status.ctimeout() || status.cmdrend() || status.ccrcfail())
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} {}
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}
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if status.ctimeout() {
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return Err(Error::Timeout);
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} else if timeout == 0 {
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return Err(Error::SoftwareTimeout);
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} else if status.ccrcfail() {
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return Err(Error::Crc);
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}
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Ok(())
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}
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}
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@ -1321,11 +1369,76 @@ where
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const BUSWIDTH: BusWidth = BusWidth::One;
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fn configure(&mut self) {
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self::todo!()
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let (clk_pin, cmd_pin, d0_pin) = self;
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cortex_m::interrupt::free(|_| unsafe {
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// clk
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let block = clk_pin.block();
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let n = clk_pin.pin() as usize;
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let afr_num = CLK::AF_NUM;
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configure_pin(block, n, afr_num, false);
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// cmd
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let block = cmd_pin.block();
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let n = cmd_pin.pin() as usize;
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let afr_num = CMD::AF_NUM;
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configure_pin(block, n, afr_num, true);
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// d0
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let block = d0_pin.block();
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let n = d0_pin.pin() as usize;
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let afr_num = D0::AF_NUM;
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configure_pin(block, n, afr_num, true);
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});
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}
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fn deconfigure(&mut self) {
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self::todo!()
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use pac::gpio::vals::{Moder, Ospeedr, Pupdr};
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let (clk_pin, cmd_pin, d0_pin) = self;
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cortex_m::interrupt::free(|_| unsafe {
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// clk
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let n = clk_pin.pin().into();
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clk_pin
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.block()
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.moder()
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.modify(|w| w.set_moder(n, Moder::ANALOG));
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clk_pin
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.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED));
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// cmd
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let n = cmd_pin.pin().into();
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cmd_pin
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.block()
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.moder()
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.modify(|w| w.set_moder(n, Moder::ANALOG));
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cmd_pin
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.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED));
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cmd_pin
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.block()
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.pupdr()
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.modify(|w| w.set_pupdr(n, Pupdr::FLOATING));
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// d0
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let n = d0_pin.pin().into();
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d0_pin
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.block()
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.moder()
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.modify(|w| w.set_moder(n, Moder::ANALOG));
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d0_pin
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.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED));
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d0_pin
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.block()
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.pupdr()
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.modify(|w| w.set_pupdr(n, Pupdr::FLOATING));
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});
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}
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}
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@ -1359,7 +1472,12 @@ macro_rules! impl_sdmmc_pin {
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};
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}
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impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
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#[cfg(feature = "sdmmc-rs")]
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mod sdmmc_rs {
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use super::*;
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use embedded_sdmmc::{Block, BlockCount, BlockDevice, BlockIdx};
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impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
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type Error = Error;
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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@ -1383,7 +1501,15 @@ impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
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// NOTE(unsafe) Block uses align(4)
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let buf = unsafe { &mut *(block as *mut [u8; 512] as *mut [u32; 128]) };
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inner.read_block(address, buf, card_capacity, state).await?;
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inner
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.read_block(
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address,
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buf,
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card_capacity,
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state,
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self.data_transfer_timeout,
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)
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.await?;
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address += 1;
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}
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Ok(())
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@ -1406,7 +1532,9 @@ impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
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// NOTE(unsafe) DataBlock uses align 4
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let buf = unsafe { &*(block as *const [u8; 512] as *const [u32; 128]) };
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inner.write_block(address, buf, card, state).await?;
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inner
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.write_block(address, buf, card, state, self.data_transfer_timeout)
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.await?;
|
||||
address += 1;
|
||||
}
|
||||
Ok(())
|
||||
@ -1418,4 +1546,5 @@ impl<'d, T: Instance, P: Pins<T>> BlockDevice for Sdmmc<'d, T, P> {
|
||||
let count = card.csd.block_count();
|
||||
Ok(BlockCount(count))
|
||||
}
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user