stm32/rng: add test.

embassy-stm32/src/rcc/g4.rs

@@ -118,7 +118,7 @@ impl Default for Config {
             apb2_pre: APBPrescaler::DIV1,
             low_power_run: false,
             pll: None,
-            clock_48mhz_src: None,
+            clock_48mhz_src: Some(Clock48MhzSrc::Hsi48(None)),
             adc12_clock_source: Adcsel::DISABLE,
             adc345_clock_source: Adcsel::DISABLE,
             ls: Default::default(),

embassy-stm32/src/rcc/l4l5.rs

@@ -192,6 +192,10 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::PLL => pll._r.unwrap(),
     };
 
+    #[cfg(stm32l4)]
+    RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
+    #[cfg(stm32l5)]
+    RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
     let _clk48 = match config.clk48_src {
         Clk48Src::HSI48 => hsi48,
         Clk48Src::MSI => msi,

embassy-stm32/src/rcc/u5.rs

@@ -188,7 +188,7 @@ impl Default for Config {
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
             apb3_pre: APBPrescaler::DIV1,
-            hsi48: false,
+            hsi48: true,
             voltage_range: VoltageScale::RANGE3,
             ls: Default::default(),
         }

embassy-stm32/src/rcc/wb.rs

@@ -40,6 +40,7 @@ pub struct Config {
     pub hse: Option<Hse>,
     pub sys: Sysclk,
     pub mux: Option<PllMux>,
+    pub hsi48: bool,
 
     pub pll: Option<Pll>,
     pub pllsai: Option<Pll>,
@@ -63,6 +64,7 @@ pub const WPAN_DEFAULT: Config = Config {
         source: PllSource::HSE,
         prediv: Pllm::DIV2,
     }),
+    hsi48: true,
 
     ls: super::LsConfig::default_lse(),
 
@@ -90,6 +92,7 @@ impl Default for Config {
             mux: None,
             pll: None,
             pllsai: None,
+            hsi48: true,
 
             ls: Default::default(),
 
@@ -222,6 +225,13 @@ pub(crate) unsafe fn init(config: Config) {
         _ => {}
     }
 
+    let _hsi48 = config.hsi48.then(|| {
+        rcc.crrcr().modify(|w| w.set_hsi48on(true));
+        while !rcc.crrcr().read().hsi48rdy() {}
+
+        Hertz(48_000_000)
+    });
+
     rcc.cfgr().modify(|w| {
         w.set_sw(config.sys.into());
         w.set_hpre(config.ahb1_pre);

embassy-stm32/src/rng.rs

@@ -85,7 +85,7 @@ impl<'d, T: Instance> Rng<'d, T> {
             reg.set_ie(false);
             reg.set_rngen(true);
         });
-        T::regs().cr().write(|reg| {
+        T::regs().cr().modify(|reg| {
             reg.set_ced(false);
         });
         // wait for CONDRST to be set