max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Refactor new

Browse Source
This commit is contained in:
Grant Miller 2021-12-07 13:22:59 -06:00
parent 1a7b9e3279
commit b06658c195
1 changed files with 56 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

122
embassy-stm32/src/spi/mod.rs
View File

@ -152,34 +152,43 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
} }
let pclk = T::frequency(); let pclk = T::frequency();
let br = Self::compute_baud_rate(pclk, freq.into()); let br = compute_baud_rate(pclk, freq.into());
let cpha = match config.mode.phase {
Phase::CaptureOnSecondTransition => vals::Cpha::SECONDEDGE,
Phase::CaptureOnFirstTransition => vals::Cpha::FIRSTEDGE,
};
let cpol = match config.mode.polarity {
Polarity::IdleHigh => vals::Cpol::IDLEHIGH,
Polarity::IdleLow => vals::Cpol::IDLELOW,
};
#[cfg(not(spi_v3))]
use vals::Lsbfirst;
#[cfg(spi_v3)]
use vals::Lsbfrst as Lsbfirst;
let lsbfirst = match config.byte_order {
ByteOrder::LsbFirst => Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => Lsbfirst::MSBFIRST,
};
T::enable();
T::reset();
#[cfg(any(spi_v1, spi_f1))] #[cfg(any(spi_v1, spi_f1))]
unsafe { unsafe {
T::enable();
T::reset();
T::regs().cr2().modify(|w| { T::regs().cr2().modify(|w| {
w.set_ssoe(false); w.set_ssoe(false);
}); });
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_cpha( w.set_cpha(cpha);
match config.mode.phase == Phase::CaptureOnSecondTransition { w.set_cpol(cpol);
true => vals::Cpha::SECONDEDGE,
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_mstr(vals::Mstr::MASTER); w.set_mstr(vals::Mstr::MASTER);
w.set_br(vals::Br(br)); w.set_br(br);
w.set_spe(true); w.set_spe(true);
w.set_lsbfirst(match config.byte_order { w.set_lsbfirst(lsbfirst);
ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true); w.set_ssi(true);
w.set_ssm(true); w.set_ssm(true);
w.set_crcen(false); w.set_crcen(false);
@ -192,31 +201,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
} }
#[cfg(spi_v2)] #[cfg(spi_v2)]
unsafe { unsafe {
T::enable();
T::reset();
T::regs().cr2().modify(|w| { T::regs().cr2().modify(|w| {
w.set_frxth(WordSize::EightBit.frxth()); w.set_frxth(WordSize::EightBit.frxth());
w.set_ds(WordSize::EightBit.ds()); w.set_ds(WordSize::EightBit.ds());
w.set_ssoe(false); w.set_ssoe(false);
}); });
T::regs().cr1().modify(|w| { T::regs().cr1().modify(|w| {
w.set_cpha( w.set_cpha(cpha);
match config.mode.phase == Phase::CaptureOnSecondTransition { w.set_cpol(cpol);
true => vals::Cpha::SECONDEDGE,
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_mstr(vals::Mstr::MASTER); w.set_mstr(vals::Mstr::MASTER);
w.set_br(vals::Br(br)); w.set_br(br);
w.set_lsbfirst(match config.byte_order { w.set_lsbfirst(lsbfirst);
ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
});
w.set_ssi(true); w.set_ssi(true);
w.set_ssm(true); w.set_ssm(true);
w.set_crcen(false); w.set_crcen(false);
@ -226,26 +222,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
} }
#[cfg(spi_v3)] #[cfg(spi_v3)]
unsafe { unsafe {
T::enable();
T::reset();
T::regs().ifcr().write(|w| w.0 = 0xffff_ffff); T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
T::regs().cfg2().modify(|w| { T::regs().cfg2().modify(|w| {
//w.set_ssoe(true); //w.set_ssoe(true);
w.set_ssoe(false); w.set_ssoe(false);
w.set_cpha( w.set_cpha(cpha);
match config.mode.phase == Phase::CaptureOnSecondTransition { w.set_cpol(cpol);
true => vals::Cpha::SECONDEDGE, w.set_lsbfrst(lsbfirst);
false => vals::Cpha::FIRSTEDGE,
},
);
w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
true => vals::Cpol::IDLEHIGH,
false => vals::Cpol::IDLELOW,
});
w.set_lsbfrst(match config.byte_order {
ByteOrder::LsbFirst => vals::Lsbfrst::LSBFIRST,
ByteOrder::MsbFirst => vals::Lsbfrst::MSBFIRST,
});
w.set_ssm(true); w.set_ssm(true);
w.set_master(vals::Master::MASTER); w.set_master(vals::Master::MASTER);
w.set_comm(vals::Comm::FULLDUPLEX); w.set_comm(vals::Comm::FULLDUPLEX);
@ -257,7 +240,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
T::regs().cfg1().modify(|w| { T::regs().cfg1().modify(|w| {
w.set_crcen(false); w.set_crcen(false);
w.set_mbr(vals::Mbr(br)); w.set_mbr(br);
w.set_dsize(WordSize::EightBit.dsize()); w.set_dsize(WordSize::EightBit.dsize());
}); });
T::regs().cr2().modify(|w| { T::regs().cr2().modify(|w| {
@ -281,20 +264,6 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
} }
} }
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
}
}
fn set_word_size(&mut self, word_size: WordSize) { fn set_word_size(&mut self, word_size: WordSize) {
if self.current_word_size == word_size { if self.current_word_size == word_size {
return; return;
@ -355,6 +324,27 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
} }
} }
#[cfg(not(spi_v3))]
use vals::Br;
#[cfg(spi_v3)]
use vals::Mbr as Br;
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
let val = match clocks.0 / freq.0 {
0 => unreachable!(),
1..=2 => 0b000,
3..=5 => 0b001,
6..=11 => 0b010,
12..=23 => 0b011,
24..=39 => 0b100,
40..=95 => 0b101,
96..=191 => 0b110,
_ => 0b111,
};
Br(val)
}
trait RegsExt { trait RegsExt {
fn tx_ptr<W>(&self) -> *mut W; fn tx_ptr<W>(&self) -> *mut W;
fn rx_ptr<W>(&self) -> *mut W; fn rx_ptr<W>(&self) -> *mut W;