From b07325b47600283113ffb8aa99c50080ca092abb Mon Sep 17 00:00:00 2001 From: Bob McWhirter Date: Wed, 21 Jul 2021 16:45:43 -0400 Subject: [PATCH] Enable DMA for SPIv1 on F4's etc. --- embassy-stm32/src/dma/dma.rs | 5 +- embassy-stm32/src/spi/mod.rs | 4 +- embassy-stm32/src/spi/v1.rs | 211 ++++++++++++++++++++++++++-- examples/stm32f4/.cargo/config.toml | 3 +- examples/stm32f4/memory.x | 4 +- examples/stm32f4/src/bin/spi.rs | 3 + examples/stm32f4/src/bin/spi_dma.rs | 85 +++++++++++ 7 files changed, 299 insertions(+), 16 deletions(-) create mode 100644 examples/stm32f4/src/bin/spi_dma.rs diff --git a/embassy-stm32/src/dma/dma.rs b/embassy-stm32/src/dma/dma.rs index 72502043..c5695bac 100644 --- a/embassy-stm32/src/dma/dma.rs +++ b/embassy-stm32/src/dma/dma.rs @@ -98,16 +98,17 @@ pub(crate) unsafe fn do_transfer( w.set_tcie(true); #[cfg(dma_v1)] w.set_trbuff(true); - w.set_en(true); #[cfg(dma_v2)] w.set_chsel(request); + + w.set_en(true); }); } async move { let res = poll_fn(|cx| { - let n = channel_number as usize; + let n = state_number as usize; STATE.ch_wakers[n].register(cx.waker()); match STATE.ch_status[n].load(Ordering::Acquire) { CH_STATUS_NONE => Poll::Pending, diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs index 9bb5a729..237a0720 100644 --- a/embassy-stm32/src/spi/mod.rs +++ b/embassy-stm32/src/spi/mod.rs @@ -1,8 +1,8 @@ #![macro_use] #[cfg_attr(spi_v1, path = "v1.rs")] -#[cfg_attr(spi_v2, path = "v2.rs")] -#[cfg_attr(spi_v3, path = "v3.rs")] +//#[cfg_attr(spi_v2, path = "v2.rs")] +//#[cfg_attr(spi_v3, path = "v3.rs")] mod _version; use crate::{dma, peripherals, rcc::RccPeripheral}; pub use _version::*; diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs index 01cbf86b..72bde898 100644 --- a/embassy-stm32/src/spi/v1.rs +++ b/embassy-stm32/src/spi/v1.rs @@ -1,14 +1,21 @@ #![macro_use] +use crate::dma::NoDma; use crate::gpio::{sealed::Pin, AnyPin}; use crate::pac::spi; -use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; +use crate::spi::{ + ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel, + WordSize, +}; use crate::time::Hertz; +use core::future::Future; use core::marker::PhantomData; use core::ptr; use embassy::util::Unborrow; use embassy_extras::unborrow; +use embassy_traits::spi as traits; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; +use futures::future::join3; impl WordSize { fn dff(&self) -> spi::vals::Dff { @@ -19,27 +26,31 @@ impl WordSize { } } -pub struct Spi<'d, T: Instance> { +pub struct Spi<'d, T: Instance, Tx, Rx> { sck: AnyPin, mosi: AnyPin, miso: AnyPin, + txdma: Tx, + rxdma: Rx, current_word_size: WordSize, phantom: PhantomData<&'d mut T>, } -impl<'d, T: Instance> Spi<'d, T> { +impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { pub fn new( _peri: impl Unborrow + 'd, sck: impl Unborrow>, mosi: impl Unborrow>, miso: impl Unborrow>, + txdma: impl Unborrow, + rxdma: impl Unborrow, freq: F, config: Config, ) -> Self where F: Into, { - unborrow!(sck, mosi, miso); + unborrow!(sck, mosi, miso, txdma, rxdma); unsafe { sck.set_as_af(sck.af_num()); @@ -94,6 +105,8 @@ impl<'d, T: Instance> Spi<'d, T> { sck, mosi, miso, + txdma, + rxdma, current_word_size: WordSize::EightBit, phantom: PhantomData, } @@ -128,9 +141,150 @@ impl<'d, T: Instance> Spi<'d, T> { self.current_word_size = word_size; } } + + #[allow(unused)] + async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error> + where + Tx: TxDmaChannel, + { + unsafe { + T::regs().cr1().modify(|w| { + w.set_spe(false); + }); + T::regs().cr2().modify(|reg| { + reg.set_rxdmaen(true); + }); + } + self.set_word_size(WordSize::EightBit); + + let request = self.txdma.request(); + let dst = T::regs().dr().ptr() as *mut u8; + let f = self.txdma.write(request, write, dst); + + unsafe { + T::regs().cr2().modify(|reg| { + reg.set_txdmaen(true); + }); + T::regs().cr1().modify(|w| { + w.set_spe(true); + }); + } + + f.await; + Ok(()) + } + + #[allow(unused)] + async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error> + where + Tx: TxDmaChannel, + Rx: RxDmaChannel, + { + unsafe { + T::regs().cr1().modify(|w| { + w.set_spe(false); + }); + T::regs().cr2().modify(|reg| { + reg.set_rxdmaen(true); + }); + } + self.set_word_size(WordSize::EightBit); + + let clock_byte_count = read.len(); + + let rx_request = self.rxdma.request(); + let rx_src = T::regs().dr().ptr() as *mut u8; + let rx_f = self.rxdma.read(rx_request, rx_src, read); + + let tx_request = self.txdma.request(); + let tx_dst = T::regs().dr().ptr() as *mut u8; + let clock_byte = 0x00; + let tx_f = self + .txdma + .write_x(tx_request, &clock_byte, clock_byte_count, tx_dst); + + unsafe { + T::regs().cr2().modify(|reg| { + reg.set_txdmaen(true); + }); + T::regs().cr1().modify(|w| { + w.set_spe(true); + }); + } + + join3(tx_f, rx_f, Self::wait_for_idle()).await; + + unsafe { + T::regs().cr2().modify(|reg| { + reg.set_txdmaen(false); + reg.set_rxdmaen(false); + }); + T::regs().cr1().modify(|w| { + w.set_spe(false); + }); + } + + Ok(()) + } + + #[allow(unused)] + async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> + where + Tx: TxDmaChannel, + Rx: RxDmaChannel, + { + unsafe { + T::regs().cr1().modify(|w| { + w.set_spe(false); + }); + T::regs().cr2().modify(|reg| { + reg.set_rxdmaen(true); + }); + } + self.set_word_size(WordSize::EightBit); + + let rx_request = self.rxdma.request(); + let rx_src = T::regs().dr().ptr() as *mut u8; + let rx_f = self.rxdma.read(rx_request, rx_src, read); + + let tx_request = self.txdma.request(); + let tx_dst = T::regs().dr().ptr() as *mut u8; + let tx_f = self.txdma.write(tx_request, write, tx_dst); + + unsafe { + T::regs().cr2().modify(|reg| { + reg.set_txdmaen(true); + }); + T::regs().cr1().modify(|w| { + w.set_spe(true); + }); + } + + join3(tx_f, rx_f, Self::wait_for_idle()).await; + + unsafe { + T::regs().cr2().modify(|reg| { + reg.set_txdmaen(false); + reg.set_rxdmaen(false); + }); + T::regs().cr1().modify(|w| { + w.set_spe(false); + }); + } + + Ok(()) + } + + async fn wait_for_idle() { + unsafe { + while T::regs().sr().read().bsy() { + // spin + } + } + } } -impl<'d, T: Instance> Drop for Spi<'d, T> { +impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> { fn drop(&mut self) { unsafe { self.sck.set_as_analog(); @@ -140,7 +294,7 @@ impl<'d, T: Instance> Drop for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T, NoDma, NoDma> { type Error = Error; fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { @@ -176,7 +330,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T, NoDma, NoDma> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { @@ -217,7 +371,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T, NoDma, NoDma> { type Error = Error; fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { @@ -253,7 +407,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { } } -impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T, NoDma, NoDma> { type Error = Error; fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { @@ -291,3 +445,42 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> Ok(words) } } + +impl<'d, T: Instance, Tx, Rx> traits::Spi for Spi<'d, T, Tx, Rx> { + type Error = super::Error; +} + +impl<'d, T: Instance, Tx: TxDmaChannel, Rx> traits::Write for Spi<'d, T, Tx, Rx> { + #[rustfmt::skip] + type WriteFuture<'a> where Self: 'a = impl Future> + 'a; + + fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> { + self.write_dma_u8(data) + } +} + +impl<'d, T: Instance, Tx: TxDmaChannel, Rx: RxDmaChannel> traits::Read + for Spi<'d, T, Tx, Rx> +{ + #[rustfmt::skip] + type ReadFuture<'a> where Self: 'a = impl Future> + 'a; + + fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> { + self.read_dma_u8(data) + } +} + +impl<'d, T: Instance, Tx: TxDmaChannel, Rx: RxDmaChannel> traits::FullDuplex + for Spi<'d, T, Tx, Rx> +{ + #[rustfmt::skip] + type WriteReadFuture<'a> where Self: 'a = impl Future> + 'a; + + fn read_write<'a>( + &'a mut self, + read: &'a mut [u8], + write: &'a [u8], + ) -> Self::WriteReadFuture<'a> { + self.read_write_dma_u8(read, write) + } +} diff --git a/examples/stm32f4/.cargo/config.toml b/examples/stm32f4/.cargo/config.toml index 8704a9ba..f7173a19 100644 --- a/examples/stm32f4/.cargo/config.toml +++ b/examples/stm32f4/.cargo/config.toml @@ -3,7 +3,8 @@ build-std = ["core"] [target.'cfg(all(target_arch = "arm", target_os = "none"))'] # replace STM32F429ZITx with your chip as listed in `probe-run --list-chips` -runner = "probe-run --chip STM32F429ZITx" +#runner = "probe-run --chip STM32F429ZITx" +runner = "probe-run --chip STM32F401RE" rustflags = [ # LLD (shipped with the Rust toolchain) is used as the default linker diff --git a/examples/stm32f4/memory.x b/examples/stm32f4/memory.x index f21e3257..bcd2bbcd 100644 --- a/examples/stm32f4/memory.x +++ b/examples/stm32f4/memory.x @@ -2,6 +2,6 @@ MEMORY { /* NOTE 1 K = 1 KiBi = 1024 bytes */ /* These values correspond to the STM32F429ZI */ - FLASH : ORIGIN = 0x08000000, LENGTH = 2048K - RAM : ORIGIN = 0x20000000, LENGTH = 192K + FLASH : ORIGIN = 0x08000000, LENGTH = 512K + RAM : ORIGIN = 0x20000000, LENGTH = 96K } diff --git a/examples/stm32f4/src/bin/spi.rs b/examples/stm32f4/src/bin/spi.rs index 88fc84bc..60428387 100644 --- a/examples/stm32f4/src/bin/spi.rs +++ b/examples/stm32f4/src/bin/spi.rs @@ -18,6 +18,7 @@ use embassy_stm32::dbgmcu::Dbgmcu; use embassy_stm32::spi::{Config, Spi}; use embassy_stm32::time::Hertz; use embedded_hal::blocking::spi::Transfer; +use embassy_stm32::dma::NoDma; #[entry] fn main() -> ! { @@ -34,6 +35,8 @@ fn main() -> ! { p.PC10, p.PC12, p.PC11, + NoDma, + NoDma, Hertz(1_000_000), Config::default(), ); diff --git a/examples/stm32f4/src/bin/spi_dma.rs b/examples/stm32f4/src/bin/spi_dma.rs new file mode 100644 index 00000000..db6b69c8 --- /dev/null +++ b/examples/stm32f4/src/bin/spi_dma.rs @@ -0,0 +1,85 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] +#![allow(incomplete_features)] + +#[path = "../example_common.rs"] +mod example_common; +use core::fmt::Write; +use cortex_m_rt::entry; +use embassy::executor::Executor; +use embassy::time::Clock; +use embassy::util::Forever; +use example_common::*; +use embassy_traits::spi::FullDuplex; +use heapless::String; +use embassy_stm32::spi::{Spi, Config}; +use embassy_stm32::pac; +use embassy_stm32::time::Hertz; +use core::str::from_utf8; + +#[embassy::task] +async fn main_task() { + let p = embassy_stm32::init(Default::default()); + + let mut spi = Spi::new( + p.SPI1, + p.PB3, + p.PA7, + p.PA6, + p.DMA2_CH3, + p.DMA2_CH2, + Hertz(1_000_000), + Config::default(), + ); + + for n in 0u32.. { + let mut write: String<128> = String::new(); + let mut read = [0;128]; + core::write!(&mut write, "Hello DMA World {}!\r\n", n).unwrap(); + spi.read_write(&mut read[0..write.len()], write.as_bytes()).await.ok(); + info!("read via spi+dma: {}", from_utf8(&read).unwrap()); + } +} + +struct ZeroClock; + +impl Clock for ZeroClock { + fn now(&self) -> u64 { + 0 + } +} + +static EXECUTOR: Forever = Forever::new(); + +#[entry] +fn main() -> ! { + info!("Hello World!"); + unsafe { + pac::DBGMCU.cr().modify(|w| { + w.set_dbg_sleep(true); + w.set_dbg_standby(true); + w.set_dbg_stop(true); + }); + + pac::RCC.ahb1enr().modify(|w| { + w.set_gpioaen(true); + w.set_gpioben(true); + w.set_gpiocen(true); + w.set_gpioden(true); + w.set_gpioeen(true); + w.set_gpiofen(true); + }); + } + + unsafe { embassy::time::set_clock(&ZeroClock) }; + + let executor = EXECUTOR.put(Executor::new()); + + executor.run(|spawner| { + unwrap!(spawner.spawn(main_task())); + }) +}