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Fix AF pullup configuration for GPIOv1

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This commit is contained in:
chemicstry 2022-06-06 17:05:37 +03:00
parent 34673f52c9
commit b0ffd9a1cc
1 changed files with 19 additions and 8 deletions
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27
embassy-stm32/src/gpio.rs
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@ -424,9 +424,14 @@ pub(crate) mod sealed {
} }
} }
#[inline]
unsafe fn set_as_af(&self, af_num: u8, af_type: AFType) {
self.set_as_af_pull(af_num, af_type, Pull::None);
}
#[cfg(gpio_v1)] #[cfg(gpio_v1)]
#[inline] #[inline]
unsafe fn set_as_af(&self, _af_num: u8, af_type: AFType) { unsafe fn set_as_af_pull(&self, _af_num: u8, af_type: AFType, pull: Pull) {
// F1 uses the AFIO register for remapping. // F1 uses the AFIO register for remapping.
// For now, this is not implemented, so af_num is ignored // For now, this is not implemented, so af_num is ignored
// _af_num should be zero here, since it is not set by stm32-data // _af_num should be zero here, since it is not set by stm32-data
@ -435,9 +440,21 @@ pub(crate) mod sealed {
let crlh = if n < 8 { 0 } else { 1 }; let crlh = if n < 8 { 0 } else { 1 };
match af_type { match af_type {
AFType::Input => { AFType::Input => {
let cnf = match pull {
Pull::Up => {
r.bsrr().write(|w| w.set_bs(n, true));
vals::CnfIn::PULL
}
Pull::Down => {
r.bsrr().write(|w| w.set_br(n, true));
vals::CnfIn::PULL
}
Pull::None => vals::CnfIn::FLOATING,
};
r.cr(crlh).modify(|w| { r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::INPUT); w.set_mode(n % 8, vals::Mode::INPUT);
w.set_cnf_in(n % 8, vals::CnfIn::FLOATING); w.set_cnf_in(n % 8, cnf);
}); });
} }
AFType::OutputPushPull => { AFType::OutputPushPull => {
@ -455,12 +472,6 @@ pub(crate) mod sealed {
} }
} }
#[cfg(gpio_v2)]
#[inline]
unsafe fn set_as_af(&self, af_num: u8, af_type: AFType) {
self.set_as_af_pull(af_num, af_type, Pull::None);
}
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
#[inline] #[inline]
unsafe fn set_as_af_pull(&self, af_num: u8, af_type: AFType, pull: Pull) { unsafe fn set_as_af_pull(&self, af_num: u8, af_type: AFType, pull: Pull) {