rcc: ahb/apb -> hclk/pclk

embassy-stm32/Cargo.toml

@@ -58,7 +58,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-01a757e40df688efcda23607185640e1c2396ba9" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-01a757e40df688efcda23607185640e1c2396ba9", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/build.rs

@@ -466,7 +466,13 @@ fn main() {
 
             let ptype = if let Some(reg) = &p.registers { reg.kind } else { "" };
             let pname = format_ident!("{}", p.name);
-            let clk = format_ident!("{}", rcc.clock.to_ascii_lowercase());
+            let clk = format_ident!(
+                "{}",
+                rcc.clock
+                    .to_ascii_lowercase()
+                    .replace("ahb", "hclk")
+                    .replace("apb", "pclk")
+            );
             let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
             let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
 
@@ -523,7 +529,7 @@ fn main() {
                             let variant_name = format_ident!("{}", v.name);
                             let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
 
-                            if v.name.starts_with("AHB") || v.name.starts_with("APB") || v.name == "SYS" { 
+                            if v.name.starts_with("HCLK") || v.name.starts_with("PCLK") || v.name == "SYS" { 
                                 quote! {
                                     #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
                                 }

embassy-stm32/src/dac/mod.rs

@@ -564,7 +564,7 @@ foreach_peripheral!(
                 #[cfg(any(rcc_h7, rcc_h7rm0433))]
                 impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
                     fn frequency() -> crate::time::Hertz {
-                        critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
+                        critical_section::with(|_| unsafe { crate::rcc::get_freqs().pclk1 })
                     }
 
                     fn enable_and_reset_with_cs(_cs: critical_section::CriticalSection) {

embassy-stm32/src/eth/v1/mod.rs

@@ -191,7 +191,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         // TODO MTU size setting not found for v1 ethernet, check if correct
 
         // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
-        let hclk = unsafe { crate::rcc::get_freqs() }.ahb1;
+        let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
         let hclk_mhz = hclk.0 / 1_000_000;
 
         // Set the MDC clock frequency in the range 1MHz - 2.5MHz

embassy-stm32/src/eth/v2/mod.rs

@@ -164,7 +164,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         });
 
         // NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
-        let hclk = unsafe { crate::rcc::get_freqs() }.ahb1;
+        let hclk = unsafe { crate::rcc::get_freqs() }.hclk1;
         let hclk_mhz = hclk.0 / 1_000_000;
 
         // Set the MDC clock frequency in the range 1MHz - 2.5MHz

embassy-stm32/src/rcc/bd.rs

@@ -106,7 +106,7 @@ impl LsConfig {
 
     pub const fn off() -> Self {
         Self {
-            rtc: RtcClockSource::NOCLOCK,
+            rtc: RtcClockSource::DISABLE,
             lsi: false,
             lse: None,
         }
@@ -133,7 +133,7 @@ impl LsConfig {
                 Some(LSI_FREQ)
             }
             RtcClockSource::LSE => Some(self.lse.as_ref().unwrap().frequency),
-            RtcClockSource::NOCLOCK => None,
+            RtcClockSource::DISABLE => None,
             _ => todo!(),
         };
 
@@ -180,7 +180,7 @@ impl LsConfig {
         ok &= reg.rtcsel() == self.rtc;
         #[cfg(not(rcc_wba))]
         {
-            ok &= reg.rtcen() == (self.rtc != RtcClockSource::NOCLOCK);
+            ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
         }
         ok &= reg.lseon() == lse_en;
         ok &= reg.lsebyp() == lse_byp;
@@ -225,7 +225,7 @@ impl LsConfig {
             while !bdcr().read().lserdy() {}
         }
 
-        if self.rtc != RtcClockSource::NOCLOCK {
+        if self.rtc != RtcClockSource::DISABLE {
             bdcr().modify(|w| {
                 #[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
                 assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");

embassy-stm32/src/rcc/c0.rs

@@ -135,9 +135,9 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        apb1: apb_freq,
+        pclk1: apb_freq,
-        apb1_tim: apb_tim_freq,
+        pclk1_tim: apb_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/f0.rs

@@ -162,11 +162,11 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: Hertz(real_sysclk),
-        apb1: Hertz(pclk),
+        pclk1: Hertz(pclk),
-        apb2: Hertz(pclk),
+        pclk2: Hertz(pclk),
-        apb1_tim: Hertz(pclk * timer_mul),
+        pclk1_tim: Hertz(pclk * timer_mul),
-        apb2_tim: Hertz(pclk * timer_mul),
+        pclk2_tim: Hertz(pclk * timer_mul),
-        ahb1: Hertz(hclk),
+        hclk1: Hertz(hclk),
         rtc,
     });
 }

embassy-stm32/src/rcc/f1.rs

@@ -180,11 +180,11 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: Hertz(real_sysclk),
-        apb1: Hertz(pclk1),
+        pclk1: Hertz(pclk1),
-        apb2: Hertz(pclk2),
+        pclk2: Hertz(pclk2),
-        apb1_tim: Hertz(pclk1 * timer_mul1),
+        pclk1_tim: Hertz(pclk1 * timer_mul1),
-        apb2_tim: Hertz(pclk2 * timer_mul2),
+        pclk2_tim: Hertz(pclk2 * timer_mul2),
-        ahb1: Hertz(hclk),
+        hclk1: Hertz(hclk),
         adc: Some(Hertz(adcclk)),
         rtc,
     });

embassy-stm32/src/rcc/f2.rs

@@ -307,13 +307,13 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb3: ahb_freq,
+        hclk3: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         pll1_q: Some(pll_clocks.pll48_freq),
         rtc,
     });

embassy-stm32/src/rcc/f3.rs

@@ -281,11 +281,11 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sysclk,
-        apb1: pclk1,
+        pclk1: pclk1,
-        apb2: pclk2,
+        pclk2: pclk2,
-        apb1_tim: pclk1 * timer_mul1,
+        pclk1_tim: pclk1 * timer_mul1,
-        apb2_tim: pclk2 * timer_mul2,
+        pclk2_tim: pclk2 * timer_mul2,
-        ahb1: hclk,
+        hclk1: hclk,
         #[cfg(rcc_f3)]
         adc: adc,
         #[cfg(all(rcc_f3, adc3_common))]

embassy-stm32/src/rcc/f4.rs

@@ -340,15 +340,15 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: Hertz(sysclk),
-        apb1: Hertz(pclk1),
+        pclk1: Hertz(pclk1),
-        apb2: Hertz(pclk2),
+        pclk2: Hertz(pclk2),
 
-        apb1_tim: Hertz(pclk1 * timer_mul1),
+        pclk1_tim: Hertz(pclk1 * timer_mul1),
-        apb2_tim: Hertz(pclk2 * timer_mul2),
+        pclk2_tim: Hertz(pclk2 * timer_mul2),
 
-        ahb1: Hertz(hclk),
+        hclk1: Hertz(hclk),
-        ahb2: Hertz(hclk),
+        hclk2: Hertz(hclk),
-        ahb3: Hertz(hclk),
+        hclk3: Hertz(hclk),
 
         pll1_q: plls.pll48clk.map(Hertz),
 

embassy-stm32/src/rcc/f7.rs

@@ -259,15 +259,15 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: Hertz(sysclk),
-        apb1: Hertz(pclk1),
+        pclk1: Hertz(pclk1),
-        apb2: Hertz(pclk2),
+        pclk2: Hertz(pclk2),
 
-        apb1_tim: Hertz(pclk1 * timer_mul1),
+        pclk1_tim: Hertz(pclk1 * timer_mul1),
-        apb2_tim: Hertz(pclk2 * timer_mul2),
+        pclk2_tim: Hertz(pclk2 * timer_mul2),
 
-        ahb1: Hertz(hclk),
+        hclk1: Hertz(hclk),
-        ahb2: Hertz(hclk),
+        hclk2: Hertz(hclk),
-        ahb3: Hertz(hclk),
+        hclk3: Hertz(hclk),
 
         pll1_q: plls.pll48clk.map(Hertz),
 

embassy-stm32/src/rcc/g0.rs

@@ -89,7 +89,7 @@ impl Default for Config {
 impl PllConfig {
     pub(crate) fn init(self) -> Hertz {
         let (src, input_freq) = match self.source {
-            PllSrc::HSI16 => (vals::Pllsrc::HSI16, HSI_FREQ),
+            PllSrc::HSI16 => (vals::Pllsrc::HSI, HSI_FREQ),
             PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
         };
 
@@ -186,7 +186,7 @@ pub(crate) unsafe fn init(config: Config) {
         }
         ClockSrc::PLL(pll) => {
             let freq = pll.init();
-            (freq, Sw::PLLRCLK)
+            (freq, Sw::PLL1_R)
         }
         ClockSrc::LSI => {
             // Enable LSI
@@ -275,9 +275,9 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        apb1: apb_freq,
+        pclk1: apb_freq,
-        apb1_tim: apb_tim_freq,
+        pclk1_tim: apb_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/g4.rs

@@ -33,7 +33,7 @@ impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
             PllSrc::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI16 => Pllsrc::HSI16,
+            PllSrc::HSI16 => Pllsrc::HSI,
         }
     }
 }
@@ -201,7 +201,7 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
 
-            (HSI_FREQ, Sw::HSI16)
+            (HSI_FREQ, Sw::HSI)
         }
         ClockSrc::HSE(freq) => {
             // Enable HSE
@@ -249,7 +249,7 @@ pub(crate) unsafe fn init(config: Config) {
                 }
             }
 
-            (Hertz(freq), Sw::PLLRCLK)
+            (Hertz(freq), Sw::PLL1_R)
         }
     };
 
@@ -286,7 +286,7 @@ pub(crate) unsafe fn init(config: Config) {
                 let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
                 assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
 
-                crate::pac::rcc::vals::Clk48sel::PLLQCLK
+                crate::pac::rcc::vals::Clk48sel::PLL1_Q
             }
             Clock48MhzSrc::Hsi48(crs_config) => {
                 // Enable HSI48
@@ -348,12 +348,12 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         adc: adc12_ck,
         adc34: adc345_ck,
         pll1_p: None,

embassy-stm32/src/rcc/h.rs

@@ -387,7 +387,7 @@ pub(crate) unsafe fn init(config: Config) {
         Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
         Sysclk::HSE => (unwrap!(hse), Sw::HSE),
         Sysclk::CSI => (unwrap!(csi), Sw::CSI),
-        Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
+        Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1_P),
     };
 
     // Check limits.
@@ -445,7 +445,7 @@ pub(crate) unsafe fn init(config: Config) {
     };
     #[cfg(stm32h5)]
     let adc = match config.adc_clock_source {
-        AdcClockSource::HCLK => Some(hclk),
+        AdcClockSource::HCLK1 => Some(hclk),
         AdcClockSource::SYS => Some(sys),
         AdcClockSource::PLL2_R => pll2.r,
         AdcClockSource::HSE => hse,
@@ -524,19 +524,19 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys,
-        ahb1: hclk,
+        hclk1: hclk,
-        ahb2: hclk,
+        hclk2: hclk,
-        ahb3: hclk,
+        hclk3: hclk,
-        ahb4: hclk,
+        hclk4: hclk,
-        apb1,
+        pclk1: apb1,
-        apb2,
+        pclk2: apb2,
-        apb3,
+        pclk3: apb3,
         #[cfg(stm32h7)]
-        apb4,
+        pclk4: apb4,
         #[cfg(stm32h5)]
-        apb4: Hertz(1),
+        pclk4: Hertz(1),
-        apb1_tim,
+        pclk1_tim: apb1_tim,
-        apb2_tim,
+        pclk2_tim: apb2_tim,
         adc,
         rtc,
 

embassy-stm32/src/rcc/l0l1.rs

@@ -209,11 +209,11 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/l4.rs

@@ -329,13 +329,13 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb3: ahb_freq,
+        hclk3: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/l5.rs

@@ -261,13 +261,13 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb3: ahb_freq,
+        hclk3: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/mod.rs

@@ -48,21 +48,21 @@ pub struct Clocks {
     pub sys: Hertz,
 
     // APB
-    pub apb1: Hertz,
+    pub pclk1: Hertz,
-    pub apb1_tim: Hertz,
+    pub pclk1_tim: Hertz,
     #[cfg(not(any(rcc_c0, rcc_g0)))]
-    pub apb2: Hertz,
+    pub pclk2: Hertz,
     #[cfg(not(any(rcc_c0, rcc_g0)))]
-    pub apb2_tim: Hertz,
+    pub pclk2_tim: Hertz,
     #[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_u5))]
-    pub apb3: Hertz,
+    pub pclk3: Hertz,
     #[cfg(any(rcc_h7, rcc_h7rm0433, rcc_h7ab, stm32h5))]
-    pub apb4: Hertz,
+    pub pclk4: Hertz,
     #[cfg(any(rcc_wba))]
-    pub apb7: Hertz,
+    pub pclk7: Hertz,
 
     // AHB
-    pub ahb1: Hertz,
+    pub hclk1: Hertz,
     #[cfg(any(
         rcc_l4,
         rcc_l5,
@@ -82,7 +82,7 @@ pub struct Clocks {
         rcc_wl5,
         rcc_wle
     ))]
-    pub ahb2: Hertz,
+    pub hclk2: Hertz,
     #[cfg(any(
         rcc_l4,
         rcc_l5,
@@ -100,9 +100,9 @@ pub struct Clocks {
         rcc_wl5,
         rcc_wle
     ))]
-    pub ahb3: Hertz,
+    pub hclk3: Hertz,
     #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
-    pub ahb4: Hertz,
+    pub hclk4: Hertz,
 
     #[cfg(all(rcc_f4, not(stm32f410)))]
     pub plli2s1_q: Option<Hertz>,

embassy-stm32/src/rcc/u5.rs

@@ -436,14 +436,14 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb3: ahb_freq,
+        hclk3: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb3: apb3_freq,
+        pclk3: apb3_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/wb.rs

@@ -236,13 +236,13 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb1_clk,
+        hclk1: ahb1_clk,
-        ahb2: ahb2_clk,
+        hclk2: ahb2_clk,
-        ahb3: ahb3_clk,
+        hclk3: ahb3_clk,
-        apb1: apb1_clk,
+        pclk1: apb1_clk,
-        apb2: apb2_clk,
+        pclk2: apb2_clk,
-        apb1_tim: apb1_tim_clk,
+        pclk1_tim: apb1_tim_clk,
-        apb2_tim: apb2_tim_clk,
+        pclk2_tim: apb2_tim_clk,
         rtc,
     })
 }

embassy-stm32/src/rcc/wba.rs

@@ -142,14 +142,14 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb4: ahb_freq,
+        hclk4: ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb7: apb7_freq,
+        pclk7: apb7_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }

embassy-stm32/src/rcc/wl.rs

@@ -145,14 +145,14 @@ pub(crate) unsafe fn init(config: Config) {
 
     set_freqs(Clocks {
         sys: sys_clk,
-        ahb1: ahb_freq,
+        hclk1: ahb_freq,
-        ahb2: ahb_freq,
+        hclk2: ahb_freq,
-        ahb3: shd_ahb_freq,
+        hclk3: shd_ahb_freq,
-        apb1: apb1_freq,
+        pclk1: apb1_freq,
-        apb2: apb2_freq,
+        pclk2: apb2_freq,
-        apb3: shd_ahb_freq,
+        pclk3: shd_ahb_freq,
-        apb1_tim: apb1_tim_freq,
+        pclk1_tim: apb1_tim_freq,
-        apb2_tim: apb2_tim_freq,
+        pclk2_tim: apb2_tim_freq,
         rtc,
     });
 }