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Refactor DMA traits.

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This commit is contained in:
Matous Hybl
2021-11-19 19:15:55 +01:00
committed by Dario Nieuwenhuis
parent e2719aba10
commit b2910558d3
9 changed files with 591 additions and 559 deletions
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27
embassy-stm32/src/spi/v1.rs
View File

@ -20,7 +20,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let request = self.txdma.request();
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
let f = crate::dma::write(&mut self.txdma, request, write, dst);
unsafe {
T::regs().cr2().modify(|reg| {
@ -54,14 +54,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
let clock_byte = 0x00u8;
let tx_f = crate::dma::write_repeated(
&mut self.txdma,
tx_request,
clock_byte,
clock_byte_count,
tx_dst,
);
unsafe {
T::regs().cr2().modify(|reg| {
@ -110,13 +114,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let rx_f = crate::dma::read(
&mut self.rxdma,
rx_request,
rx_src,
&mut read[0..write.len()],
);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {

27
embassy-stm32/src/spi/v2.rs
View File

@ -24,7 +24,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let request = self.txdma.request();
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
let f = crate::dma::write(&mut self.txdma, request, write, dst);
unsafe {
T::regs().cr2().modify(|reg| {
@ -67,14 +67,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
let clock_byte = 0x00u8;
let tx_f = crate::dma::write_repeated(
&mut self.txdma,
tx_request,
clock_byte,
clock_byte_count,
tx_dst,
);
unsafe {
T::regs().cr2().modify(|reg| {
@ -128,13 +132,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let rx_f = crate::dma::read(
&mut self.rxdma,
rx_request,
rx_src,
&mut read[0..write.len()],
);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {

27
embassy-stm32/src/spi/v3.rs
View File

@ -24,7 +24,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let request = self.txdma.request();
let dst = T::regs().tx_ptr();
let f = self.txdma.write(request, write, dst);
let f = crate::dma::write(&mut self.txdma, request, write, dst);
unsafe {
T::regs().cfg1().modify(|reg| {
@ -70,14 +70,18 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let rx_f = crate::dma::read(&mut self.rxdma, rx_request, rx_src, read);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
let clock_byte = 0x00u8;
let tx_f = crate::dma::write_repeated(
&mut self.txdma,
tx_request,
clock_byte,
clock_byte_count,
tx_dst,
);
unsafe {
T::regs().cfg1().modify(|reg| {
@ -132,13 +136,16 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let rx_request = self.rxdma.request();
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
let rx_f = crate::dma::read(
&mut self.rxdma,
rx_request,
rx_src,
&mut read[0..write.len()],
);
let tx_request = self.txdma.request();
let tx_dst = T::regs().tx_ptr();
let tx_f = self.txdma.write(tx_request, write, tx_dst);
let tx_f = crate::dma::write(&mut self.txdma, tx_request, write, tx_dst);
unsafe {
T::regs().cfg1().modify(|reg| {