Fix RCC safety and add reset to DAC

This commit is contained in:
chemicstry
2022-03-18 01:11:57 +02:00
parent ca88ace98d
commit b30a42aff8
3 changed files with 43 additions and 23 deletions

View File

@ -7,16 +7,18 @@ use embedded_hal_02::blocking::delay::DelayUs;
pub const VDDA_CALIB_MV: u32 = 3000;
#[cfg(not(rcc_f4))]
unsafe fn enable() {
fn enable() {
todo!()
}
#[cfg(rcc_f4)]
unsafe fn enable() {
// TODO do not enable all adc clocks if not needed
crate::pac::RCC.apb2enr().modify(|w| w.set_adc1en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc2en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc3en(true));
fn enable() {
critical_section::with(|_| unsafe {
// TODO do not enable all adc clocks if not needed
crate::pac::RCC.apb2enr().modify(|w| w.set_adc1en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc2en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc3en(true));
});
}
pub enum Resolution {
@ -125,8 +127,8 @@ where
{
pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
unborrow!(_peri);
enable();
unsafe {
enable();
// disable before config is set
T::regs().cr2().modify(|reg| {
reg.set_adon(crate::pac::adc::vals::Adon::DISABLED);

View File

@ -8,13 +8,15 @@ pub const VDDA_CALIB_MV: u32 = 3000;
/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
/// configuration.
unsafe fn enable() {
#[cfg(stm32h7)]
crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
#[cfg(stm32g0)]
crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
#[cfg(stm32l4)]
crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
fn enable() {
critical_section::with(|_| unsafe {
#[cfg(stm32h7)]
crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
#[cfg(stm32g0)]
crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
#[cfg(stm32l4)]
crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
});
}
pub enum Resolution {
@ -206,8 +208,8 @@ pub struct Adc<'d, T: Instance> {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
unborrow!(_peri);
enable();
unsafe {
enable();
T::regs().cr().modify(|reg| {
#[cfg(not(adc_g0))]
reg.set_deeppwd(false);