Fix RCC safety and add reset to DAC
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@ -8,13 +8,15 @@ pub const VDDA_CALIB_MV: u32 = 3000;
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/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
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/// configuration.
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unsafe fn enable() {
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#[cfg(stm32h7)]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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#[cfg(stm32l4)]
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crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
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fn enable() {
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critical_section::with(|_| unsafe {
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#[cfg(stm32h7)]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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#[cfg(stm32l4)]
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crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
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});
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}
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pub enum Resolution {
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@ -206,8 +208,8 @@ pub struct Adc<'d, T: Instance> {
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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unborrow!(_peri);
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enable();
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unsafe {
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enable();
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T::regs().cr().modify(|reg| {
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#[cfg(not(adc_g0))]
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reg.set_deeppwd(false);
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