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Fix RCC safety and add reset to DAC

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This commit is contained in:
chemicstry 2022-03-18 01:11:57 +02:00
parent ca88ace98d
commit b30a42aff8
3 changed files with 43 additions and 23 deletions
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8
embassy-stm32/src/adc/v2.rs
View File

@ -7,16 +7,18 @@ use embedded_hal_02::blocking::delay::DelayUs;
pub const VDDA_CALIB_MV: u32 = 3000; pub const VDDA_CALIB_MV: u32 = 3000;
#[cfg(not(rcc_f4))] #[cfg(not(rcc_f4))]
unsafe fn enable() { fn enable() {
todo!() todo!()
} }
#[cfg(rcc_f4)] #[cfg(rcc_f4)]
unsafe fn enable() { fn enable() {
critical_section::with(|_| unsafe {
// TODO do not enable all adc clocks if not needed // TODO do not enable all adc clocks if not needed
crate::pac::RCC.apb2enr().modify(|w| w.set_adc1en(true)); crate::pac::RCC.apb2enr().modify(|w| w.set_adc1en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc2en(true)); crate::pac::RCC.apb2enr().modify(|w| w.set_adc2en(true));
crate::pac::RCC.apb2enr().modify(|w| w.set_adc3en(true)); crate::pac::RCC.apb2enr().modify(|w| w.set_adc3en(true));
});
} }
pub enum Resolution { pub enum Resolution {
@ -125,8 +127,8 @@ where
{ {
pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self { pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
unborrow!(_peri); unborrow!(_peri);
unsafe {
enable(); enable();
unsafe {
// disable before config is set // disable before config is set
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
reg.set_adon(crate::pac::adc::vals::Adon::DISABLED); reg.set_adon(crate::pac::adc::vals::Adon::DISABLED);

6
embassy-stm32/src/adc/v3.rs
View File

@ -8,13 +8,15 @@ pub const VDDA_CALIB_MV: u32 = 3000;
/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock /// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
/// configuration. /// configuration.
unsafe fn enable() { fn enable() {
critical_section::with(|_| unsafe {
#[cfg(stm32h7)] #[cfg(stm32h7)]
crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true)); crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
#[cfg(stm32g0)] #[cfg(stm32g0)]
crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true)); crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
#[cfg(stm32l4)] #[cfg(stm32l4)]
crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true)); crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
});
} }
pub enum Resolution { pub enum Resolution {
@ -206,8 +208,8 @@ pub struct Adc<'d, T: Instance> {
impl<'d, T: Instance> Adc<'d, T> { impl<'d, T: Instance> Adc<'d, T> {
pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self { pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
unborrow!(_peri); unborrow!(_peri);
unsafe {
enable(); enable();
unsafe {
T::regs().cr().modify(|reg| { T::regs().cr().modify(|reg| {
#[cfg(not(adc_g0))] #[cfg(not(adc_g0))]
reg.set_deeppwd(false); reg.set_deeppwd(false);

24
embassy-stm32/src/dac/v2.rs
View File

@ -91,6 +91,20 @@ pub struct Dac<'d, T: Instance> {
phantom: PhantomData<&'d mut T>, phantom: PhantomData<&'d mut T>,
} }
macro_rules! enable {
($enable_reg:ident, $enable_field: ident, $reset_reg:ident, $reset_field:ident) => {
crate::pac::RCC
.$enable_reg()
.modify(|w| w.$enable_field(true));
crate::pac::RCC
.$reset_reg()
.modify(|w| w.$reset_field(true));
crate::pac::RCC
.$reset_reg()
.modify(|w| w.$reset_field(false));
};
}
impl<'d, T: Instance> Dac<'d, T> { impl<'d, T: Instance> Dac<'d, T> {
pub fn new_1ch( pub fn new_1ch(
peri: impl Unborrow<Target = T> + 'd, peri: impl Unborrow<Target = T> + 'd,
@ -113,14 +127,16 @@ impl<'d, T: Instance> Dac<'d, T> {
unsafe { unsafe {
// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent DAC clock // Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent DAC clock
// configuration. // configuration.
critical_section::with(|_| {
#[cfg(rcc_h7)] #[cfg(rcc_h7)]
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true)); enable!(apb1lenr, set_dac12en, apb1lrstr, set_dac12rst);
#[cfg(rcc_h7ab)] #[cfg(rcc_h7ab)]
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac1en(true)); enable!(apb1lenr, set_dac1en, apb1lrstr, set_dac1rst);
#[cfg(stm32g0)] #[cfg(stm32g0)]
crate::pac::RCC.apbenr1().modify(|w| w.set_dac1en(true)); enable!(apbenr1, set_dac1en, apbrstr1, set_dac1rst);
#[cfg(stm32l4)] #[cfg(stm32l4)]
crate::pac::RCC.apb1enr1().modify(|w| w.set_dac1en(true)); enable!(apb1enr1, set_dac1en, apb1rstr1, set_dac1rst);
});
if channels >= 1 { if channels >= 1 {
T::regs().cr().modify(|reg| { T::regs().cr().modify(|reg| {