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Use the correct register names.

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This commit is contained in:
Bob McWhirter 2021-05-20 14:24:40 -04:00
parent 222faccbab
commit b3eda9914b
2 changed files with 6 additions and 6 deletions
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8
embassy-stm32/src/spi/v1.rs
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@ -152,7 +152,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T> {
// spin
}
unsafe {
let dr = regs.txdr().ptr() as *mut u8;
let dr = regs.dr().ptr() as *mut u8;
ptr::write_volatile(dr, *word);
}
loop {
@ -188,7 +188,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
// spin
}
unsafe {
let dr = regs.txdr().ptr() as *mut u8;
let dr = regs.dr().ptr() as *mut u8;
ptr::write_volatile(dr, *word);
}
@ -229,7 +229,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T> {
// spin
}
unsafe {
let dr = regs.txdr().ptr() as *mut u16;
let dr = regs.dr().ptr() as *mut u16;
ptr::write_volatile(dr, *word);
}
loop {
@ -265,7 +265,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
// spin
}
unsafe {
let dr = regs.txdr().ptr() as *mut u16;
let dr = regs.dr().ptr() as *mut u16;
ptr::write_volatile(dr, *word);
}
while unsafe { !regs.sr().read().rxne() } {

4
embassy-stm32/src/spi/v2.rs
View File

@ -220,7 +220,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T> {
}
}
unsafe {
let dr = regs.rxdr().ptr() as *const u8;
let dr = regs.dr().ptr() as *const u8;
*word = ptr::read_volatile(dr);
}
let sr = unsafe { regs.sr().read() };
@ -294,7 +294,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T>
// spin waiting for inbound to shift in.
}
unsafe {
let dr = regs.rxdr().ptr() as *const u16;
let dr = regs.dr().ptr() as *const u16;
*word = ptr::read_volatile(dr);
}
let sr = unsafe { regs.sr().read() };