max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

remove use of embedded-hal SPI traits. Instead just call our bus trait directly and push responsibility for implementing CS on the trait implementor

Browse Source
This commit is contained in:
kbleeke 2023-03-21 19:15:54 +01:00
parent a6a2a035d5
commit b4b8d82980
6 changed files with 59 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Cargo.toml
View File

@ -25,5 +25,4 @@ cortex-m-rt = "0.7.0"
futures = { version = "0.3.17", default-features = false, features = ["async-await", "cfg-target-has-atomic", "unstable"] }
embedded-hal-1 = { package = "embedded-hal", version = "1.0.0-alpha.9" }
embedded-hal-async = { version = "0.2.0-alpha.0" }
num_enum = { version = "0.5.7", default-features = false }

2
examples/rpi-pico-w/Cargo.toml
View File

@ -47,8 +47,6 @@ futures = { version = "0.3.17", default-features = false, features = [
pio-proc = "0.2"
pio = "0.2.1"
embedded-hal-1 = { package = "embedded-hal", version = "1.0.0-alpha.9" }
embedded-hal-async = { version = "0.2.0-alpha.0" }
embedded-io = { version = "0.4.0", features = ["async", "defmt"] }
heapless = "0.7.15"

60
examples/rpi-pico-w/src/main.rs
View File

@ -6,7 +6,7 @@
mod pio;
use core::convert::Infallible;
use core::slice;
use core::str::from_utf8;
use defmt::*;
@ -16,8 +16,6 @@ use embassy_net::{Config, Stack, StackResources};
use embassy_rp::gpio::{Flex, Level, Output};
use embassy_rp::peripherals::{DMA_CH0, PIN_23, PIN_24, PIN_25, PIN_29};
use embassy_rp::pio::{Pio0, PioPeripherial, PioStateMachineInstance, Sm0};
use embedded_hal_1::spi::ErrorType;
use embedded_hal_async::spi::{ExclusiveDevice, SpiBusFlush, SpiBusRead, SpiBusWrite};
use embedded_io::asynch::Write;
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
@ -37,7 +35,7 @@ async fn wifi_task(
runner: cyw43::Runner<
'static,
Output<'static, PIN_23>,
ExclusiveDevice<PioSpi<PioStateMachineInstance<Pio0, Sm0>, DMA_CH0>, Output<'static, PIN_25>>,
PioSpi<PIN_25, PioStateMachineInstance<Pio0, Sm0>, DMA_CH0>,
>,
) -> ! {
runner.run().await
@ -75,8 +73,7 @@ async fn main(spawner: Spawner) {
let (_, sm, _, _, _) = p.PIO0.split();
let dma = p.DMA_CH0;
let bus = PioSpi::new(sm, p.PIN_24, p.PIN_29, dma);
let spi = ExclusiveDevice::new(bus, cs);
let spi = PioSpi::new(sm, cs, p.PIN_24, p.PIN_29, dma);
let state = singleton!(cyw43::State::new());
let (net_device, mut control, runner) = cyw43::new(state, pwr, spi, fw).await;
@ -146,7 +143,6 @@ async fn main(spawner: Spawner) {
info!("rxd {}", from_utf8(&buf[..n]).unwrap());
match socket.write_all(&buf[..n]).await {
Ok(()) => {}
Err(e) => {
@ -168,31 +164,13 @@ struct MySpi {
/// - IRQ
/// - strap to set to gSPI mode on boot.
dio: Flex<'static, PIN_24>,
/// Chip select
cs: Output<'static, PIN_25>,
}
impl ErrorType for MySpi {
type Error = Infallible;
}
impl cyw43::SpiBusCyw43<u32> for MySpi {
async fn cmd_write<'a>(&'a mut self, write: &'a [u32]) -> Result<(), Self::Error> {
self.write(write).await
}
async fn cmd_read<'a>(&'a mut self, write: &'a [u32], read: &'a mut [u32]) -> Result<(), Self::Error> {
self.write(write).await?;
self.read(read).await
}
}
impl SpiBusFlush for MySpi {
async fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
}
impl SpiBusRead<u32> for MySpi {
async fn read(&mut self, words: &mut [u32]) -> Result<(), Self::Error> {
impl MySpi {
async fn read(&mut self, words: &mut [u32]) {
self.dio.set_as_input();
for word in words {
let mut w = 0;
@ -210,13 +188,9 @@ impl SpiBusRead<u32> for MySpi {
}
*word = w
}
Ok(())
}
}
impl SpiBusWrite<u32> for MySpi {
async fn write(&mut self, words: &[u32]) -> Result<(), Self::Error> {
async fn write(&mut self, words: &[u32]) {
self.dio.set_as_output();
for word in words {
let mut word = *word;
@ -238,6 +212,20 @@ impl SpiBusWrite<u32> for MySpi {
self.clk.set_low();
self.dio.set_as_input();
Ok(())
}
}
impl cyw43::SpiBusCyw43 for MySpi {
async fn cmd_write(&mut self, write: &[u32]) {
self.cs.set_low();
self.write(write).await;
self.cs.set_high();
}
async fn cmd_read(&mut self, write: u32, read: &mut [u32]) {
self.cs.set_low();
self.write(slice::from_ref(&write)).await;
self.read(read).await;
self.cs.set_high();
}
}

61
examples/rpi-pico-w/src/pio.rs
View File

@ -2,34 +2,27 @@ use core::slice;
use cyw43::SpiBusCyw43;
use embassy_rp::dma::Channel;
use embassy_rp::gpio::{Drive, Pin, Pull, SlewRate};
use embassy_rp::gpio::{Drive, Output, Pin, Pull, SlewRate};
use embassy_rp::pio::{PioStateMachine, ShiftDirection};
use embassy_rp::relocate::RelocatedProgram;
use embassy_rp::{pio_instr_util, Peripheral};
use embedded_hal_1::spi::ErrorType;
use embedded_hal_async::spi::SpiBusFlush;
use pio::Wrap;
use pio_proc::pio_asm;
pub struct PioSpi<SM, DMA> {
// cs: Output<'static, AnyPin>,
pub struct PioSpi<CS: Pin, SM, DMA> {
cs: Output<'static, CS>,
sm: SM,
dma: DMA,
wrap_target: u8,
}
impl<SM, DMA> PioSpi<SM, DMA>
impl<CS, SM, DMA> PioSpi<CS, SM, DMA>
where
SM: PioStateMachine,
DMA: Channel,
CS: Pin,
{
pub fn new<DIO, CLK>(
mut sm: SM,
// cs: AnyPin,
dio: DIO,
clk: CLK,
dma: DMA,
) -> Self
pub fn new<DIO, CLK>(mut sm: SM, cs: Output<'static, CS>, dio: DIO, clk: CLK, dma: DMA) -> Self
where
DIO: Pin,
CLK: Pin,
@ -105,7 +98,7 @@ where
pio_instr_util::set_pin(&mut sm, 0);
Self {
// cs: Output::new(cs, Level::High),
cs,
sm,
dma,
wrap_target: target,
@ -156,43 +149,21 @@ where
}
}
#[derive(Debug)]
pub enum PioError {}
impl embedded_hal_async::spi::Error for PioError {
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
embedded_hal_1::spi::ErrorKind::Other
}
}
impl<SM, DMA> ErrorType for PioSpi<SM, DMA>
where
SM: PioStateMachine,
{
type Error = PioError;
}
impl<SM, DMA> SpiBusFlush for PioSpi<SM, DMA>
where
SM: PioStateMachine,
{
async fn flush(&mut self) -> Result<(), Self::Error> {
Ok(())
}
}
impl<SM, DMA> SpiBusCyw43<u32> for PioSpi<SM, DMA>
impl<CS, SM, DMA> SpiBusCyw43 for PioSpi<CS, SM, DMA>
where
CS: Pin,
SM: PioStateMachine,
DMA: Channel,
{
async fn cmd_write<'a>(&'a mut self, write: &'a [u32]) -> Result<(), Self::Error> {
async fn cmd_write(&mut self, write: & [u32]) {
self.cs.set_low();
self.write(write).await;
Ok(())
self.cs.set_high();
}
async fn cmd_read<'a>(&'a mut self, write: &'a [u32], read: &'a mut [u32]) -> Result<(), Self::Error> {
self.cmd_read(write[0], read).await;
Ok(())
async fn cmd_read(&mut self, write: u32, read: & mut [u32]) {
self.cs.set_low();
self.cmd_read(write, read).await;
self.cs.set_high();
}
}

104
src/bus.rs
View File

@ -2,22 +2,22 @@ use core::slice;
use embassy_time::{Duration, Timer};
use embedded_hal_1::digital::OutputPin;
use embedded_hal_1::spi::ErrorType;
use embedded_hal_async::spi::{transaction, SpiDevice};
use futures::FutureExt;
use crate::consts::*;
/// Custom Spi Trait that _only_ supports the bus operation of the cyw43
pub trait SpiBusCyw43<Word: 'static + Copy>: ErrorType {
/// Implementors are expected to hold the CS pin low during an operation.
pub trait SpiBusCyw43 {
/// Issues a write command on the bus
/// Frist 32 bits of `word` are expected to be a cmd word
async fn cmd_write<'a>(&'a mut self, write: &'a [Word]) -> Result<(), Self::Error>;
/// First 32 bits of `word` are expected to be a cmd word
async fn cmd_write(&mut self, write: &[u32]);
/// Issues a read command on the bus
/// `write` is expected to be a 32 bit cmd word
/// `read` will contain the response of the device
async fn cmd_read<'a>(&'a mut self, write: &'a [Word], read: &'a mut [Word]) -> Result<(), Self::Error>;
///
async fn cmd_read(&mut self, write: u32, read: &mut [u32]);
}
pub(crate) struct Bus<PWR, SPI> {
@ -29,8 +29,7 @@ pub(crate) struct Bus<PWR, SPI> {
impl<PWR, SPI> Bus<PWR, SPI>
where
PWR: OutputPin,
SPI: SpiDevice,
SPI::Bus: SpiBusCyw43<u32>,
SPI: SpiBusCyw43,
{
pub(crate) fn new(pwr: PWR, spi: SPI) -> Self {
Self {
@ -87,14 +86,8 @@ where
pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) {
let cmd = cmd_word(READ, INC_ADDR, FUNC_WLAN, 0, len_in_u8);
let len_in_u32 = (len_in_u8 as usize + 3) / 4;
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd]).await?;
// bus.read(&mut buf[..len_in_u32]).await?;
bus.cmd_read(slice::from_ref(&cmd), &mut buf[..len_in_u32]).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_read(cmd, &mut buf[..len_in_u32]).await;
}
pub async fn wlan_write(&mut self, buf: &[u32]) {
@ -104,15 +97,7 @@ where
cmd_buf[0] = cmd;
cmd_buf[1..][..buf.len()].copy_from_slice(buf);
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd]).await?;
// bus.write(buf).await?;
bus.cmd_write(&cmd_buf).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_write(&cmd_buf).await;
}
#[allow(unused)]
@ -136,22 +121,7 @@ where
let cmd = cmd_word(READ, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd]).await?;
// // 4-byte response delay.
// let mut junk = [0; 1];
// bus.read(&mut junk).await?;
// // Read data
// bus.read(&mut buf[..(len + 3) / 4]).await?;
bus.cmd_read(slice::from_ref(&cmd), &mut buf[..(len + 3) / 4 + 1])
.await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_read(cmd, &mut buf[..(len + 3) / 4 + 1]).await;
data[..len].copy_from_slice(&slice8_mut(&mut buf[1..])[..len]);
@ -183,16 +153,7 @@ where
let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
buf[0] = cmd;
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd]).await?;
// bus.write(&buf[..(len + 3) / 4]).await?;
bus.cmd_write(&buf[..(len + 3) / 4 + 1]).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_write(&buf[..(len + 3) / 4 + 1]).await;
// Advance ptr.
addr += len as u32;
@ -307,19 +268,7 @@ where
let mut buf = [0; 2];
let len = if func == FUNC_BACKPLANE { 2 } else { 1 };
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd]).await?;
// if func == FUNC_BACKPLANE {
// // 4-byte response delay.
// bus.read(&mut buf).await?;
// }
// bus.read(&mut buf).await?;
bus.cmd_read(slice::from_ref(&cmd), &mut buf[..len]).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_read(cmd, &mut buf[..len]).await;
if func == FUNC_BACKPLANE {
buf[1]
@ -331,13 +280,7 @@ where
async fn writen(&mut self, func: u32, addr: u32, val: u32, len: u32) {
let cmd = cmd_word(WRITE, INC_ADDR, func, addr, len);
transaction!(&mut self.spi, |bus| async {
// bus.write(&[cmd, val]).await?;
bus.cmd_write(&[cmd, val]).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_write(&[cmd, val]).await;
}
async fn read32_swapped(&mut self, addr: u32) -> u32 {
@ -345,15 +288,7 @@ where
let cmd = swap16(cmd);
let mut buf = [0; 1];
transaction!(&mut self.spi, |bus| async {
// bus.write(&[swap16(cmd)]).await?;
// bus.read(&mut buf).await?;
bus.cmd_read(slice::from_ref(&cmd), &mut buf).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_read(cmd, &mut buf).await;
swap16(buf[0])
}
@ -362,14 +297,7 @@ where
let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BUS, addr, 4);
let buf = [swap16(cmd), swap16(val)];
transaction!(&mut self.spi, |bus| async {
// bus.write(&[swap16(cmd), swap16(val)]).await?;
bus.cmd_write(&buf).await?;
Ok(())
})
.await
.unwrap();
self.spi.cmd_write(&buf).await;
}
}

7
src/lib.rs
View File

@ -22,7 +22,6 @@ use embassy_futures::yield_now;
use embassy_net_driver_channel as ch;
use embassy_time::{block_for, Duration, Timer};
use embedded_hal_1::digital::OutputPin;
use embedded_hal_async::spi::SpiDevice;
use crate::bus::Bus;
pub use crate::bus::SpiBusCyw43;
@ -513,8 +512,7 @@ pub async fn new<'a, PWR, SPI>(
) -> (NetDriver<'a>, Control<'a>, Runner<'a, PWR, SPI>)
where
PWR: OutputPin,
SPI: SpiDevice,
SPI::Bus: SpiBusCyw43<u32>,
SPI: SpiBusCyw43,
{
let (ch_runner, device) = ch::new(&mut state.ch, [0; 6]);
let state_ch = ch_runner.state_runner();
@ -552,8 +550,7 @@ where
impl<'a, PWR, SPI> Runner<'a, PWR, SPI>
where
PWR: OutputPin,
SPI: SpiDevice,
SPI::Bus: SpiBusCyw43<u32>,
SPI: SpiBusCyw43,
{
async fn init(&mut self, firmware: &[u8]) {
self.bus.init().await;