Add support for generating PAC for dual cores
* Chips that have multiple cores will be exposed as chipname_corename, i.e. stm32wl55jc_cm4 * Chips that have single cores will use the chip family as feature name and pick the first and only core from the list * Add support for stm32wl55 chip family
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@ -19,10 +19,17 @@ data_path = '../stm32-data/data'
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try:
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_, chip_name, output_file = sys.argv
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except:
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raise Exception("Usage: gen.py STM32F429ZI path/to/generated.rs")
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raise Exception("Usage: gen.py STM32F429ZI_CM0 path/to/generated.rs")
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c = chip_name.split('_', 1)
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chip_name = c[0].upper()
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core_name = None
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if len(c) > 1:
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core_name = c[1].lower()
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# ======= load chip
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chip_name = chip_name.upper()
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with open(f'{data_path}/chips/{chip_name}.yaml', 'r') as f:
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chip = yaml.load(f, Loader=SafeLoader)
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@ -41,7 +48,13 @@ with open(output_file, 'w') as f:
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singletons.extend((f'EXTI{x}' for x in range(16)))
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num_dmas = 0
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for (name, peri) in chip['peripherals'].items():
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core = chip['cores'][0]
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if core_name != None:
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for c in chip['cores']:
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if core_name == c['name']:
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core = c
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for (name, peri) in core['peripherals'].items():
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if 'block' not in peri:
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continue
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