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Add support for generating PAC for dual cores

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* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
This commit is contained in:
Ulf Lilleengen
2021-06-16 15:12:07 +02:00
parent c9bf039cae
commit b6a8703698
12 changed files with 463 additions and 90 deletions
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93
stm32-metapac/Cargo.toml
View File

@ -778,23 +778,40 @@ stm32h743xg = []
stm32h743xi = []
stm32h743zg = []
stm32h743zi = []
stm32h745bg = []
stm32h745bi = []
stm32h745ig = []
stm32h745ii = []
stm32h745xg = []
stm32h745xi = []
stm32h745zg = []
stm32h745zi = []
stm32h747ag = []
stm32h747ai = []
stm32h747bg = []
stm32h747bi = []
stm32h747ig = []
stm32h747ii = []
stm32h747xg = []
stm32h747xi = []
stm32h747zi = []
stm32h745bg_cm7 = []
stm32h745bg_cm4 = []
stm32h745bi_cm7 = []
stm32h745bi_cm4 = []
stm32h745ig_cm7 = []
stm32h745ig_cm4 = []
stm32h745ii_cm7 = []
stm32h745ii_cm4 = []
stm32h745xg_cm7 = []
stm32h745xg_cm4 = []
stm32h745xi_cm7 = []
stm32h745xi_cm4 = []
stm32h745zg_cm7 = []
stm32h745zg_cm4 = []
stm32h745zi_cm7 = []
stm32h745zi_cm4 = []
stm32h747ag_cm7 = []
stm32h747ag_cm4 = []
stm32h747ai_cm7 = []
stm32h747ai_cm4 = []
stm32h747bg_cm7 = []
stm32h747bg_cm4 = []
stm32h747bi_cm7 = []
stm32h747bi_cm4 = []
stm32h747ig_cm7 = []
stm32h747ig_cm4 = []
stm32h747ii_cm7 = []
stm32h747ii_cm4 = []
stm32h747xg_cm7 = []
stm32h747xg_cm4 = []
stm32h747xi_cm7 = []
stm32h747xi_cm4 = []
stm32h747zi_cm7 = []
stm32h747zi_cm4 = []
stm32h750ib = []
stm32h750vb = []
stm32h750xb = []
@ -805,15 +822,24 @@ stm32h753ii = []
stm32h753vi = []
stm32h753xi = []
stm32h753zi = []
stm32h755bi = []
stm32h755ii = []
stm32h755xi = []
stm32h755zi = []
stm32h757ai = []
stm32h757bi = []
stm32h757ii = []
stm32h757xi = []
stm32h757zi = []
stm32h755bi_cm7 = []
stm32h755bi_cm4 = []
stm32h755ii_cm7 = []
stm32h755ii_cm4 = []
stm32h755xi_cm7 = []
stm32h755xi_cm4 = []
stm32h755zi_cm7 = []
stm32h755zi_cm4 = []
stm32h757ai_cm7 = []
stm32h757ai_cm4 = []
stm32h757bi_cm7 = []
stm32h757bi_cm4 = []
stm32h757ii_cm7 = []
stm32h757ii_cm4 = []
stm32h757xi_cm7 = []
stm32h757xi_cm4 = []
stm32h757zi_cm7 = []
stm32h757zi_cm4 = []
stm32h7a3ag = []
stm32h7a3ai = []
stm32h7a3ig = []
@ -1204,11 +1230,16 @@ stm32wb55ve = []
stm32wb55vg = []
stm32wb55vy = []
stm32wb5mmg = []
stm32wl54cc = []
stm32wl54jc = []
stm32wl55cc = []
stm32wl55jc = []
stm32wl55uc = []
stm32wl54cc_cm4 = []
stm32wl54cc_cm0p = []
stm32wl54jc_cm4 = []
stm32wl54jc_cm0p = []
stm32wl55cc_cm4 = []
stm32wl55cc_cm0p = []
stm32wl55jc_cm4 = []
stm32wl55jc_cm0p = []
stm32wl55uc_cm4 = []
stm32wl55uc_cm0p = []
stm32wle4c8 = []
stm32wle4cb = []
stm32wle4cc = []

89
stm32-metapac/gen/src/lib.rs
View File

@ -16,11 +16,16 @@ pub struct Chip {
pub name: String,
pub family: String,
pub line: String,
pub core: String,
pub cores: Vec<Core>,
pub flash: u32,
pub ram: u32,
pub gpio_af: String,
pub packages: Vec<Package>,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Core {
pub name: String,
pub peripherals: HashMap<String, Peripheral>,
pub interrupts: HashMap<String, u32>,
}
@ -153,13 +158,41 @@ pub fn gen(options: Options) {
println!("cwd: {:?}", env::current_dir());
let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
let mut chip_cores: HashMap<String, Option<String>> = HashMap::new();
for chip_name in &options.chips {
let mut s = chip_name.split('_');
let chip_name: &str = s.next().unwrap();
let core_name: Option<&str> = s.next();
chip_cores.insert(
chip_name.to_string(),
core_name.map(|s| s.to_ascii_lowercase().to_string()),
);
let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
println!("chip_path: {:?}", chip_path);
let chip = fs::read(chip_path).unwrap();
let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
println!("looking for core {:?}", core_name);
let core: Option<&Core> = if let Some(core_name) = core_name {
let core_name = core_name.to_ascii_lowercase();
let mut c = None;
for core in chip.cores.iter() {
if core.name == core_name {
c = Some(core);
break;
}
}
c
} else {
Some(&chip.cores[0])
};
let core = core.unwrap();
let core_name = &core.name;
let mut ir = ir::IR::new();
let mut dev = ir::Device {
@ -168,7 +201,7 @@ pub fn gen(options: Options) {
};
// Load RCC register for chip
let rcc = chip.peripherals.iter().find_map(|(name, p)| {
let rcc = core.peripherals.iter().find_map(|(name, p)| {
if name == "RCC" {
p.block.as_ref().map(|block| {
let bi = BlockInfo::parse(block);
@ -189,17 +222,17 @@ pub fn gen(options: Options) {
let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
let dma_base = chip
let dma_base = core
.peripherals
.get(&"DMA".to_string())
.unwrap_or_else(|| chip.peripherals.get(&"DMA1".to_string()).unwrap())
.unwrap_or_else(|| core.peripherals.get(&"DMA1".to_string()).unwrap())
.address;
let dma_stride = 0x400;
let gpio_base = chip.peripherals.get(&"GPIOA".to_string()).unwrap().address;
let gpio_base = core.peripherals.get(&"GPIOA".to_string()).unwrap().address;
let gpio_stride = 0x400;
for (name, p) in &chip.peripherals {
for (name, p) in &core.peripherals {
let mut ir_peri = ir::Peripheral {
name: name.clone(),
array: None,
@ -338,7 +371,7 @@ pub fn gen(options: Options) {
dev.peripherals.push(ir_peri);
}
for (name, &num) in &chip.interrupts {
for (name, &num) in &core.interrupts {
dev.interrupts.push(ir::Interrupt {
name: name.clone(),
description: None,
@ -386,9 +419,17 @@ pub fn gen(options: Options) {
transform::sort::Sort {}.run(&mut ir).unwrap();
transform::Sanitize {}.run(&mut ir).unwrap();
let chip_dir = out_dir
.join("src/chips")
.join(chip_name.to_ascii_lowercase());
let chip_dir = if chip.cores.len() > 1 {
out_dir.join("src/chips").join(format!(
"{}_{}",
chip_name.to_ascii_lowercase(),
core_name.to_ascii_lowercase()
))
} else {
out_dir
.join("src/chips")
.join(chip_name.to_ascii_lowercase())
};
fs::create_dir_all(&chip_dir).unwrap();
let items = generate::render(&ir, &generate_opts).unwrap();
@ -403,7 +444,7 @@ pub fn gen(options: Options) {
let mut device_x = String::new();
for (name, _) in &chip.interrupts {
for (name, _) in &core.interrupts {
write!(
&mut device_x,
"PROVIDE({} = DefaultHandler);\n",
@ -462,14 +503,24 @@ pub fn gen(options: Options) {
let librs = include_bytes!("assets/lib_inner.rs");
let i = bytes_find(librs, PATHS_MARKER).unwrap();
let mut paths = String::new();
for chip_name in &options.chips {
let x = chip_name.to_ascii_lowercase();
write!(
&mut paths,
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
x, x
)
.unwrap();
for (chip, cores) in chip_cores.iter() {
let x = chip.to_ascii_lowercase();
if let Some(c) = cores {
write!(
&mut paths,
"#[cfg_attr(feature=\"{}_{}\", path = \"chips/{}_{}/pac.rs\")]",
x, c, x, c
)
.unwrap();
} else {
write!(
&mut paths,
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
x, x
)
.unwrap();
}
}
let mut contents: Vec<u8> = Vec::new();
contents.extend(&librs[..i]);

14
stm32-metapac/gen_features.py
View File

@ -8,6 +8,11 @@ import toml
from collections import OrderedDict
from glob import glob
try:
from yaml import CSafeLoader as SafeLoader
except ImportError:
from yaml import SafeLoader
abspath = os.path.abspath(__file__)
dname = os.path.dirname(abspath)
os.chdir(dname)
@ -19,8 +24,13 @@ features = {}
for f in sorted(glob('../stm32-data/data/chips/*.yaml')):
# Use the filename to get the chip name. Ultra fast, we don't have to read YAML!
name = os.path.splitext(os.path.basename(f))[0].lower()
features[name] = []
with open(f, 'r') as f:
chip = yaml.load(f, Loader=SafeLoader)
if len(chip['cores']) > 1:
for core in chip['cores']:
features[name + "_" + core['name']] = []
else:
features[name] = []
# ========= Update Cargo features