From b6b20eda8cb1e49c55bc091209a38cc210d3ad40 Mon Sep 17 00:00:00 2001
From: Brandon Ros <brandonros1@gmail.com>
Date: Sun, 20 Aug 2023 18:22:06 -0400
Subject: [PATCH] try to match C as closely as possible

---
 cyw43/src/bus.rs    |  9 +++++++--
 cyw43/src/consts.rs | 22 ++++++++++++++++++----
 2 files changed, 25 insertions(+), 6 deletions(-)

diff --git a/cyw43/src/bus.rs b/cyw43/src/bus.rs
index bf16ed50..46352692 100644
--- a/cyw43/src/bus.rs
+++ b/cyw43/src/bus.rs
@@ -75,11 +75,16 @@ where
         trace!("{:#010b}", (val & 0xff));
 
         // 32-bit word length, little endian (which is the default endianess).
-        // TODO: C library is uint32_t val = WORD_LENGTH_32 | ENDIAN_BIG | HIGH_SPEED_MODE | INTERRUPT_POLARITY_HIGH | WAKE_UP | 0x4 << (8 * SPI_RESPONSE_DELAY) | INTR_WITH_STATUS << (8 * SPI_STATUS_ENABLE);
+        // TODO: C library is uint32_t val = WORD_LENGTH_32 | HIGH_SPEED_MODE| ENDIAN_BIG | INTERRUPT_POLARITY_HIGH | WAKE_UP | 0x4 << (8 * SPI_RESPONSE_DELAY) | INTR_WITH_STATUS << (8 * SPI_STATUS_ENABLE);
         debug!("write REG_BUS_CTRL");
         self.write32_swapped(
             REG_BUS_CTRL,
-            WORD_LENGTH_32 | HIGH_SPEED | INTERRUPT_HIGH | WAKE_UP | STATUS_ENABLE | INTERRUPT_WITH_STATUS,
+            WORD_LENGTH_32
+                | HIGH_SPEED
+                | INTERRUPT_POLARITY_HIGH
+                | WAKE_UP
+                | 0x4 << (8 * REG_BUS_RESPONSE_DELAY)
+                | INTR_WITH_STATUS << (8 * REG_BUS_STATUS_ENABLE),
         )
         .await;
 
diff --git a/cyw43/src/consts.rs b/cyw43/src/consts.rs
index 43485c38..e845f19d 100644
--- a/cyw43/src/consts.rs
+++ b/cyw43/src/consts.rs
@@ -5,19 +5,33 @@ pub(crate) const FUNC_BACKPLANE: u32 = 1;
 pub(crate) const FUNC_WLAN: u32 = 2;
 pub(crate) const FUNC_BT: u32 = 3;
 
+// Register addresses
 pub(crate) const REG_BUS_CTRL: u32 = 0x0;
+pub(crate) const REG_BUS_RESPONSE_DELAY: u32 = 0x1;
+pub(crate) const REG_BUS_STATUS_ENABLE: u32 = 0x2;
 pub(crate) const REG_BUS_INTERRUPT: u32 = 0x04; // 16 bits - Interrupt status
 pub(crate) const REG_BUS_INTERRUPT_ENABLE: u32 = 0x06; // 16 bits - Interrupt mask
 pub(crate) const REG_BUS_STATUS: u32 = 0x8;
 pub(crate) const REG_BUS_TEST_RO: u32 = 0x14;
 pub(crate) const REG_BUS_TEST_RW: u32 = 0x18;
 pub(crate) const REG_BUS_RESP_DELAY: u32 = 0x1c;
+
+// SPI_BUS_CONTROL Bits
 pub(crate) const WORD_LENGTH_32: u32 = 0x1;
+pub(crate) const ENDIAN_BIG: u32 = 0x2;
+pub(crate) const CLOCK_PHASE: u32 = 0x4;
+pub(crate) const CLOCK_POLARITY: u32 = 0x8;
 pub(crate) const HIGH_SPEED: u32 = 0x10;
-pub(crate) const INTERRUPT_HIGH: u32 = 1 << 5;
-pub(crate) const WAKE_UP: u32 = 1 << 7;
-pub(crate) const STATUS_ENABLE: u32 = 1 << 16;
-pub(crate) const INTERRUPT_WITH_STATUS: u32 = 1 << 17;
+pub(crate) const INTERRUPT_POLARITY_HIGH: u32 = 0x20;
+pub(crate) const WAKE_UP: u32 = 0x80;
+
+// SPI_STATUS_ENABLE bits
+pub(crate) const STATUS_ENABLE: u32 = 0x01;
+pub(crate) const INTR_WITH_STATUS: u32 = 0x02;
+pub(crate) const RESP_DELAY_ALL: u32 = 0x04;
+pub(crate) const DWORD_PKT_LEN_EN: u32 = 0x08;
+pub(crate) const CMD_ERR_CHK_EN: u32 = 0x20;
+pub(crate) const DATA_ERR_CHK_EN: u32 = 0x40;
 
 // SPI_STATUS_REGISTER bits
 pub(crate) const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001;