From b6fc19182b4ae02ea1e9107ca28b88f4a3b0b60a Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <lulf@redhat.com>
Date: Thu, 23 Sep 2021 14:43:17 +0200
Subject: [PATCH] Add pwr for L1 and update RCC to new reg block

---
 embassy-stm32/src/pwr/l1.rs     |  1 +
 embassy-stm32/src/pwr/mod.rs    |  1 +
 embassy-stm32/src/rcc/l1/mod.rs | 43 +++++++++++++++++----------------
 stm32-data                      |  2 +-
 4 files changed, 25 insertions(+), 22 deletions(-)
 create mode 100644 embassy-stm32/src/pwr/l1.rs

diff --git a/embassy-stm32/src/pwr/l1.rs b/embassy-stm32/src/pwr/l1.rs
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/embassy-stm32/src/pwr/l1.rs
@@ -0,0 +1 @@
+
diff --git a/embassy-stm32/src/pwr/mod.rs b/embassy-stm32/src/pwr/mod.rs
index b19ab326..37f7e572 100644
--- a/embassy-stm32/src/pwr/mod.rs
+++ b/embassy-stm32/src/pwr/mod.rs
@@ -2,6 +2,7 @@
 #[cfg_attr(pwr_f4, path = "f4.rs")]
 #[cfg_attr(pwr_wl5, path = "wl5.rs")]
 #[cfg_attr(pwr_g0, path = "g0.rs")]
+#[cfg_attr(pwr_l1, path = "l1.rs")]
 mod _version;
 
 pub use _version::*;
diff --git a/embassy-stm32/src/rcc/l1/mod.rs b/embassy-stm32/src/rcc/l1/mod.rs
index 25b5609c..f6edd4e4 100644
--- a/embassy-stm32/src/rcc/l1/mod.rs
+++ b/embassy-stm32/src/rcc/l1/mod.rs
@@ -7,7 +7,6 @@ use crate::time::U32Ext;
 use core::marker::PhantomData;
 use embassy::util::Unborrow;
 use embassy_hal_common::unborrow;
-use pac::rcc::vals::{Hpre, Ppre, Sw};
 
 /// Most of clock setup is copied from rcc/l0
 
@@ -22,30 +21,32 @@ pub enum ClockSrc {
     HSI,
 }
 
+type Ppre = u8;
 impl Into<Ppre> for APBPrescaler {
     fn into(self) -> Ppre {
         match self {
-            APBPrescaler::NotDivided => Ppre::DIV1,
-            APBPrescaler::Div2 => Ppre::DIV2,
-            APBPrescaler::Div4 => Ppre::DIV4,
-            APBPrescaler::Div8 => Ppre::DIV8,
-            APBPrescaler::Div16 => Ppre::DIV16,
+            APBPrescaler::NotDivided => 0b000,
+            APBPrescaler::Div2 => 0b100,
+            APBPrescaler::Div4 => 0b101,
+            APBPrescaler::Div8 => 0b110,
+            APBPrescaler::Div16 => 0b111,
         }
     }
 }
 
+type Hpre = u8;
 impl Into<Hpre> for AHBPrescaler {
     fn into(self) -> Hpre {
         match self {
-            AHBPrescaler::NotDivided => Hpre::DIV1,
-            AHBPrescaler::Div2 => Hpre::DIV2,
-            AHBPrescaler::Div4 => Hpre::DIV4,
-            AHBPrescaler::Div8 => Hpre::DIV8,
-            AHBPrescaler::Div16 => Hpre::DIV16,
-            AHBPrescaler::Div64 => Hpre::DIV64,
-            AHBPrescaler::Div128 => Hpre::DIV128,
-            AHBPrescaler::Div256 => Hpre::DIV256,
-            AHBPrescaler::Div512 => Hpre::DIV512,
+            AHBPrescaler::NotDivided => 0b0000,
+            AHBPrescaler::Div2 => 0b1000,
+            AHBPrescaler::Div4 => 0b1001,
+            AHBPrescaler::Div8 => 0b1010,
+            AHBPrescaler::Div16 => 0b1011,
+            AHBPrescaler::Div64 => 0b1100,
+            AHBPrescaler::Div128 => 0b1101,
+            AHBPrescaler::Div256 => 0b1110,
+            AHBPrescaler::Div512 => 0b1111,
         }
     }
 }
@@ -157,7 +158,7 @@ impl RccExt for RCC {
                 }
 
                 let freq = 32_768 * (1 << (range as u8 + 1));
-                (freq, Sw::MSI)
+                (freq, 0b00)
             }
             ClockSrc::HSI => {
                 // Enable HSI
@@ -166,7 +167,7 @@ impl RccExt for RCC {
                     while !rcc.cr().read().hsirdy() {}
                 }
 
-                (HSI_FREQ, Sw::HSI)
+                (HSI_FREQ, 0b01)
             }
             ClockSrc::HSE(freq) => {
                 // Enable HSE
@@ -175,7 +176,7 @@ impl RccExt for RCC {
                     while !rcc.cr().read().hserdy() {}
                 }
 
-                (freq.0, Sw::HSE)
+                (freq.0, 0b10)
             }
         };
 
@@ -192,7 +193,7 @@ impl RccExt for RCC {
             AHBPrescaler::NotDivided => sys_clk,
             pre => {
                 let pre: Hpre = pre.into();
-                let pre = 1 << (pre.0 as u32 - 7);
+                let pre = 1 << (pre as u32 - 7);
                 sys_clk / pre
             }
         };
@@ -201,7 +202,7 @@ impl RccExt for RCC {
             APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
             pre => {
                 let pre: Ppre = pre.into();
-                let pre: u8 = 1 << (pre.0 - 3);
+                let pre: u8 = 1 << (pre - 3);
                 let freq = ahb_freq / pre as u32;
                 (freq, freq * 2)
             }
@@ -211,7 +212,7 @@ impl RccExt for RCC {
             APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
             pre => {
                 let pre: Ppre = pre.into();
-                let pre: u8 = 1 << (pre.0 - 3);
+                let pre: u8 = 1 << (pre - 3);
                 let freq = ahb_freq / (1 << (pre as u8 - 3));
                 (freq, freq * 2)
             }
diff --git a/stm32-data b/stm32-data
index 7f5f8e7c..18df8200 160000
--- a/stm32-data
+++ b/stm32-data
@@ -1 +1 @@
-Subproject commit 7f5f8e7c641d74a0e97e2d84bac61b7c6c267a7e
+Subproject commit 18df82005f29da14e7d4c442f7cff3a46939c434