Merge upstream

This commit is contained in:
Henrik Alsér 2022-07-08 23:37:35 +02:00
commit b72ba0a6c4
2 changed files with 118 additions and 0 deletions

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@ -1,4 +1,21 @@
//! Blocking shared I2C bus //! Blocking shared I2C bus
//!
//! # Example (nrf52)
//!
//! ```rust
//! use embassy_embedded_hal::shared_bus::blocking::i2c::I2cBusDevice;
//! use embassy::blocking_mutex::{NoopMutex, raw::NoopRawMutex};
//!
//! static I2C_BUS: Forever<NoopMutex<RefCell<Twim<TWISPI0>>>> = Forever::new();
//! let irq = interrupt::take!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
//! let i2c = Twim::new(p.TWISPI0, irq, p.P0_03, p.P0_04, Config::default());
//! let i2c_bus = NoopMutex::new(RefCell::new(i2c));
//! let i2c_bus = I2C_BUS.put(i2c_bus);
//!
//! let i2c_dev1 = I2cBusDevice::new(i2c_bus);
//! let mpu = Mpu6050::new(i2c_dev1);
//! ```
use core::cell::RefCell; use core::cell::RefCell;
use embassy::blocking_mutex::raw::RawMutex; use embassy::blocking_mutex::raw::RawMutex;
@ -84,6 +101,7 @@ where
} }
} }
<<<<<<< HEAD
pub struct I2cBusDeviceWithConfig<'a, M: RawMutex, BUS, C> { pub struct I2cBusDeviceWithConfig<'a, M: RawMutex, BUS, C> {
bus: &'a Mutex<M, RefCell<BUS>>, bus: &'a Mutex<M, RefCell<BUS>>,
config: C, config: C,
@ -165,4 +183,46 @@ where
let _ = operations; let _ = operations;
todo!() todo!()
} }
=======
impl<'a, M, BUS, E> embedded_hal_02::blocking::i2c::Write for I2cBusDevice<'_, M, BUS>
where
M: RawMutex,
BUS: embedded_hal_02::blocking::i2c::Write<Error = E>,
{
type Error = I2cBusDeviceError<E>;
fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Self::Error> {
self.bus
.lock(|bus| bus.borrow_mut().write(addr, bytes).map_err(I2cBusDeviceError::I2c))
}
}
impl<'a, M, BUS, E> embedded_hal_02::blocking::i2c::Read for I2cBusDevice<'_, M, BUS>
where
M: RawMutex,
BUS: embedded_hal_02::blocking::i2c::Read<Error = E>,
{
type Error = I2cBusDeviceError<E>;
fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Self::Error> {
self.bus
.lock(|bus| bus.borrow_mut().read(addr, bytes).map_err(I2cBusDeviceError::I2c))
}
}
impl<'a, M, BUS, E> embedded_hal_02::blocking::i2c::WriteRead for I2cBusDevice<'_, M, BUS>
where
M: RawMutex,
BUS: embedded_hal_02::blocking::i2c::WriteRead<Error = E>,
{
type Error = I2cBusDeviceError<E>;
fn write_read<'w>(&mut self, addr: u8, bytes: &'w [u8], buffer: &'w mut [u8]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
bus.borrow_mut()
.write_read(addr, bytes, buffer)
.map_err(I2cBusDeviceError::I2c)
})
}
>>>>>>> master
} }

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@ -1,4 +1,23 @@
//! Blocking shared SPI bus //! Blocking shared SPI bus
//!
//! # Example (nrf52)
//!
//! ```rust
//! use embassy_embedded_hal::shared_bus::blocking::spi::SpiBusDevice;
//! use embassy::blocking_mutex::{NoopMutex, raw::NoopRawMutex};
//!
//! static SPI_BUS: Forever<NoopMutex<RefCell<Spim<SPI3>>>> = Forever::new();
//! let irq = interrupt::take!(SPIM3);
//! let spi = Spim::new_txonly(p.SPI3, irq, p.P0_15, p.P0_18, Config::default());
//! let spi_bus = NoopMutex::new(RefCell::new(spi));
//! let spi_bus = SPI_BUS.put(spi_bus);
//!
//! // Device 1, using embedded-hal compatible driver for ST7735 LCD display
//! let cs_pin1 = Output::new(p.P0_24, Level::Low, OutputDrive::Standard);
//! let spi_dev1 = SpiBusDevice::new(spi_bus, cs_pin1);
//! let display1 = ST7735::new(spi_dev1, dc1, rst1, Default::default(), false, 160, 128);
//! ```
use core::cell::RefCell; use core::cell::RefCell;
use embassy::blocking_mutex::raw::RawMutex; use embassy::blocking_mutex::raw::RawMutex;
@ -57,6 +76,7 @@ where
} }
} }
<<<<<<< HEAD
pub struct SpiBusDeviceWithConfig<'a, M: RawMutex, BUS, CS, C> { pub struct SpiBusDeviceWithConfig<'a, M: RawMutex, BUS, CS, C> {
bus: &'a Mutex<M, RefCell<BUS>>, bus: &'a Mutex<M, RefCell<BUS>>,
cs: CS, cs: CS,
@ -101,6 +121,44 @@ where
flush_res.map_err(SpiBusDeviceError::Spi)?; flush_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiBusDeviceError::Cs)?; cs_res.map_err(SpiBusDeviceError::Cs)?;
=======
impl<'d, M, BUS, CS, BusErr, CsErr> embedded_hal_02::blocking::spi::Transfer<u8> for SpiBusDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: embedded_hal_02::blocking::spi::Transfer<u8, Error = BusErr>,
CS: OutputPin<Error = CsErr>,
{
type Error = SpiBusDeviceError<BusErr, CsErr>;
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
let f_res = bus.transfer(words);
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiBusDeviceError::Cs)?;
Ok(f_res)
})
}
}
impl<'d, M, BUS, CS, BusErr, CsErr> embedded_hal_02::blocking::spi::Write<u8> for SpiBusDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: embedded_hal_02::blocking::spi::Write<u8, Error = BusErr>,
CS: OutputPin<Error = CsErr>,
{
type Error = SpiBusDeviceError<BusErr, CsErr>;
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiBusDeviceError::Cs)?;
let f_res = bus.write(words);
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiBusDeviceError::Spi)?;
cs_res.map_err(SpiBusDeviceError::Cs)?;
>>>>>>> master
Ok(f_res) Ok(f_res)
}) })
} }