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Merge #762

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762: Allow maximal clock for F7 HCLK r=Dirbaio a=matoushybl

Fixes a type in clock calculations, see: aaf2034cab/src/rcc.rs (L347)

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
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bors[bot] 2022-05-08 21:12:04 +00:00 committed by GitHub
commit b7a27113f0
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embassy-stm32/src/rcc/f7.rs
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@ -170,7 +170,7 @@ pub(crate) unsafe fn init(config: Config) {
// Calculate real AHB clock // Calculate real AHB clock
let hclk = sysclk / hpre_div; let hclk = sysclk / hpre_div;
assert!(hclk < max::HCLK_MAX); assert!(hclk <= max::HCLK_MAX);
let pclk1 = config let pclk1 = config
.pclk1 .pclk1