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Checkpoint with lifetime issues.

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This commit is contained in:
Bob McWhirter
2021-06-25 14:00:11 -04:00
parent 1732551db4
commit b88fc2847a
10 changed files with 328 additions and 174 deletions
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69
embassy-stm32/src/bdma/mod.rs Normal file
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@ -0,0 +1,69 @@
#![macro_use]
#[cfg_attr(bdma_v1, path = "v1.rs")]
#[cfg_attr(bdma_v2, path = "v2.rs")]
mod _version;
#[allow(unused)]
pub use _version::*;
use crate::pac;
use crate::peripherals;
pub(crate) mod sealed {
use super::*;
pub trait Channel {
fn num(&self) -> u8;
fn dma_num(&self) -> u8 {
self.num() / 8
}
fn ch_num(&self) -> u8 {
self.num() % 8
}
fn regs(&self) -> pac::dma::Dma {
pac::DMA(self.num() as _)
}
}
}
pub trait Channel: sealed::Channel + Sized {}
macro_rules! impl_dma_channel {
($channel_peri:ident, $dma_num:expr, $ch_num:expr) => {
impl Channel for peripherals::$channel_peri {}
impl sealed::Channel for peripherals::$channel_peri {
#[inline]
fn num(&self) -> u8 {
$dma_num * 8 + $ch_num
}
}
};
}
/*
crate::pac::peripherals!(
(dma,DMA1) => {
impl_dma_channel!(DMA1_CH0, 0, 0);
impl_dma_channel!(DMA1_CH1, 0, 1);
impl_dma_channel!(DMA1_CH2, 0, 2);
impl_dma_channel!(DMA1_CH3, 0, 3);
impl_dma_channel!(DMA1_CH4, 0, 4);
impl_dma_channel!(DMA1_CH5, 0, 5);
impl_dma_channel!(DMA1_CH6, 0, 6);
impl_dma_channel!(DMA1_CH7, 0, 7);
};
(dma,DMA2) => {
impl_dma_channel!(DMA2_CH0, 1, 0);
impl_dma_channel!(DMA2_CH1, 1, 1);
impl_dma_channel!(DMA2_CH2, 1, 2);
impl_dma_channel!(DMA2_CH3, 1, 3);
impl_dma_channel!(DMA2_CH4, 1, 4);
impl_dma_channel!(DMA2_CH5, 1, 5);
impl_dma_channel!(DMA2_CH6, 1, 6);
impl_dma_channel!(DMA2_CH7, 1, 7);
};
);
*/

65
embassy-stm32/src/dma/mod.rs
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@ -1,67 +1,22 @@
#![macro_use]
#[cfg_attr(dma_v1, path = "v1.rs")]
//#[cfg_attr(dma_v1, path = "v1.rs")]
#[cfg_attr(dma_v2, path = "v2.rs")]
mod _version;
#[allow(unused)]
pub use _version::*;
use crate::pac;
use crate::peripherals;
use core::future::Future;
pub(crate) mod sealed {
use super::*;
pub trait WriteDma<T> {
type WriteDmaFuture<'a>: Future<Output = ()> + 'a
where
Self: 'a;
pub trait Channel {
fn num(&self) -> u8;
fn dma_num(&self) -> u8 {
self.num() / 8
}
fn ch_num(&self) -> u8 {
self.num() % 8
}
fn regs(&self) -> pac::dma::Dma {
pac::DMA(self.num() as _)
}
}
fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
where
T: 'a;
}
pub trait Channel: sealed::Channel + Sized {}
macro_rules! impl_dma_channel {
($type:ident, $dma_num:expr, $ch_num:expr) => {
impl Channel for peripherals::$type {}
impl sealed::Channel for peripherals::$type {
#[inline]
fn num(&self) -> u8 {
$dma_num * 8 + $ch_num
}
}
};
}
crate::pac::peripherals!(
(dma,DMA1) => {
impl_dma_channel!(DMA1_CH0, 0, 0);
impl_dma_channel!(DMA1_CH1, 0, 1);
impl_dma_channel!(DMA1_CH2, 0, 2);
impl_dma_channel!(DMA1_CH3, 0, 3);
impl_dma_channel!(DMA1_CH4, 0, 4);
impl_dma_channel!(DMA1_CH5, 0, 5);
impl_dma_channel!(DMA1_CH6, 0, 6);
impl_dma_channel!(DMA1_CH7, 0, 7);
};
(dma,DMA2) => {
impl_dma_channel!(DMA2_CH0, 1, 0);
impl_dma_channel!(DMA2_CH1, 1, 1);
impl_dma_channel!(DMA2_CH2, 1, 2);
impl_dma_channel!(DMA2_CH3, 1, 3);
impl_dma_channel!(DMA2_CH4, 1, 4);
impl_dma_channel!(DMA2_CH5, 1, 5);
impl_dma_channel!(DMA2_CH6, 1, 6);
impl_dma_channel!(DMA2_CH7, 1, 7);
};
);
pub trait ReadDma {}

265
embassy-stm32/src/dma/v2.rs
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@ -9,9 +9,14 @@ use crate::interrupt;
use crate::pac;
use crate::pac::dma::{regs, vals};
const DMAS: [pac::dma::Dma; 2] = [pac::DMA1, pac::DMA2];
use crate::pac::dma_channels;
use crate::pac::interrupts;
use crate::pac::peripheral_count;
use crate::pac::peripheral_dma_channels;
use crate::pac::peripherals;
use crate::peripherals;
const CH_COUNT: usize = 16;
const CH_COUNT: usize = peripheral_count!(DMA) * 8;
const CH_STATUS_NONE: u8 = 0;
const CH_STATUS_COMPLETED: u8 = 1;
const CH_STATUS_ERROR: u8 = 2;
@ -41,9 +46,8 @@ pub(crate) async unsafe fn transfer_m2p(
src: &[u8],
dst: *mut u8,
) {
let n = ch.num() as usize;
let r = ch.regs();
let c = r.st(ch.ch_num() as _);
let n = ch.num();
let c = ch.regs();
// ndtr is max 16 bits.
assert!(src.len() <= 0xFFFF);
@ -82,106 +86,169 @@ pub(crate) async unsafe fn transfer_m2p(
}
unsafe fn on_irq() {
for (dman, &dma) in DMAS.iter().enumerate() {
for isrn in 0..2 {
let isr = dma.isr(isrn).read();
dma.ifcr(isrn).write_value(isr);
peripherals! {
(dma, $dma:ident) => {
for isrn in 0..2 {
let isr = pac::$dma.isr(isrn).read();
pac::$dma.ifcr(isrn).write_value(isr);
let dman = <peripherals::$dma as sealed::Dma>::num() as usize;
for chn in 0..4 {
let n = dman * 8 + isrn * 4 + chn;
if isr.teif(chn) {
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
STATE.ch_wakers[n].wake();
} else if isr.tcif(chn) {
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
STATE.ch_wakers[n].wake();
for chn in 0..4 {
let n = dman * 8 + isrn * 4 + chn;
if isr.teif(chn) {
STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
STATE.ch_wakers[n].wake();
} else if isr.tcif(chn) {
STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
STATE.ch_wakers[n].wake();
}
}
}
}
};
}
}
#[interrupt]
unsafe fn DMA1_STREAM0() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM1() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM2() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM3() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM4() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM5() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM6() {
on_irq()
}
#[interrupt]
unsafe fn DMA1_STREAM7() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM0() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM1() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM2() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM3() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM4() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM5() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM6() {
on_irq()
}
#[interrupt]
unsafe fn DMA2_STREAM7() {
on_irq()
}
/// safety: must be called only once
pub(crate) unsafe fn init() {
interrupt::DMA1_STREAM0::steal().enable();
interrupt::DMA1_STREAM1::steal().enable();
interrupt::DMA1_STREAM2::steal().enable();
interrupt::DMA1_STREAM3::steal().enable();
interrupt::DMA1_STREAM4::steal().enable();
interrupt::DMA1_STREAM5::steal().enable();
interrupt::DMA1_STREAM6::steal().enable();
interrupt::DMA1_STREAM7::steal().enable();
interrupt::DMA2_STREAM0::steal().enable();
interrupt::DMA2_STREAM1::steal().enable();
interrupt::DMA2_STREAM2::steal().enable();
interrupt::DMA2_STREAM3::steal().enable();
interrupt::DMA2_STREAM4::steal().enable();
interrupt::DMA2_STREAM5::steal().enable();
interrupt::DMA2_STREAM6::steal().enable();
interrupt::DMA2_STREAM7::steal().enable();
interrupts! {
(DMA, $irq:ident) => {
interrupt::$irq::steal().enable();
};
}
}
pub(crate) mod sealed {
use super::*;
pub trait Dma {
fn num() -> u8;
fn regs() -> &'static pac::dma::Dma;
}
pub trait Channel {
fn dma_regs() -> &'static pac::dma::Dma;
fn num(&self) -> usize;
fn ch_num(&self) -> u8;
fn regs(&self) -> pac::dma::St {
Self::dma_regs().st(self.ch_num() as _)
}
}
pub trait PeripheralChannel<PERI>: Channel {
fn request(&self) -> u8;
}
}
pub trait Dma: sealed::Dma + Sized {}
pub trait Channel: sealed::Channel + Sized {}
pub trait PeripheralChannel<PERI>: sealed::PeripheralChannel<PERI> + Sized {}
macro_rules! impl_dma {
($peri:ident, $num:expr) => {
impl Dma for peripherals::$peri {}
impl sealed::Dma for peripherals::$peri {
fn num() -> u8 {
$num
}
fn regs() -> &'static pac::dma::Dma {
&pac::$peri
}
}
};
}
macro_rules! impl_dma_channel {
($channel_peri:ident, $dma_peri:ident, $dma_num:expr, $ch_num:expr) => {
impl Channel for peripherals::$channel_peri {}
impl sealed::Channel for peripherals::$channel_peri {
#[inline]
fn dma_regs() -> &'static pac::dma::Dma {
&crate::pac::$dma_peri
}
fn num(&self) -> usize {
($dma_num * 8) + $ch_num
}
fn ch_num(&self) -> u8 {
$ch_num
}
}
impl<T> WriteDma<T> for peripherals::$channel_peri
where
Self: sealed::PeripheralChannel<T>,
T: 'static,
{
type WriteDmaFuture<'a> = impl Future<Output = ()>;
fn transfer<'a>(&'a mut self, buf: &'a [u8], dst: *mut u8) -> Self::WriteDmaFuture<'a>
where
T: 'a,
{
let request = sealed::PeripheralChannel::<T>::request(self);
unsafe { transfer_m2p(self, request, buf, dst) }
}
}
};
}
peripherals! {
(dma, DMA1) => {
impl_dma!(DMA1, 0);
dma_channels! {
($channel_peri:ident, DMA1, $channel_num:expr) => {
impl_dma_channel!($channel_peri, DMA1, 0, $channel_num);
};
}
};
(dma, DMA2) => {
impl_dma!(DMA2, 1);
dma_channels! {
($channel_peri:ident, DMA2, $channel_num:expr) => {
impl_dma_channel!($channel_peri, DMA2, 1, $channel_num);
};
}
};
}
interrupts! {
(DMA, $irq:ident) => {
unsafe fn $irq () {
on_irq()
}
};
}
#[cfg(usart)]
use crate::usart;
peripheral_dma_channels! {
($peri:ident, usart, $kind:ident, RX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
impl usart::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::RxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$event_num
}
}
impl PeripheralChannel<peripherals::$peri> for peripherals::$channel_peri { }
};
($peri:ident, usart, $kind:ident, TX, $channel_peri:ident, $dma_peri:ident, $channel_num:expr, $event_num:expr) => {
impl usart::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl usart::sealed::TxDma<peripherals::$peri> for peripherals::$channel_peri { }
impl sealed::PeripheralChannel<peripherals::$peri> for peripherals::$channel_peri {
fn request(&self) -> u8 {
$event_num
}
}
impl PeripheralChannel<peripherals::$peri> for peripherals::$channel_peri { }
};
}

2
embassy-stm32/src/lib.rs
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@ -22,6 +22,8 @@ pub mod rcc;
// Sometimes-present hardware
#[cfg(adc)]
pub mod adc;
#[cfg(bdma)]
pub mod bdma;
#[cfg(timer)]
pub mod clock;
#[cfg(dac)]

11
embassy-stm32/src/usart/mod.rs
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@ -1,7 +1,7 @@
#![macro_use]
#[cfg_attr(usart_v1, path = "v1.rs")]
#[cfg_attr(usart_v2, path = "v2.rs")]
//#[cfg_attr(usart_v2, path = "v2.rs")]
mod _version;
use crate::peripherals;
pub use _version::*;
@ -25,6 +25,7 @@ pub enum Error {
pub(crate) mod sealed {
use super::*;
use crate::dma::WriteDma;
pub trait Instance {
fn regs(&self) -> Usart;
@ -44,7 +45,12 @@ pub(crate) mod sealed {
pub trait CkPin<T: Instance>: Pin {
fn af_num(&self) -> u8;
}
pub trait RxDma<T: Instance> {}
pub trait TxDma<T: Instance>: WriteDma<T> {}
}
pub trait Instance: sealed::Instance {}
pub trait RxPin<T: Instance>: sealed::RxPin<T> {}
pub trait TxPin<T: Instance>: sealed::TxPin<T> {}
@ -52,6 +58,9 @@ pub trait CtsPin<T: Instance>: sealed::CtsPin<T> {}
pub trait RtsPin<T: Instance>: sealed::RtsPin<T> {}
pub trait CkPin<T: Instance>: sealed::CkPin<T> {}
pub trait RxDma<T: Instance>: sealed::RxDma<T> {}
pub trait TxDma<T: Instance>: sealed::TxDma<T> {}
crate::pac::peripherals!(
(usart, $inst:ident) => {
impl sealed::Instance for peripherals::$inst {

10
embassy-stm32/src/usart/v1.rs
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@ -104,11 +104,16 @@ impl<'d, T: Instance> Uart<'d, T> {
#[cfg(dma_v2)]
pub async fn write_dma(
&mut self,
ch: &mut impl crate::dma::Channel,
//ch: &mut impl crate::dma::Channel,
ch: &mut impl TxDma<T>,
buffer: &[u8],
) -> Result<(), Error> {
let ch_func = 4; // USART3_TX
let r = self.inner.regs();
let dst = r.dr().ptr() as *mut u8;
ch.transfer(buffer, dst).await;
Ok(())
/*
let ch_func = 4; // USART3_TX
unsafe {
r.cr3().write(|w| {
@ -121,6 +126,7 @@ impl<'d, T: Instance> Uart<'d, T> {
}
Ok(())
*/
}
pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {