stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.

This commit is contained in:
Dario Nieuwenhuis
2023-10-11 03:53:27 +02:00
parent 5a19d18b9c
commit b91d1eaca0
31 changed files with 267 additions and 403 deletions

View File

@ -1,16 +1,12 @@
use crate::pac::pwr::vals::Vos;
use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllp, Pllq, Pllsrc, Ppre, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
/// Clocks configuration
#[non_exhaustive]
#[derive(Default)]
@ -23,9 +19,7 @@ pub struct Config {
pub pclk2: Option<Hertz>,
pub pll48: bool,
pub rtc: Option<RtcClockSource>,
pub lsi: bool,
pub lse: Option<Hertz>,
pub ls: super::LsConfig,
}
fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
@ -261,17 +255,7 @@ pub(crate) unsafe fn init(config: Config) {
})
});
BackupDomain::configure_ls(
config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
config.lsi,
config.lse.map(|_| Default::default()),
);
let rtc = match config.rtc {
Some(RtcClockSource::LSI) => Some(LSI_FREQ),
Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
_ => None,
};
let rtc = config.ls.init();
set_freqs(Clocks {
sys: Hertz(sysclk),