stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
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@ -1,16 +1,12 @@
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hpre, Pllm, Plln, Pllp, Pllq, Pllsrc, Ppre, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// Clocks configuration
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#[non_exhaustive]
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#[derive(Default)]
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@ -23,9 +19,7 @@ pub struct Config {
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pub pclk2: Option<Hertz>,
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pub pll48: bool,
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pub rtc: Option<RtcClockSource>,
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pub lsi: bool,
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pub lse: Option<Hertz>,
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pub ls: super::LsConfig,
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}
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fn setup_pll(pllsrcclk: u32, use_hse: bool, pllsysclk: Option<u32>, pll48clk: bool) -> PllResults {
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@ -261,17 +255,7 @@ pub(crate) unsafe fn init(config: Config) {
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})
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});
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BackupDomain::configure_ls(
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config.rtc.unwrap_or(RtcClockSource::NOCLOCK),
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config.lsi,
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config.lse.map(|_| Default::default()),
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);
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let rtc = match config.rtc {
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Some(RtcClockSource::LSI) => Some(LSI_FREQ),
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Some(RtcClockSource::LSE) => Some(config.lse.unwrap()),
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_ => None,
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};
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let rtc = config.ls.init();
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set_freqs(Clocks {
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sys: Hertz(sysclk),
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