stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
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@ -5,16 +5,12 @@ pub use crate::pac::rcc::vals::{
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Pllsrc as PllSource, Ppre as APBPrescaler,
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};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// HSE speed
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pub const HSE_FREQ: Hertz = Hertz(32_000_000);
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@ -33,10 +29,8 @@ pub struct Config {
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pub shd_ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub rtc_mux: RtcClockSource,
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pub lse: Option<Hertz>,
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pub lsi: bool,
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pub adc_clock_source: AdcClockSource,
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pub ls: super::LsConfig,
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}
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impl Default for Config {
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@ -48,10 +42,8 @@ impl Default for Config {
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shd_ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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rtc_mux: RtcClockSource::LSI,
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lsi: true,
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lse: None,
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adc_clock_source: AdcClockSource::HSI16,
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ls: Default::default(),
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}
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}
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}
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@ -104,9 +96,6 @@ pub(crate) unsafe fn init(config: Config) {
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while FLASH.acr().read().latency() != ws {}
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// Enables the LSI if configured
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BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
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match config.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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@ -129,12 +118,8 @@ pub(crate) unsafe fn init(config: Config) {
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w.set_msirange(range);
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w.set_msion(true);
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if config.rtc_mux == RtcClockSource::LSE {
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(true);
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} else {
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w.set_msipllen(false);
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}
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(config.ls.lse.is_some());
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});
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while !RCC.cr().read().msirdy() {}
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}
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@ -156,6 +141,8 @@ pub(crate) unsafe fn init(config: Config) {
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// TODO: switch voltage range
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let rtc = config.ls.init();
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set_freqs(Clocks {
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sys: sys_clk,
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ahb1: ahb_freq,
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@ -166,6 +153,7 @@ pub(crate) unsafe fn init(config: Config) {
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apb3: shd_ahb_freq,
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apb1_tim: apb1_tim_freq,
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apb2_tim: apb2_tim_freq,
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rtc,
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});
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}
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