max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adc_v3: replace cfg(stm32g0) + friends with cfg(adc_g0)

Browse Source 
Since any MCU (not just STM32G0) using adc_g0 should probably be handled the same way.
This commit is contained in:
Olle Sandberg
2023-09-05 12:10:31 +02:00
parent a05afc5426
commit bb2d6c8542
2 changed files with 29 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
embassy-stm32/src/adc/v3.rs
View File

@ -26,9 +26,9 @@ pub struct VrefInt;
impl<T: Instance> AdcPin<T> for VrefInt {}
impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
fn channel(&self) -> u8 {
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
let val = 0;
#[cfg(stm32g0)]
#[cfg(adc_g0)]
let val = 13;
val
}
@ -38,9 +38,9 @@ pub struct Temperature;
impl<T: Instance> AdcPin<T> for Temperature {}
impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
fn channel(&self) -> u8 {
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
let val = 17;
#[cfg(stm32g0)]
#[cfg(adc_g0)]
let val = 12;
val
}
@ -50,9 +50,9 @@ pub struct Vbat;
impl<T: Instance> AdcPin<T> for Vbat {}
impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
fn channel(&self) -> u8 {
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
let val = 18;
#[cfg(stm32g0)]
#[cfg(adc_g0)]
let val = 14;
val
}
@ -92,9 +92,14 @@ impl<'d, T: Instance> Adc<'d, T> {
}
pub fn enable_vrefint(&self, delay: &mut impl DelayUs<u32>) -> VrefInt {
#[cfg(not(adc_g0))]
T::common_regs().ccr().modify(|reg| {
reg.set_vrefen(true);
});
#[cfg(adc_g0)]
T::regs().ccr().modify(|reg| {
reg.set_vrefen(true);
});
// "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
// to stabilize the internal voltage reference, we wait a little more.
@ -106,17 +111,27 @@ impl<'d, T: Instance> Adc<'d, T> {
}
pub fn enable_temperature(&self) -> Temperature {
#[cfg(not(adc_g0))]
T::common_regs().ccr().modify(|reg| {
reg.set_ch17sel(true);
});
#[cfg(adc_g0)]
T::regs().ccr().modify(|reg| {
reg.set_tsen(true);
});
Temperature {}
}
pub fn enable_vbat(&self) -> Vbat {
#[cfg(not(adc_g0))]
T::common_regs().ccr().modify(|reg| {
reg.set_ch18sel(true);
});
#[cfg(adc_g0)]
T::regs().ccr().modify(|reg| {
reg.set_vbaten(true);
});
Vbat {}
}
@ -126,9 +141,9 @@ impl<'d, T: Instance> Adc<'d, T> {
}
pub fn set_resolution(&mut self, resolution: Resolution) {
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
#[cfg(stm32g0)]
#[cfg(adc_g0)]
T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
}
@ -182,9 +197,9 @@ impl<'d, T: Instance> Adc<'d, T> {
Self::set_channel_sample_time(pin.channel(), self.sample_time);
// Select channel
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
#[cfg(stm32g0)]
#[cfg(adc_g0)]
T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel()));
// Some models are affected by an erratum:
@ -203,12 +218,12 @@ impl<'d, T: Instance> Adc<'d, T> {
val
}
#[cfg(stm32g0)]
#[cfg(adc_g0)]
fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
}
#[cfg(not(stm32g0))]
#[cfg(not(adc_g0))]
fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
let sample_time = sample_time.into();
T::regs()