stm32: update metapac

2023-10-17 20:31:44 -05:00
parent d94b9fe6fb
commit bbd12c9372
18 changed files with 44 additions and 36 deletions
--- a/embassy-stm32/src/rcc/f2.rs
+++ b/embassy-stm32/src/rcc/f2.rs
@ -256,7 +256,7 @@ pub(crate) unsafe fn init(config: Config) {
        ClockSrc::PLL => {
            RCC.cr().modify(|w| w.set_pllon(true));
            while !RCC.cr().read().pllrdy() {}
-            (pll_clocks.main_freq, Sw::PLL)
+            (pll_clocks.main_freq, Sw::PLL1_P)
        }
    };
    // RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL