Add is_eraseable_range and split write into consecutive parts
This commit is contained in:
@ -1,15 +1,13 @@
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use core::convert::TryInto;
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use core::mem::size_of;
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use core::ptr::write_volatile;
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use super::{FlashRegion, FLASH_SIZE};
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use atomic_polyfill::{fence, Ordering};
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use super::{FlashRegion, FLASH_SIZE, WRITE_SIZE};
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use crate::flash::Error;
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use crate::pac;
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const WRITE_SIZE: usize = super::BANK1::WRITE_SIZE;
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const ERASE_SIZE: usize = super::BANK1::ERASE_SIZE;
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pub(crate) const MAX_WRITE_SIZE: usize = WRITE_SIZE;
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pub(crate) const MAX_ERASE_SIZE: usize = ERASE_SIZE;
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const SECOND_BANK_OFFSET: usize = 0x0010_0000;
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const fn is_dual_bank() -> bool {
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@ -33,59 +31,60 @@ pub(crate) unsafe fn unlock() {
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}
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}
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pub(crate) unsafe fn blocking_write(first_address: u32, buf: &[u8]) -> Result<(), Error> {
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let bank = if !is_dual_bank() || (first_address - super::FLASH_BASE as u32) < SECOND_BANK_OFFSET as u32 {
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pub(crate) unsafe fn begin_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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}
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pub(crate) unsafe fn end_write() {}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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// We cannot have the write setup sequence in begin_write as it depends on the address
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let bank = if !is_dual_bank() || (start_address - super::FLASH_BASE as u32) < SECOND_BANK_OFFSET as u32 {
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pac::FLASH.bank(0)
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} else {
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pac::FLASH.bank(1)
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};
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bank.cr().write(|w| {
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w.set_pg(true);
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w.set_psize(2); // 32 bits at once
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});
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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fence(Ordering::SeqCst);
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let ret = {
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let mut ret: Result<(), Error> = Ok(());
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let mut address = first_address;
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'outer: for chunk in buf.chunks(WRITE_SIZE) {
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let vals = chunk.chunks_exact(size_of::<u32>());
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assert!(vals.remainder().is_empty());
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for val in vals {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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let mut res = None;
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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ret = blocking_wait_ready(bank);
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bank.sr().modify(|w| {
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if w.eop() {
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w.set_eop(true);
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}
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});
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if ret.is_err() {
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break 'outer;
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}
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res = Some(blocking_wait_ready(bank));
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bank.sr().modify(|w| {
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if w.eop() {
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w.set_eop(true);
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}
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});
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if res.unwrap().is_err() {
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break;
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}
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ret
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};
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}
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bank.cr().write(|w| w.set_pg(false));
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
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fence(Ordering::SeqCst);
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ret
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res.unwrap()
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}
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pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
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let start_sector = (from - super::FLASH_BASE as u32) / ERASE_SIZE as u32;
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let end_sector = (to - super::FLASH_BASE as u32) / ERASE_SIZE as u32;
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pub(crate) fn is_eraseable_range(start_address: u32, end_address: u32) -> bool {
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start_address % ERASE_SIZE as u32 == 0 && end_address % ERASE_SIZE as u32 == 0
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}
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pub(crate) unsafe fn blocking_erase(start_address: u32, end_address: u32) -> Result<(), Error> {
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let start_sector = (start_address - super::FLASH_BASE as u32) / ERASE_SIZE as u32;
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let end_sector = (end_address - super::FLASH_BASE as u32) / ERASE_SIZE as u32;
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for sector in start_sector..end_sector {
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let bank = if sector >= 8 { 1 } else { 0 };
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let ret = erase_sector(pac::FLASH.bank(bank), (sector % 8) as u8);
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@ -93,7 +92,6 @@ pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
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return ret;
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}
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}
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Ok(())
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}
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@ -157,7 +155,7 @@ unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
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});
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}
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pub(crate) unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
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unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
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loop {
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let sr = bank.sr().read();
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