Use RCC frequency instead of config
This commit is contained in:
		@@ -133,6 +133,7 @@ cfg_if::cfg_if! {
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                _ => Err(Error::BadClock),
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					                _ => Err(Error::BadClock),
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            }?;
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					            }?;
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					            // SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]
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            let clk_f = Hertz(ker_ck.0 / (clk_div as u32 + 2));
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					            let clk_f = Hertz(ker_ck.0 / (clk_div as u32 + 2));
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            Ok((clk_div, clk_f))
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					            Ok((clk_div, clk_f))
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        }
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					        }
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@@ -159,18 +160,10 @@ cfg_if::cfg_if! {
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/// SDMMC configuration
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					/// SDMMC configuration
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///
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					///
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/// You should probably change the default clock values to match your configuration
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///
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/// Default values:
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					/// Default values:
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/// hclk = 400_000_000 Hz
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/// kernel_clk: 100_000_000 Hz
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/// data_transfer_timeout: 5_000_000
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					/// data_transfer_timeout: 5_000_000
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#[non_exhaustive]
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					#[non_exhaustive]
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pub struct Config {
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					pub struct Config {
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    /// AHB clock
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    pub hclk: Hertz,
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    /// SDMMC kernel clock
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    pub kernel_clk: Hertz,
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    /// The timeout to be set for data transfers, in card bus clock periods
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					    /// The timeout to be set for data transfers, in card bus clock periods
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    pub data_transfer_timeout: u32,
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					    pub data_transfer_timeout: u32,
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}
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					}
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@@ -178,8 +171,6 @@ pub struct Config {
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impl Default for Config {
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					impl Default for Config {
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    fn default() -> Self {
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					    fn default() -> Self {
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        Self {
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					        Self {
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            hclk: Hertz(400_000_000),
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            kernel_clk: Hertz(100_000_000),
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            data_transfer_timeout: 5_000_000,
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					            data_transfer_timeout: 5_000_000,
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        }
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					        }
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    }
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					    }
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@@ -219,7 +210,7 @@ impl<'d, T: Instance, P: Pins<T>, Dma: SdioDma<T>> Sdmmc<'d, T, P, Dma> {
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        T::reset();
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					        T::reset();
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        let inner = T::inner();
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					        let inner = T::inner();
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        let clock = inner.new_inner(config.kernel_clk);
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					        let clock = inner.new_inner(T::frequency());
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        irq.set_handler(Self::on_interrupt);
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					        irq.set_handler(Self::on_interrupt);
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        irq.unpend();
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					        irq.unpend();
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@@ -248,8 +239,7 @@ impl<'d, T: Instance, P: Pins<T>, Dma: SdioDma<T>> Sdmmc<'d, T, P, Dma> {
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                P::BUSWIDTH,
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					                P::BUSWIDTH,
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                &mut self.card,
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					                &mut self.card,
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                &mut self.signalling,
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					                &mut self.signalling,
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                self.config.hclk,
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					                T::frequency(),
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                self.config.kernel_clk,
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                &mut self.clock,
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					                &mut self.clock,
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                T::state(),
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					                T::state(),
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                self.config.data_transfer_timeout,
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					                self.config.data_transfer_timeout,
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@@ -371,7 +361,6 @@ impl SdmmcInner {
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        bus_width: BusWidth,
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					        bus_width: BusWidth,
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        old_card: &mut Option<Card>,
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					        old_card: &mut Option<Card>,
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        signalling: &mut Signalling,
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					        signalling: &mut Signalling,
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        hclk: Hertz,
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        ker_ck: Hertz,
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					        ker_ck: Hertz,
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        clock: &mut Hertz,
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					        clock: &mut Hertz,
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        waker_reg: &AtomicWaker,
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					        waker_reg: &AtomicWaker,
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@@ -474,10 +463,10 @@ impl SdmmcInner {
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            // Set Clock
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					            // Set Clock
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            if freq.0 <= 25_000_000 {
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					            if freq.0 <= 25_000_000 {
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                // Final clock frequency
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					                // Final clock frequency
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                self.clkcr_set_clkdiv(freq.0, width, hclk, ker_ck, clock)?;
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					                self.clkcr_set_clkdiv(freq.0, width, ker_ck, clock)?;
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            } else {
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					            } else {
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                // Switch to max clock for SDR12
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					                // Switch to max clock for SDR12
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                self.clkcr_set_clkdiv(25_000_000, width, hclk, ker_ck, clock)?;
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					                self.clkcr_set_clkdiv(25_000_000, width, ker_ck, clock)?;
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            }
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					            }
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            // Read status
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					            // Read status
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@@ -497,7 +486,7 @@ impl SdmmcInner {
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                if *signalling == Signalling::SDR25 {
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					                if *signalling == Signalling::SDR25 {
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                    // Set final clock frequency
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					                    // Set final clock frequency
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                    self.clkcr_set_clkdiv(freq.0, width, hclk, ker_ck, clock)?;
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					                    self.clkcr_set_clkdiv(freq.0, width, ker_ck, clock)?;
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                    if self.read_status(&card)?.state() != CurrentState::Transfer {
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					                    if self.read_status(&card)?.state() != CurrentState::Transfer {
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                        return Err(Error::SignalingSwitchFailed);
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					                        return Err(Error::SignalingSwitchFailed);
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@@ -804,7 +793,6 @@ impl SdmmcInner {
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        &self,
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					        &self,
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        freq: u32,
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					        freq: u32,
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        width: BusWidth,
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					        width: BusWidth,
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        hclk: Hertz,
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        ker_ck: Hertz,
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					        ker_ck: Hertz,
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        clock: &mut Hertz,
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					        clock: &mut Hertz,
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    ) -> Result<(), Error> {
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					    ) -> Result<(), Error> {
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@@ -814,7 +802,7 @@ impl SdmmcInner {
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        // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7
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					        // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7
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        // Section 55.5.8
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					        // Section 55.5.8
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        let sdmmc_bus_bandwidth = new_clock.0 * (width as u32);
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					        let sdmmc_bus_bandwidth = new_clock.0 * (width as u32);
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        assert!(hclk.0 > 3 * sdmmc_bus_bandwidth / 32);
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					        assert!(ker_ck.0 > 3 * sdmmc_bus_bandwidth / 32);
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        *clock = new_clock;
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					        *clock = new_clock;
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        // NOTE(unsafe) We have exclusive access to the regblock
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					        // NOTE(unsafe) We have exclusive access to the regblock
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@@ -6,7 +6,7 @@
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mod example_common;
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					mod example_common;
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use embassy::executor::Spawner;
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					use embassy::executor::Spawner;
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use embassy_stm32::sdmmc::{self, Sdmmc};
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					use embassy_stm32::sdmmc::Sdmmc;
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use embassy_stm32::time::U32Ext;
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					use embassy_stm32::time::U32Ext;
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use embassy_stm32::{interrupt, Config, Peripherals};
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					use embassy_stm32::{interrupt, Config, Peripherals};
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use example_common::*;
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					use example_common::*;
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@@ -26,16 +26,12 @@ async fn main(_spawner: Spawner, p: Peripherals) -> ! {
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    let irq = interrupt::take!(SDIO);
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					    let irq = interrupt::take!(SDIO);
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    let mut config = sdmmc::Config::default();
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    config.hclk = 48.mhz().into();
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    config.kernel_clk = 48.mhz().into();
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    let mut sdmmc = unsafe {
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					    let mut sdmmc = unsafe {
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        Sdmmc::new(
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					        Sdmmc::new(
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            p.SDIO,
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					            p.SDIO,
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            (p.PC12, p.PD2, p.PC8, p.PC9, p.PC10, p.PC11),
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					            (p.PC12, p.PD2, p.PC8, p.PC9, p.PC10, p.PC11),
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            irq,
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					            irq,
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            config,
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					            Default::default(),
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            p.DMA2_CH3,
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					            p.DMA2_CH3,
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        )
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					        )
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    };
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					    };
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