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Merge branch 'implement-uart' of ssh://github.com/xoviat/embassy into implement-uart

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xoviat 2021-01-12 14:00:39 -06:00
commit c07f7467a0
2 changed files with 53 additions and 57 deletions
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14
embassy-stm32f4-examples/src/serial.rs
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@ -28,8 +28,8 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
.pclk1(24.mhz()) .pclk1(24.mhz())
.freeze(); .freeze();
unsafe { let mut serial = unsafe {
let mut serial = serial::Serial::new( serial::Serial::new(
gpioa.pa9.into_alternate_af7(), gpioa.pa9.into_alternate_af7(),
gpioa.pa10.into_alternate_af7(), gpioa.pa10.into_alternate_af7(),
interrupt::take!(DMA2_STREAM7), interrupt::take!(DMA2_STREAM7),
@ -40,12 +40,12 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
config::Parity::ParityNone, config::Parity::ParityNone,
9600.bps(), 9600.bps(),
clocks, clocks,
); )
let buf = singleton!(: [u8; 30] = [0; 30]).unwrap(); };
let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
buf[5] = 0x01; buf[5] = 0x01;
serial.send(buf).await; serial.send(buf).await;
}
} }
static EXECUTOR: Forever<Executor> = Forever::new(); static EXECUTOR: Forever<Executor> = Forever::new();

96
embassy-stm32f4/src/serial.rs
View File

@ -152,37 +152,35 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> { fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> {
unsafe { INSTANCE = self }; unsafe { INSTANCE = self };
unsafe { let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
let static_buf = core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf);
let tx_stream = self.tx_stream.take().unwrap(); let tx_stream = self.tx_stream.take().unwrap();
let usart = self.usart.take().unwrap(); let usart = self.usart.take().unwrap();
STATE.tx_int.reset(); STATE.tx_int.reset();
async move { async move {
let mut tx_transfer = Transfer::init( let mut tx_transfer = Transfer::init(
tx_stream, tx_stream,
usart, usart,
static_buf, static_buf,
None, None,
DmaConfig::default() DmaConfig::default()
.transfer_complete_interrupt(true) .transfer_complete_interrupt(true)
.memory_increment(true) .memory_increment(true)
.double_buffer(false), .double_buffer(false),
); );
self.tx_int.unpend(); self.tx_int.unpend();
self.tx_int.enable(); self.tx_int.enable();
tx_transfer.start(|_usart| {}); tx_transfer.start(|_usart| {});
STATE.tx_int.wait().await; STATE.tx_int.wait().await;
let (tx_stream, usart, _buf, _) = tx_transfer.free(); let (tx_stream, usart, _buf, _) = tx_transfer.free();
self.tx_stream.replace(tx_stream); self.tx_stream.replace(tx_stream);
self.usart.replace(usart); self.usart.replace(usart);
Ok(()) Ok(())
}
} }
} }
@ -199,31 +197,29 @@ impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> { fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
unsafe { INSTANCE = self }; unsafe { INSTANCE = self };
unsafe { let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
let static_buf = core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf); let rx_stream = self.rx_stream.take().unwrap();
let rx_stream = self.rx_stream.take().unwrap(); let usart = self.usart.take().unwrap();
let usart = self.usart.take().unwrap(); STATE.rx_int.reset();
STATE.rx_int.reset(); async move {
async move { let mut rx_transfer = Transfer::init(
let mut rx_transfer = Transfer::init( rx_stream,
rx_stream, usart,
usart, static_buf,
static_buf, None,
None, DmaConfig::default()
DmaConfig::default() .transfer_complete_interrupt(true)
.transfer_complete_interrupt(true) .memory_increment(true)
.memory_increment(true) .double_buffer(false),
.double_buffer(false), );
); self.rx_int.unpend();
self.rx_int.unpend(); self.rx_int.enable();
self.rx_int.enable(); rx_transfer.start(|_usart| {});
rx_transfer.start(|_usart| {}); STATE.rx_int.wait().await;
STATE.rx_int.wait().await; let (rx_stream, usart, _, _) = rx_transfer.free();
let (rx_stream, usart, buf, _) = rx_transfer.free(); self.rx_stream.replace(rx_stream);
self.rx_stream.replace(rx_stream); self.usart.replace(usart);
self.usart.replace(usart); Ok(())
Ok(())
}
} }
} }
} }