stm32: implement qei
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@ -1,4 +1,5 @@
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pub mod complementary_pwm;
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pub mod complementary_pwm;
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pub mod qei;
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pub mod simple_pwm;
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pub mod simple_pwm;
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use stm32_metapac::timer::vals;
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use stm32_metapac::timer::vals;
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@ -1,142 +1,96 @@
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//! # Quadrature Encoder Interface
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use core::marker::PhantomData;
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use crate::{
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gpio::PushPull,
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pac, rcc,
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timer::{CPin, General},
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};
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pub trait QeiExt: Sized + Instance {
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use embassy_hal_internal::{into_ref, PeripheralRef};
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fn qei(
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self,
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use super::*;
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pins: (
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use crate::gpio::sealed::AFType;
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impl Into<<Self as CPin<0>>::Ch<PushPull>>,
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use crate::gpio::AnyPin;
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impl Into<<Self as CPin<1>>::Ch<PushPull>>,
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use crate::Peripheral;
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),
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) -> Qei<Self>;
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pub enum Direction {
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Upcounting,
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Downcounting,
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}
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}
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impl<TIM: Instance> QeiExt for TIM {
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pub struct Ch1;
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fn qei(
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pub struct Ch2;
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self,
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pins: (
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pub struct QeiPin<'d, Perip, Channel> {
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impl Into<<Self as CPin<0>>::Ch<PushPull>>,
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_pin: PeripheralRef<'d, AnyPin>,
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impl Into<<Self as CPin<1>>::Ch<PushPull>>,
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phantom: PhantomData<(Perip, Channel)>,
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),
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) -> Qei<Self> {
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Qei::new(self, pins)
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}
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}
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}
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/// Hardware quadrature encoder interface peripheral
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macro_rules! channel_impl {
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pub struct Qei<TIM: Instance> {
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($new_chx:ident, $channel:ident, $pin_trait:ident) => {
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tim: TIM,
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impl<'d, Perip: CaptureCompare16bitInstance> QeiPin<'d, Perip, $channel> {
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pins: (
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pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<Perip>> + 'd) -> Self {
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<TIM as CPin<0>>::Ch<PushPull>,
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into_ref!(pin);
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<TIM as CPin<1>>::Ch<PushPull>,
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critical_section::with(|_| {
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),
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pin.set_low();
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}
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pin.set_as_af(pin.af_num(), AFType::Input);
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#[cfg(gpio_v2)]
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impl<TIM: Instance> Qei<TIM> {
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pin.set_speed(crate::gpio::Speed::VeryHigh);
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/// Configures a TIM peripheral as a quadrature encoder interface input
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pub fn new(
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mut tim: TIM,
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pins: (
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impl Into<<TIM as CPin<0>>::Ch<PushPull>>,
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impl Into<<TIM as CPin<1>>::Ch<PushPull>>,
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),
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) -> Self {
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// Enable and reset clock.
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unsafe {
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TIM::enable_unchecked();
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TIM::reset_unchecked();
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}
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let pins = (pins.0.into(), pins.1.into());
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tim.setup_qei();
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Qei { tim, pins }
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}
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/// Releases the TIM peripheral and QEI pins
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#[allow(clippy::type_complexity)]
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pub fn release(
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self,
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) -> (
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TIM,
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(
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<TIM as CPin<0>>::Ch<PushPull>,
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<TIM as CPin<1>>::Ch<PushPull>,
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),
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) {
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(self.tim, self.pins)
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}
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/// Set current count number
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pub fn set_count(&mut self, value: TIM::Width) -> &mut Self {
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self.tim.write_count(value);
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self
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}
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}
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impl<TIM: Instance> embedded_hal::Qei for Qei<TIM> {
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type Count = TIM::Width;
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fn count(&self) -> Self::Count {
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self.tim.read_count()
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}
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fn direction(&self) -> embedded_hal::Direction {
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if self.tim.read_direction() {
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embedded_hal::Direction::Upcounting
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} else {
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embedded_hal::Direction::Downcounting
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}
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}
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}
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pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + General + CPin<0> + CPin<1> {
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fn setup_qei(&mut self);
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fn read_direction(&self) -> bool;
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}
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macro_rules! hal {
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($TIM:ty) => {
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impl Instance for $TIM {
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fn setup_qei(&mut self) {
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// Configure TxC1 and TxC2 as captures
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#[cfg(not(feature = "gpio-f410"))]
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self.ccmr1_input().write(|w| w.cc1s().ti1().cc2s().ti2());
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#[cfg(feature = "gpio-f410")]
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self.ccmr1_input()
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.write(|w| unsafe { w.cc1s().bits(0b01).cc2s().bits(0b01) });
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// enable and configure to capture on rising edge
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self.ccer.write(|w| {
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w.cc1e().set_bit().cc1p().clear_bit();
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w.cc2e().set_bit().cc2p().clear_bit()
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});
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});
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self.smcr.write(|w| w.sms().encoder_mode_3());
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QeiPin {
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self.set_auto_reload(<$TIM as General>::Width::MAX as u32)
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_pin: pin.map_into(),
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.unwrap();
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phantom: PhantomData,
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self.cr1.write(|w| w.cen().set_bit());
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}
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}
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fn read_direction(&self) -> bool {
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self.cr1.read().dir().bit_is_clear()
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}
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}
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}
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}
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};
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};
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}
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}
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#[cfg(feature = "tim1")]
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channel_impl!(new_ch1, Ch1, Channel1Pin);
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hal! { pac::TIM1 }
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channel_impl!(new_ch2, Ch2, Channel2Pin);
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#[cfg(feature = "tim2")]
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hal! { pac::TIM2 }
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pub struct SimplePwm<'d, T> {
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#[cfg(feature = "tim3")]
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_inner: PeripheralRef<'d, T>,
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hal! { pac::TIM3 }
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}
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#[cfg(feature = "tim4")]
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hal! { pac::TIM4 }
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impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
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#[cfg(feature = "tim5")]
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pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
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hal! { pac::TIM5 }
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Self::new_inner(tim)
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#[cfg(feature = "tim8")]
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}
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hal! { pac::TIM8 }
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fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
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into_ref!(tim);
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T::enable();
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<T as crate::rcc::sealed::RccPeripheral>::reset();
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// Configure TxC1 and TxC2 as captures
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T::regs_gp16().ccmr_input(0).modify(|w| {
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w.set_ccs(0, vals::CcmrInputCcs::TI4);
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w.set_ccs(1, vals::CcmrInputCcs::TI4);
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});
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// enable and configure to capture on rising edge
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T::regs_gp16().ccer().modify(|w| {
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w.set_cce(0, true);
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w.set_cce(1, true);
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w.set_ccp(0, false);
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w.set_ccp(1, false);
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});
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T::regs_gp16().smcr().modify(|w| {
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w.set_sms(vals::Sms::ENCODER_MODE_3);
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});
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T::regs_gp16().arr().modify(|w| w.set_arr(u16::MAX));
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T::regs_gp16().cr1().modify(|w| w.set_cen(true));
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Self { _inner: tim }
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}
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pub fn read_direction(&self) -> Direction {
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match T::regs_gp16().cr1().read().dir() {
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vals::Dir::DOWN => Direction::Downcounting,
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vals::Dir::UP => Direction::Upcounting,
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}
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}
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pub fn count(&self) -> u16 {
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T::regs_gp16().cnt().read().cnt()
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}
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}
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