max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stm32: extract lse/lsi into bd mod

Browse Source
This commit is contained in:
xoviat
2023-09-06 17:48:12 -05:00
parent d097c99719
commit c21ad04c2e
4 changed files with 9 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
embassy-stm32/src/rcc/wl.rs
View File

@ -1,5 +1,5 @@
pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
use crate::pac::{FLASH, PWR, RCC};
use crate::pac::{FLASH, RCC};
use crate::rcc::bd::{BackupDomain, RtcClockSource};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
@ -208,36 +208,7 @@ pub(crate) unsafe fn init(config: Config) {
while FLASH.acr().read().latency() != ws {}
match config.rtc_mux {
RtcClockSource::LSE => {
// 1. Unlock the backup domain
PWR.cr1().modify(|w| w.set_dbp(true));
// 2. Setup the LSE
RCC.bdcr().modify(|w| {
// Enable LSE
w.set_lseon(true);
// Max drive strength
// TODO: should probably be settable
w.set_lsedrv(Lsedrv::High as u8); //---// PAM - should not be commented
});
// Wait until LSE is running
while !RCC.bdcr().read().lserdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
}
RtcClockSource::LSI => {
// Turn on the internal 32 kHz LSI oscillator
RCC.csr().modify(|w| w.set_lsion(true));
// Wait until LSI is running
while !RCC.csr().read().lsirdy() {}
BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
}
_ => unreachable!(),
}
BackupDomain::configure_rtc(config.rtc_mux, None);
match config.mux {
ClockSrc::HSI16 => {