stm32: extract lse/lsi into bd mod
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d097c99719
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c21ad04c2e
@ -95,7 +95,7 @@ impl BackupDomain {
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}
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}
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#[allow(dead_code, unused_variables)]
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#[allow(dead_code, unused_variables)]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
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pub fn enable_lse(lse_drive: LseDrive) {
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pub fn enable_lse(lse_drive: LseDrive) {
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Self::modify(|w| {
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Self::modify(|w| {
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#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
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#[cfg(any(rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l4))]
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@ -107,7 +107,7 @@ impl BackupDomain {
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}
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}
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#[allow(dead_code)]
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#[allow(dead_code)]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
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pub fn enable_lsi() {
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pub fn enable_lsi() {
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let csr = crate::pac::RCC.csr();
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let csr = crate::pac::RCC.csr();
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@ -146,7 +146,7 @@ impl BackupDomain {
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});
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});
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}
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}
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb))]
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3))]
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#[allow(dead_code, unused_variables)]
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#[allow(dead_code, unused_variables)]
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pub fn configure_rtc(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) {
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pub fn configure_rtc(clock_source: RtcClockSource, lse_drive: Option<LseDrive>) {
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match clock_source {
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match clock_source {
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@ -2,13 +2,13 @@ use core::marker::PhantomData;
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use embassy_hal_internal::into_ref;
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use embassy_hal_internal::into_ref;
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use stm32_metapac::rcc::regs::Cfgr;
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use stm32_metapac::rcc::regs::Cfgr;
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use stm32_metapac::rcc::vals::{Lsedrv, Mcopre, Mcosel};
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use stm32_metapac::rcc::vals::{Mcopre, Mcosel};
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use crate::gpio::sealed::AFType;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Speed;
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use crate::gpio::Speed;
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use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
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use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::{set_freqs, Clocks};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::Hertz;
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@ -407,36 +407,7 @@ pub(crate) unsafe fn init(config: Config) {
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RCC.apb1enr1().modify(|w| w.set_pwren(true));
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RCC.apb1enr1().modify(|w| w.set_pwren(true));
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match config.rtc_mux {
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BackupDomain::configure_rtc(config.rtc_mux, None);
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RtcClockSource::LSE => {
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// 1. Unlock the backup domain
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PWR.cr1().modify(|w| w.set_dbp(true));
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// 2. Setup the LSE
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RCC.bdcr().modify(|w| {
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// Enable LSE
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w.set_lseon(true);
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// Max drive strength
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// TODO: should probably be settable
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w.set_lsedrv(Lsedrv::HIGH);
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});
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// Wait until LSE is running
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while !RCC.bdcr().read().lserdy() {}
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BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
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}
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RtcClockSource::LSI => {
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// Turn on the internal 32 kHz LSI oscillator
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RCC.csr().modify(|w| w.set_lsion(true));
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// Wait until LSI is running
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while !RCC.csr().read().lsirdy() {}
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BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
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}
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_ => unreachable!(),
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}
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let (sys_clk, sw) = match config.mux {
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let (sys_clk, sw) = match config.mux {
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ClockSrc::MSI(range) => {
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ClockSrc::MSI(range) => {
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@ -293,18 +293,6 @@ pub(crate) fn configure_clocks(config: &Config) {
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while !rcc.cr().read().hsirdy() {}
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while !rcc.cr().read().hsirdy() {}
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}
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}
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let needs_lsi = if let Some(rtc_mux) = &config.rtc {
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*rtc_mux == RtcClockSource::LSI
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} else {
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false
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};
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if needs_lsi {
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rcc.csr().modify(|w| w.set_lsi1on(true));
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while !rcc.csr().read().lsi1rdy() {}
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}
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match &config.lse {
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match &config.lse {
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Some(_) => {
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Some(_) => {
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rcc.cfgr().modify(|w| w.set_stopwuck(true));
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rcc.cfgr().modify(|w| w.set_stopwuck(true));
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@ -378,5 +366,5 @@ pub(crate) fn configure_clocks(config: &Config) {
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config
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config
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.rtc
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.rtc
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.map(|clock_source| BackupDomain::set_rtc_clock_source(clock_source));
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.map(|clock_source| BackupDomain::configure_rtc(clock_source, None));
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}
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}
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@ -1,5 +1,5 @@
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pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
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pub use super::bus::{AHBPrescaler, APBPrescaler, VoltageScale};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::bd::{BackupDomain, RtcClockSource};
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use crate::rcc::{set_freqs, Clocks};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::Hertz;
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@ -208,36 +208,7 @@ pub(crate) unsafe fn init(config: Config) {
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while FLASH.acr().read().latency() != ws {}
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while FLASH.acr().read().latency() != ws {}
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match config.rtc_mux {
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BackupDomain::configure_rtc(config.rtc_mux, None);
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RtcClockSource::LSE => {
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// 1. Unlock the backup domain
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PWR.cr1().modify(|w| w.set_dbp(true));
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// 2. Setup the LSE
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RCC.bdcr().modify(|w| {
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// Enable LSE
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w.set_lseon(true);
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// Max drive strength
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// TODO: should probably be settable
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w.set_lsedrv(Lsedrv::High as u8); //---// PAM - should not be commented
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});
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// Wait until LSE is running
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while !RCC.bdcr().read().lserdy() {}
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BackupDomain::set_rtc_clock_source(RtcClockSource::LSE);
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}
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RtcClockSource::LSI => {
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// Turn on the internal 32 kHz LSI oscillator
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RCC.csr().modify(|w| w.set_lsion(true));
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// Wait until LSI is running
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while !RCC.csr().read().lsirdy() {}
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BackupDomain::set_rtc_clock_source(RtcClockSource::LSI);
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}
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_ => unreachable!(),
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}
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match config.mux {
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match config.mux {
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ClockSrc::HSI16 => {
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ClockSrc::HSI16 => {
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