From c27b0296fe5abcdff87df31adcbe9774c54d239b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Thu, 7 Sep 2023 22:32:20 +0200 Subject: [PATCH] Add more documentation and comment --- embassy-net-adin1110/src/lib.rs | 7 +++++++ embassy-net-adin1110/src/phy.rs | 1 + 2 files changed, 8 insertions(+) diff --git a/embassy-net-adin1110/src/lib.rs b/embassy-net-adin1110/src/lib.rs index 78bf9fb8..53f36128 100644 --- a/embassy-net-adin1110/src/lib.rs +++ b/embassy-net-adin1110/src/lib.rs @@ -32,6 +32,7 @@ pub use regs::{Config0, Config2, SpiRegisters as sr, Status0, Status1}; use crate::fmt::Bytes; use crate::regs::{LedCntrl, LedFunc, LedPol, LedPolarity, SpiHeader}; +/// ADIN1110 intern PHY ID pub const PHYID: u32 = 0x0283_BC91; /// Error values ADIN1110 @@ -53,7 +54,9 @@ pub enum AdinError { MDIO_ACC_TIMEOUT, } +/// Type alias `Result` type with `AdinError` as error type. pub type AEResult = core::result::Result>; + /// Internet PHY address pub const MDIO_PHY_ADDR: u8 = 0x01; @@ -104,6 +107,7 @@ impl State { } } +/// ADIN1110 embassy-net driver #[derive(Debug)] pub struct ADIN1110 { /// SPI bus @@ -116,6 +120,7 @@ pub struct ADIN1110 { } impl ADIN1110 { + /// Create a new ADIN1110 instance. pub fn new(spi: SPI, spi_crc: bool, append_fcs_on_tx: bool) -> Self { Self { spi, @@ -124,6 +129,7 @@ impl ADIN1110 { } } + /// Read a SPI register pub async fn read_reg(&mut self, reg: sr) -> AEResult { let mut tx_buf = Vec::::new(); @@ -162,6 +168,7 @@ impl ADIN1110 { Ok(value) } + /// Write a SPI register pub async fn write_reg(&mut self, reg: sr, value: u32) -> AEResult<(), SPI::Error> { let mut tx_buf = Vec::::new(); diff --git a/embassy-net-adin1110/src/phy.rs b/embassy-net-adin1110/src/phy.rs index 176ad019..d54d843d 100644 --- a/embassy-net-adin1110/src/phy.rs +++ b/embassy-net-adin1110/src/phy.rs @@ -111,6 +111,7 @@ pub mod RegsC45 { } } +/// 10-BASE-T1x PHY functions. pub struct Phy10BaseT1x(u8); impl Default for Phy10BaseT1x {