From c27d63e754c131052f051d3ff40f6b7d7b4655b6 Mon Sep 17 00:00:00 2001
From: Tyler Gilbert <tyler.w.gilbert@gmail.com>
Date: Mon, 4 Dec 2023 22:07:03 -0600
Subject: [PATCH] Update ringbuffer to only work on half, add prime

---
 embassy-stm32/src/dma/ringbuffer.rs | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs
index c9f7a302..c4a76580 100644
--- a/embassy-stm32/src/dma/ringbuffer.rs
+++ b/embassy-stm32/src/dma/ringbuffer.rs
@@ -260,7 +260,21 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
 
     /// The current position of the ringbuffer
     fn pos(&self, dma: &mut impl DmaCtrl) -> usize {
-        self.cap() - dma.get_remaining_transfers()
+        let result = self.cap() - dma.get_remaining_transfers();
+        if result >= self.cap() / 2 {
+            self.cap() / 2
+        } else {
+            0
+        }
+    }
+
+    pub fn prime(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
+        if self.end != 0 {
+            return Err(OverrunError);
+        }
+        let written = self.copy_from(buffer, 0..self.cap());
+        self.end = written % self.cap();
+        Ok((written, self.cap() - written))
     }
 
     /// Write an exact number of elements to the ringbuffer.