From c38c85ef1fef86a5fc73d1329616df17afb3d385 Mon Sep 17 00:00:00 2001 From: xoviat Date: Sun, 30 Jul 2023 19:39:17 -0500 Subject: [PATCH] stm32/dma: add traces --- embassy-stm32/src/dma/ringbuffer.rs | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs index 1235e532..8056a7c3 100644 --- a/embassy-stm32/src/dma/ringbuffer.rs +++ b/embassy-stm32/src/dma/ringbuffer.rs @@ -229,6 +229,13 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> { let start = self.pos(dma.get_remaining_transfers()); if start > self.end { + trace!( + "[1]: start, end, complete_count: {}, {}, {}", + start, + self.end, + dma.get_complete_count() + ); + // The occupied portion in the ring buffer DOES wrap let len = self.copy_from(buf, self.end..start); @@ -244,8 +251,22 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { Ok((len, self.cap() - (start - self.end))) } } else if start == self.end && dma.get_complete_count() == 0 { + trace!( + "[2]: start, end, complete_count: {}, {}, {}", + start, + self.end, + dma.get_complete_count() + ); + Ok((0, 0)) } else if start <= self.end && self.end + buf.len() < self.cap() { + trace!( + "[3]: start, end, complete_count: {}, {}, {}", + start, + self.end, + dma.get_complete_count() + ); + // The occupied portion in the ring buffer DOES NOT wrap // and copying elements into the buffer WILL NOT cause it to @@ -264,6 +285,13 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> { Ok((len, self.cap() - (self.end - start))) } } else { + trace!( + "[4]: start, end, complete_count: {}, {}, {}", + start, + self.end, + dma.get_complete_count() + ); + // The occupied portion in the ring buffer DOES NOT wrap // and copying elements into the buffer WILL cause it to