Change ClassSet indexing and tune up example
Example doesn't work with F401 because it doesn't have enough usb endpoints
This commit is contained in:
Thales Fragoso
parent
890e93b4f0
commit
c4e79f66ea
@ -10,12 +10,11 @@ use cortex_m_rt::entry;
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use defmt::panic;
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use embassy::executor::{task, Executor};
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use embassy::io::{AsyncBufReadExt, AsyncWriteExt};
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use embassy::time::{Duration, Timer};
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use embassy::util::Forever;
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use embassy_stm32f4::interrupt::OwnedInterrupt;
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use embassy_stm32f4::usb::Usb;
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use embassy_stm32f4::usb_serial::UsbSerial;
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use embassy_stm32f4::{interrupt, pac, rtc};
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use embassy_stm32f4::{interrupt, pac};
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use futures::future::{select, Either};
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use futures::pin_mut;
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use stm32f4xx_hal::otg_fs::{UsbBus, USB};
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@ -27,44 +26,81 @@ use usb_device::prelude::*;
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async fn run1(bus: &'static mut UsbBusAllocator<UsbBus<USB>>) {
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info!("Async task");
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let mut read_buf = [0u8; 128];
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let mut write_buf = [0u8; 128];
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let serial = UsbSerial::new(bus, &mut read_buf, &mut write_buf);
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let mut read_buf1 = [0u8; 128];
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let mut write_buf1 = [0u8; 128];
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let serial1 = UsbSerial::new(bus, &mut read_buf1, &mut write_buf1);
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let mut read_buf2 = [0u8; 128];
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let mut write_buf2 = [0u8; 128];
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let serial2 = UsbSerial::new(bus, &mut read_buf2, &mut write_buf2);
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let device = UsbDeviceBuilder::new(bus, UsbVidPid(0x16c0, 0x27dd))
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.manufacturer("Fake company")
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.product("Serial port")
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.serial_number("TEST")
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.device_class(0x02)
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//.device_class(0x02)
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.build();
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let irq = interrupt::take!(OTG_FS);
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irq.set_priority(interrupt::Priority::Level3);
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let usb = Usb::new(device, serial, irq);
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let usb = Usb::new(device, (serial1, serial2), irq);
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pin_mut!(usb);
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let (mut read_interface, mut write_interface) = usb.as_mut().into_ref().take_serial();
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let (mut read_interface1, mut write_interface1) = usb.as_ref().take_serial_0();
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let (mut read_interface2, mut write_interface2) = usb.as_ref().take_serial_1();
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let mut buf1 = [0u8; 64];
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let mut buf2 = [0u8; 64];
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let mut buf = [0u8; 5];
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loop {
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let recv_fut = read_interface.read(&mut buf);
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let timeout = Timer::after(Duration::from_ticks(32768 * 3));
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let mut n1 = 0;
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let mut n2 = 0;
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let left = {
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let read_line1 = async {
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loop {
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let byte = unwrap!(read_interface1.read_byte().await);
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unwrap!(write_interface1.write_byte(byte).await);
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buf1[n1] = byte;
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match select(recv_fut, timeout).await {
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Either::Left((recv, _)) => {
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let recv = unwrap!(recv);
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unwrap!(write_interface.write_all(&buf[..recv]).await);
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}
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Either::Right(_) => {
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unwrap!(write_interface.write_all(b"Hello\r\n").await);
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n1 += 1;
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if byte == b'\n' || n1 == buf1.len() {
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break;
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}
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}
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};
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pin_mut!(read_line1);
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let read_line2 = async {
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loop {
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let byte = unwrap!(read_interface2.read_byte().await);
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unwrap!(write_interface2.write_byte(byte).await);
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buf2[n2] = byte;
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n2 += 1;
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if byte == b'\n' || n2 == buf2.len() {
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break;
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}
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}
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};
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pin_mut!(read_line2);
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match select(read_line1, read_line2).await {
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Either::Left(_) => true,
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Either::Right(_) => false,
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}
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};
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if left {
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unwrap!(write_interface2.write_all(b"\r\n").await);
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unwrap!(write_interface2.write_all(&buf1[..n1]).await);
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} else {
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unwrap!(write_interface1.write_all(b"\r\n").await);
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unwrap!(write_interface1.write_all(&buf2[..n2]).await);
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}
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}
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}
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static RTC: Forever<rtc::RTC<pac::TIM2>> = Forever::new();
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static ALARM: Forever<rtc::Alarm<pac::TIM2>> = Forever::new();
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static EXECUTOR: Forever<Executor> = Forever::new();
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static USB_BUS: Forever<UsbBusAllocator<UsbBus<USB>>> = Forever::new();
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@ -91,14 +127,7 @@ fn main() -> ! {
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w.dbg_stop().set_bit()
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});
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let rtc = RTC.put(rtc::RTC::new(p.TIM2, interrupt::take!(TIM2), clocks));
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rtc.start();
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unsafe { embassy::time::set_clock(rtc) };
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let alarm = ALARM.put(rtc.alarm1());
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let executor = EXECUTOR.put(Executor::new());
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executor.set_alarm(alarm);
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let gpioa = p.GPIOA.split();
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let usb = USB {
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@ -10,12 +10,20 @@ use crate::interrupt;
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use crate::usb_serial::{ReadInterface, UsbSerial, WriteInterface};
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use crate::util::peripheral::{PeripheralMutex, PeripheralState};
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pub struct State<'bus, B: UsbBus, T: ClassSet<B>> {
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pub struct State<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B>,
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{
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device: UsbDevice<'bus, B>,
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pub(crate) classes: T,
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}
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pub struct Usb<'bus, B: UsbBus, T: ClassSet<B>> {
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pub struct Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B>,
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{
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// Don't you dare moving out `PeripheralMutex`
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inner: RefCell<PeripheralMutex<State<'bus, B, T>>>,
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}
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@ -53,24 +61,54 @@ where
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impl<'bus, 'c, B, T> Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B> + SerialState<'bus, 'c, B>,
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T: ClassSet<B> + SerialState<'bus, 'c, B, Index0>,
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{
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pub fn take_serial<'a>(
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pub fn take_serial_0<'a>(
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self: Pin<&'a Self>,
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) -> (
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ReadInterface<'a, 'bus, 'c, B, T>,
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WriteInterface<'a, 'bus, 'c, B, T>,
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ReadInterface<'a, 'bus, 'c, Index0, B, T>,
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WriteInterface<'a, 'bus, 'c, Index0, B, T>,
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) {
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let this = self.get_ref();
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let r = ReadInterface {
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inner: &this.inner,
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_buf_lifetime: PhantomData,
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_index: PhantomData,
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};
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let w = WriteInterface {
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inner: &this.inner,
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_buf_lifetime: PhantomData,
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_index: PhantomData,
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};
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(r, w)
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}
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}
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impl<'bus, 'c, B, T> Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B> + SerialState<'bus, 'c, B, Index1>,
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{
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pub fn take_serial_1<'a>(
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self: Pin<&'a Self>,
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) -> (
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ReadInterface<'a, 'bus, 'c, Index1, B, T>,
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WriteInterface<'a, 'bus, 'c, Index1, B, T>,
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) {
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let this = self.get_ref();
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let r = ReadInterface {
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inner: &this.inner,
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_buf_lifetime: PhantomData,
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_index: PhantomData,
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};
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let w = WriteInterface {
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inner: &this.inner,
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_buf_lifetime: PhantomData,
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_index: PhantomData,
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};
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(r, w)
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}
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@ -95,23 +133,56 @@ pub trait IntoClassSet<B: UsbBus, C: ClassSet<B>> {
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fn into_class_set(self) -> C;
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}
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pub struct ClassSet1<B: UsbBus, T: UsbClass<B>> {
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class: T,
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pub struct ClassSet1<B, C1>
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where
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B: UsbBus,
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C1: UsbClass<B>,
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{
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class: C1,
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_bus: PhantomData<B>,
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}
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impl<B, T> ClassSet<B> for ClassSet1<B, T>
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pub struct ClassSet2<B, C1, C2>
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where
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B: UsbBus,
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T: UsbClass<B>,
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C1: UsbClass<B>,
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C2: UsbClass<B>,
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{
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class1: C1,
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class2: C2,
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_bus: PhantomData<B>,
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}
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pub struct Index0;
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pub struct Index1;
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impl<B, C1> ClassSet<B> for ClassSet1<B, C1>
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where
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B: UsbBus,
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C1: UsbClass<B>,
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{
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fn poll_all(&mut self, device: &mut UsbDevice<'_, B>) -> bool {
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device.poll(&mut [&mut self.class])
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}
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}
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impl<B: UsbBus, T: UsbClass<B>> IntoClassSet<B, ClassSet1<B, T>> for T {
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fn into_class_set(self) -> ClassSet1<B, T> {
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impl<B, C1, C2> ClassSet<B> for ClassSet2<B, C1, C2>
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where
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B: UsbBus,
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C1: UsbClass<B>,
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C2: UsbClass<B>,
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{
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fn poll_all(&mut self, device: &mut UsbDevice<'_, B>) -> bool {
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device.poll(&mut [&mut self.class1, &mut self.class2])
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}
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}
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impl<B, C1> IntoClassSet<B, ClassSet1<B, C1>> for C1
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where
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B: UsbBus,
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C1: UsbClass<B>,
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{
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fn into_class_set(self) -> ClassSet1<B, C1> {
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ClassSet1 {
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class: self,
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_bus: PhantomData,
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@ -119,12 +190,49 @@ impl<B: UsbBus, T: UsbClass<B>> IntoClassSet<B, ClassSet1<B, T>> for T {
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}
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}
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pub trait SerialState<'bus, 'a, B: UsbBus> {
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impl<B, C1, C2> IntoClassSet<B, ClassSet2<B, C1, C2>> for (C1, C2)
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where
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B: UsbBus,
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C1: UsbClass<B>,
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C2: UsbClass<B>,
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{
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fn into_class_set(self) -> ClassSet2<B, C1, C2> {
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ClassSet2 {
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class1: self.0,
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class2: self.1,
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_bus: PhantomData,
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}
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}
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}
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pub trait SerialState<'bus, 'a, B: UsbBus, I> {
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fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B>;
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}
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impl<'bus, 'a, B: UsbBus> SerialState<'bus, 'a, B> for ClassSet1<B, UsbSerial<'bus, 'a, B>> {
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impl<'bus, 'a, B: UsbBus> SerialState<'bus, 'a, B, Index0>
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for ClassSet1<B, UsbSerial<'bus, 'a, B>>
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{
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fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
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&mut self.class
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}
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}
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impl<'bus, 'a, B, C2> SerialState<'bus, 'a, B, Index0> for ClassSet2<B, UsbSerial<'bus, 'a, B>, C2>
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where
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B: UsbBus,
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C2: UsbClass<B>,
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{
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fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
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&mut self.class1
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}
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}
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impl<'bus, 'a, B, C1> SerialState<'bus, 'a, B, Index1> for ClassSet2<B, C1, UsbSerial<'bus, 'a, B>>
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where
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B: UsbBus,
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C1: UsbClass<B>,
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{
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fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
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&mut self.class2
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}
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}
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@ -1,5 +1,5 @@
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use core::cell::RefCell;
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use core::marker::{PhantomData, PhantomPinned};
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use core::marker::{PhantomData, Unpin};
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use core::pin::Pin;
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use core::task::{Context, Poll};
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@ -14,26 +14,39 @@ use crate::usb::{ClassSet, SerialState, State};
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use crate::util::peripheral::PeripheralMutex;
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use crate::util::ring_buffer::RingBuffer;
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pub struct ReadInterface<'a, 'bus, 'c, B: UsbBus, T: SerialState<'bus, 'c, B> + ClassSet<B>> {
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pub struct ReadInterface<'a, 'bus, 'c, I, B, T>
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where
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I: Unpin,
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B: UsbBus,
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T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
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{
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// Don't you dare moving out `PeripheralMutex`
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pub(crate) inner: &'a RefCell<PeripheralMutex<State<'bus, B, T>>>,
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pub(crate) _buf_lifetime: PhantomData<&'c T>,
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pub(crate) _index: PhantomData<I>,
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}
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/// Write interface for USB CDC_ACM
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///
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/// This interface is buffered, meaning that after the write returns the bytes might not be fully
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/// on the wire just yet
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pub struct WriteInterface<'a, 'bus, 'c, B: UsbBus, T: SerialState<'bus, 'c, B> + ClassSet<B>> {
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pub struct WriteInterface<'a, 'bus, 'c, I, B, T>
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where
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I: Unpin,
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B: UsbBus,
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T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
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{
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// Don't you dare moving out `PeripheralMutex`
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pub(crate) inner: &'a RefCell<PeripheralMutex<State<'bus, B, T>>>,
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pub(crate) _buf_lifetime: PhantomData<&'c T>,
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pub(crate) _index: PhantomData<I>,
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}
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impl<'a, 'bus, 'c, B, T> AsyncBufRead for ReadInterface<'a, 'bus, 'c, B, T>
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impl<'a, 'bus, 'c, I, B, T> AsyncBufRead for ReadInterface<'a, 'bus, 'c, I, B, T>
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where
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I: Unpin,
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B: UsbBus,
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T: SerialState<'bus, 'c, B> + ClassSet<B>,
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T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
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{
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fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<io::Result<&[u8]>> {
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let this = self.get_mut();
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@ -68,10 +81,11 @@ where
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}
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}
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impl<'a, 'bus, 'c, B, T> AsyncWrite for WriteInterface<'a, 'bus, 'c, B, T>
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impl<'a, 'bus, 'c, I, B, T> AsyncWrite for WriteInterface<'a, 'bus, 'c, I, B, T>
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where
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I: Unpin,
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B: UsbBus,
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T: SerialState<'bus, 'c, B> + ClassSet<B>,
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T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
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{
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fn poll_write(
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self: Pin<&mut Self>,
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