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Wire up DMA with USART v1.

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This commit is contained in:
Bob McWhirter
2021-06-29 10:59:22 -04:00
parent b88fc2847a
commit c53ab325c1
5 changed files with 107 additions and 32 deletions
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5
embassy-stm32/src/usart/mod.rs
View File

@ -1,13 +1,14 @@
#![macro_use]
#[cfg_attr(usart_v1, path = "v1.rs")]
//#[cfg_attr(usart_v2, path = "v2.rs")]
#[cfg_attr(usart_v2, path = "v2.rs")]
mod _version;
use crate::peripherals;
pub use _version::*;
use crate::gpio::Pin;
use crate::pac::usart::Usart;
use crate::rcc::RccPeripheral;
/// Serial error
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
@ -51,7 +52,7 @@ pub(crate) mod sealed {
pub trait TxDma<T: Instance>: WriteDma<T> {}
}
pub trait Instance: sealed::Instance {}
pub trait Instance: sealed::Instance + RccPeripheral {}
pub trait RxPin<T: Instance>: sealed::RxPin<T> {}
pub trait TxPin<T: Instance>: sealed::TxPin<T> {}
pub trait CtsPin<T: Instance>: sealed::CtsPin<T> {}

27
embassy-stm32/src/usart/v1.rs
View File

@ -63,14 +63,17 @@ impl<'d, T: Instance> Uart<'d, T> {
rx: impl Unborrow<Target = impl RxPin<T>>,
tx: impl Unborrow<Target = impl TxPin<T>>,
config: Config,
pclk_freq: u32,
//pclk_freq: u32,
) -> Self {
unborrow!(inner, rx, tx);
let pclk_freq = T::frequency();
//let pclk_freq = 16_000_000;
// TODO: enable in RCC
// TODO: better calculation, including error checking and OVER8 if possible.
let div = (pclk_freq + (config.baudrate / 2)) / config.baudrate;
let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
let r = inner.regs();
@ -108,25 +111,15 @@ impl<'d, T: Instance> Uart<'d, T> {
ch: &mut impl TxDma<T>,
buffer: &[u8],
) -> Result<(), Error> {
unsafe {
self.inner.regs().cr3().modify(|reg| {
reg.set_dmat(true);
});
}
let r = self.inner.regs();
let dst = r.dr().ptr() as *mut u8;
ch.transfer(buffer, dst).await;
Ok(())
/*
let ch_func = 4; // USART3_TX
unsafe {
r.cr3().write(|w| {
w.set_dmat(true);
});
let dst = r.dr().ptr() as *mut u8;
crate::dma::transfer_m2p(ch, ch_func, buffer, dst).await;
}
Ok(())
*/
}
pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {