From f9ac0c80476db8cc33bd07beb7b48b6e96b053e7 Mon Sep 17 00:00:00 2001
From: Ulf Lilleengen <lulf@redhat.com>
Date: Tue, 7 Dec 2021 09:40:45 +0100
Subject: [PATCH] Add back MISO flush

---
 embassy-stm32/src/spi/v2.rs | 5 +++++
 embassy-stm32/src/spi/v3.rs | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs
index de78676c..e24710df 100644
--- a/embassy-stm32/src/spi/v2.rs
+++ b/embassy-stm32/src/spi/v2.rs
@@ -14,6 +14,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(false);
             });
+
+            // Flush the read buffer to avoid errornous data from being read
+            while T::regs().sr().read().rxne() {
+                let _ = T::regs().dr().read();
+            }
         }
         self.set_word_size(WordSize::EightBit);
 
diff --git a/embassy-stm32/src/spi/v3.rs b/embassy-stm32/src/spi/v3.rs
index ef0f2306..6d75de03 100644
--- a/embassy-stm32/src/spi/v3.rs
+++ b/embassy-stm32/src/spi/v3.rs
@@ -15,6 +15,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
             T::regs().cr1().modify(|w| {
                 w.set_spe(false);
             });
+
+            // Flush the read buffer to avoid errornous data from being read
+            while T::regs().sr().read().rxp() {
+                let _ = T::regs().rxdr().read();
+            }
         }
 
         let request = self.txdma.request();