stm32/rcc: add voltage_scale, flash waitstates.
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@ -1,10 +1,11 @@
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use super::bd::BackupDomain;
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use super::RtcClockSource;
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
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use crate::pac::RCC;
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#[cfg(crs)]
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use crate::pac::{crs, CRS, SYSCFG};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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@ -140,6 +141,7 @@ pub struct Config {
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pub rtc: Option<RtcClockSource>,
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pub lse: Option<Hertz>,
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pub lsi: bool,
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pub voltage_scale: VoltageScale,
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}
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impl Default for Config {
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@ -155,11 +157,17 @@ impl Default for Config {
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rtc: None,
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lse: None,
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lsi: false,
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voltage_scale: VoltageScale::RANGE1,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Set voltage scale
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while PWR.csr().read().vosf() {}
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PWR.cr().write(|w| w.set_vos(config.voltage_scale));
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while PWR.csr().read().vosf() {}
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let (sys_clk, sw) = match config.mux {
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ClockSrc::MSI(range) => {
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// Set MSI range
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@ -245,6 +253,22 @@ pub(crate) unsafe fn init(config: Config) {
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config.lse.map(|_| Default::default()),
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);
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let wait_states = match config.voltage_scale {
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VoltageScale::RANGE1 => match sys_clk {
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..=16_000_000 => 0,
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_ => 1,
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},
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VoltageScale::RANGE2 => match sys_clk {
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..=8_000_000 => 0,
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_ => 1,
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},
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VoltageScale::RANGE3 => 0,
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_ => unreachable!(),
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};
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FLASH.acr().modify(|w| {
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w.set_latency(wait_states != 0);
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});
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre.into());
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