stm32-wl: set RTC clock source on RCC init

This commit is contained in:
Olle Sandberg 2023-08-16 13:57:03 +02:00
parent dd5a886830
commit c80c323634

View File

@ -2,6 +2,7 @@ pub use super::common::{AHBPrescaler, APBPrescaler, VoltageScale};
use crate::pac::pwr::vals::Dbp; use crate::pac::pwr::vals::Dbp;
use crate::pac::{FLASH, PWR, RCC}; use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks}; use crate::rcc::{set_freqs, Clocks};
use crate::rtc::{Rtc, RtcClockSource as RCS};
use crate::time::Hertz; use crate::time::Hertz;
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC, /// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
@ -229,6 +230,8 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSE is running // Wait until LSE is running
while !RCC.bdcr().read().lserdy() {} while !RCC.bdcr().read().lserdy() {}
Rtc::set_clock_source(RCS::LSE);
} }
RtcClockSource::LSI32 => { RtcClockSource::LSI32 => {
// Turn on the internal 32 kHz LSI oscillator // Turn on the internal 32 kHz LSI oscillator
@ -236,6 +239,8 @@ pub(crate) unsafe fn init(config: Config) {
// Wait until LSI is running // Wait until LSI is running
while !RCC.csr().read().lsirdy() {} while !RCC.csr().read().lsirdy() {}
Rtc::set_clock_source(RCS::LSI);
} }
} }