diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..55150179 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "embassy-stm32/stm32-data"] + path = embassy-stm32/stm32-data + url = https://github.com/Dirbaio/stm32-data.git diff --git a/.vscode/settings.json b/.vscode/settings.json index 8a292c0b..ca242662 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,7 +1,6 @@ { "rust-analyzer.assist.importMergeBehavior": "last", "editor.formatOnSave": true, - "rust-analyzer.cargo.allFeatures": false, "rust-analyzer.checkOnSave.allFeatures": false, "rust-analyzer.checkOnSave.allTargets": false, "rust-analyzer.cargo.target": "thumbv7em-none-eabi", diff --git a/embassy-macros/src/lib.rs b/embassy-macros/src/lib.rs index dc234cd6..c2f928b9 100644 --- a/embassy-macros/src/lib.rs +++ b/embassy-macros/src/lib.rs @@ -197,7 +197,7 @@ pub fn interrupt_declare(item: TokenStream) -> TokenStream { type Priority = crate::interrupt::Priority; fn number(&self) -> u16 { use cortex_m::interrupt::InterruptNumber; - let irq = crate::pac::Interrupt::#name; + let irq = InterruptEnum::#name; irq.number() as u16 } unsafe fn steal() -> Self { diff --git a/embassy-stm32-examples/Cargo.toml b/embassy-stm32-examples/Cargo.toml new file mode 100644 index 00000000..8d1361cf --- /dev/null +++ b/embassy-stm32-examples/Cargo.toml @@ -0,0 +1,34 @@ +[package] +authors = ["Dario Nieuwenhuis "] +edition = "2018" +name = "embassy-stm32f4-examples" +version = "0.1.0" + +[features] +default = [ + "defmt-default", +] +defmt-default = [] +defmt-trace = [] +defmt-debug = [] +defmt-info = [] +defmt-warn = [] +defmt-error = [] + +[dependencies] +embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] } +embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] } +embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"] } +embassy-extras = {version = "0.1.0", path = "../embassy-extras" } +stm32f4 = { version = "0.13", features = ["stm32f429"] } + +defmt = "0.2.0" +defmt-rtt = "0.2.0" + +cortex-m = "0.7.1" +cortex-m-rt = "0.6.13" +embedded-hal = { version = "0.2.4" } +panic-probe = { version = "0.2.0", features= ["print-defmt"] } +futures = { version = "0.3.8", default-features = false, features = ["async-await"] } +rtt-target = { version = "0.3", features = ["cortex-m"] } +heapless = "0.7" \ No newline at end of file diff --git a/embassy-stm32-examples/src/bin/blinky.rs b/embassy-stm32-examples/src/bin/blinky.rs new file mode 100644 index 00000000..9ccd6c01 --- /dev/null +++ b/embassy-stm32-examples/src/bin/blinky.rs @@ -0,0 +1,53 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; +use embassy_stm32::gpio::{Level, Output}; +use embedded_hal::digital::v2::OutputPin; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; + +#[entry] +fn main() -> ! { + info!("Hello World!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled()); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + + let p = embassy_stm32::init(Default::default()); + + let mut led = Output::new(p.PB7, Level::High); + + loop { + info!("high"); + led.set_high().unwrap(); + cortex_m::asm::delay(10_000_000); + + info!("low"); + led.set_low().unwrap(); + cortex_m::asm::delay(10_000_000); + } +} diff --git a/embassy-stm32-examples/src/bin/button.rs b/embassy-stm32-examples/src/bin/button.rs new file mode 100644 index 00000000..c3421852 --- /dev/null +++ b/embassy-stm32-examples/src/bin/button.rs @@ -0,0 +1,58 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; +use embassy_stm32::gpio::{Input, Level, Output, Pull}; +use embedded_hal::digital::v2::{InputPin, OutputPin}; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; + +#[entry] +fn main() -> ! { + info!("Hello World!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled()); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + + let p = embassy_stm32::init(Default::default()); + + let button = Input::new(p.PC13, Pull::Down); + let mut led1 = Output::new(p.PB0, Level::High); + let _led2 = Output::new(p.PB7, Level::High); + let mut led3 = Output::new(p.PB14, Level::High); + + loop { + if button.is_high().unwrap() { + info!("high"); + led1.set_high().unwrap(); + led3.set_low().unwrap(); + } else { + info!("low"); + led1.set_low().unwrap(); + led3.set_high().unwrap(); + } + } +} diff --git a/embassy-stm32-examples/src/bin/button_exti.rs b/embassy-stm32-examples/src/bin/button_exti.rs new file mode 100644 index 00000000..d6f545fa --- /dev/null +++ b/embassy-stm32-examples/src/bin/button_exti.rs @@ -0,0 +1,82 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; +use embassy::executor::Executor; +use embassy::time::Clock; +use embassy::util::Forever; +use embassy_stm32::exti::{self, ExtiInput}; +use embassy_stm32::gpio::{Input, Pull}; +use embassy_traits::gpio::{WaitForFallingEdge, WaitForRisingEdge}; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; + +#[embassy::task] +async fn main_task() { + let p = embassy_stm32::init(Default::default()); + + let button = Input::new(p.PC13, Pull::Down); + let mut button = ExtiInput::new(button, p.EXTI13); + + info!("Press the USER button..."); + + loop { + button.wait_for_rising_edge().await; + info!("Pressed!"); + button.wait_for_falling_edge().await; + info!("Released!"); + } +} + +struct ZeroClock; + +impl Clock for ZeroClock { + fn now(&self) -> u64 { + 0 + } +} + +static EXECUTOR: Forever = Forever::new(); + +#[entry] +fn main() -> ! { + info!("Hello World!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled()); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + pp.RCC.apb2enr.modify(|_, w| { + w.syscfgen().enabled(); + w + }); + + unsafe { embassy::time::set_clock(&ZeroClock) }; + + let executor = EXECUTOR.put(Executor::new()); + + executor.run(|spawner| { + unwrap!(spawner.spawn(main_task())); + }) +} diff --git a/embassy-stm32-examples/src/bin/spi.rs b/embassy-stm32-examples/src/bin/spi.rs new file mode 100644 index 00000000..59ba0958 --- /dev/null +++ b/embassy-stm32-examples/src/bin/spi.rs @@ -0,0 +1,72 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; + +use embassy_stm32::gpio::{Input, Level, Output, Pull}; +use embedded_hal::digital::v2::{InputPin, OutputPin}; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; +//use stm32l4::stm32l4x5 as pac; +use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0}; +use embassy_stm32::time::Hertz; +use embedded_hal::blocking::spi::Transfer; + +#[entry] +fn main() -> ! { + info!("Hello World, dude!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().set_bit()); + + pp.RCC.apb1enr.modify(|_, w| { + w.spi3en().enabled(); + w + }); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + + let rc = pp.RCC.cfgr.read().sws().bits(); + let p = embassy_stm32::init(Default::default()); + + let mut spi = Spi::new( + Hertz(16_000_000), + p.SPI3, + p.PC10, + p.PC12, + p.PC11, + Hertz(1_000_000), + Config::default(), + ); + + let mut cs = Output::new(p.PE0, Level::High); + + loop { + let mut buf = [0x0A; 4]; + cs.set_low(); + spi.transfer(&mut buf); + cs.set_high(); + info!("xfer {=[u8]:x}", buf); + } +} diff --git a/embassy-stm32-examples/src/bin/usart.rs b/embassy-stm32-examples/src/bin/usart.rs new file mode 100644 index 00000000..d35fbf9f --- /dev/null +++ b/embassy-stm32-examples/src/bin/usart.rs @@ -0,0 +1,86 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; +use cortex_m::prelude::_embedded_hal_blocking_serial_Write; +use embassy::executor::Executor; +use embassy::time::Clock; +use embassy::util::Forever; +use embassy_stm32::gpio::NoPin; +use embassy_stm32::usart::{Config, Uart}; +use example_common::*; + +use cortex_m_rt::entry; +use stm32f4::stm32f429 as pac; + +#[embassy::task] +async fn main_task() { + let p = embassy_stm32::init(Default::default()); + + let config = Config::default(); + let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config, 16_000_000); + + usart.bwrite_all(b"Hello Embassy World!\r\n").unwrap(); + info!("wrote Hello, starting echo"); + + let mut buf = [0u8; 1]; + loop { + usart.read(&mut buf).unwrap(); + usart.bwrite_all(&buf).unwrap(); + } +} + +struct ZeroClock; + +impl Clock for ZeroClock { + fn now(&self) -> u64 { + 0 + } +} + +static EXECUTOR: Forever = Forever::new(); + +#[entry] +fn main() -> ! { + info!("Hello World!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled()); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w + }); + pp.RCC.apb2enr.modify(|_, w| { + w.syscfgen().enabled(); + w + }); + pp.RCC.apb1enr.modify(|_, w| { + w.usart3en().enabled(); + w + }); + + unsafe { embassy::time::set_clock(&ZeroClock) }; + + let executor = EXECUTOR.put(Executor::new()); + + executor.run(|spawner| { + unwrap!(spawner.spawn(main_task())); + }) +} diff --git a/embassy-stm32-examples/src/bin/usart_dma.rs b/embassy-stm32-examples/src/bin/usart_dma.rs new file mode 100644 index 00000000..c8b7d645 --- /dev/null +++ b/embassy-stm32-examples/src/bin/usart_dma.rs @@ -0,0 +1,89 @@ +#![no_std] +#![no_main] +#![feature(trait_alias)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] + +#[path = "../example_common.rs"] +mod example_common; +use core::fmt::Write; +use cortex_m_rt::entry; +use embassy::executor::Executor; +use embassy::time::Clock; +use embassy::util::Forever; +use embassy_stm32::usart::{Config, Uart}; +use example_common::*; +use heapless::String; +use stm32f4::stm32f429 as pac; + +#[embassy::task] +async fn main_task() { + let mut p = embassy_stm32::init(Default::default()); + + let config = Config::default(); + let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config, 16_000_000); + + for n in 0.. { + let mut s: String<128> = String::new(); + core::write!(&mut s, "Hello DMA World {}!\r\n", n).unwrap(); + + usart + .write_dma(&mut p.DMA1_CH3, s.as_bytes()) + .await + .unwrap(); + info!("wrote DMA"); + } +} + +struct ZeroClock; + +impl Clock for ZeroClock { + fn now(&self) -> u64 { + 0 + } +} + +static EXECUTOR: Forever = Forever::new(); + +#[entry] +fn main() -> ! { + info!("Hello World!"); + + let pp = pac::Peripherals::take().unwrap(); + + pp.DBGMCU.cr.modify(|_, w| { + w.dbg_sleep().set_bit(); + w.dbg_standby().set_bit(); + w.dbg_stop().set_bit() + }); + pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled()); + + pp.RCC.ahb1enr.modify(|_, w| { + w.gpioaen().enabled(); + w.gpioben().enabled(); + w.gpiocen().enabled(); + w.gpioden().enabled(); + w.gpioeen().enabled(); + w.gpiofen().enabled(); + w.dma1en().enabled(); + w.dma2en().enabled(); + w + }); + pp.RCC.apb2enr.modify(|_, w| { + w.syscfgen().enabled(); + w + }); + pp.RCC.apb1enr.modify(|_, w| { + w.usart3en().enabled(); + w + }); + + unsafe { embassy::time::set_clock(&ZeroClock) }; + + let executor = EXECUTOR.put(Executor::new()); + + executor.run(|spawner| { + unwrap!(spawner.spawn(main_task())); + }) +} diff --git a/embassy-stm32/.pep8 b/embassy-stm32/.pep8 new file mode 100644 index 00000000..c9a137c8 --- /dev/null +++ b/embassy-stm32/.pep8 @@ -0,0 +1,2 @@ +[pep8] +max_line_length = 255 \ No newline at end of file diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml new file mode 100644 index 00000000..3d5bb57c --- /dev/null +++ b/embassy-stm32/Cargo.toml @@ -0,0 +1,463 @@ +[package] +name = "embassy-stm32" +version = "0.1.0" +authors = ["Dario Nieuwenhuis "] +edition = "2018" + +[dependencies] +embassy = { version = "0.1.0", path = "../embassy" } +embassy-macros = { version = "0.1.0", path = "../embassy-macros" } +embassy-extras = {version = "0.1.0", path = "../embassy-extras" } +embassy-traits = {version = "0.1.0", path = "../embassy-traits" } + +defmt = { version = "0.2.0", optional = true } +log = { version = "0.4.11", optional = true } +cortex-m-rt = { version = "0.6.13", features = ["device"] } +cortex-m = "0.7.1" +embedded-hal = { version = "0.2.4" } +futures = { version = "0.3.5", default-features = false, features = ["async-await"] } +rand_core = { version = "0.6.2", optional = true } +sdio-host = { version = "0.5.0", optional = true } +embedded-sdmmc = { git = "https://github.com/thalesfragoso/embedded-sdmmc-rs", branch = "async", optional = true } + +[build-dependencies] +regex = "1.4.6" + +[features] +defmt-trace = [ ] +defmt-debug = [ ] +defmt-info = [ ] +defmt-warn = [ ] +defmt-error = [ ] +sdmmc-rs = ["embedded-sdmmc"] + +# BEGIN GENERATED FEATURES +stm32f401cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401cd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401rd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401vd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f401ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405oe = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f405zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f407zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410c8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410r8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410t8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f410tb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f411ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f412zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413mg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f413zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f415zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f417zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f423zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f427zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f429zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f437zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f439zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446mc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446me = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446zc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f446ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f469zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32f479zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",] +stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h723zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h725zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h730ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h730ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h730vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h730zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h733vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h733zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h735ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h735ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h735rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h735vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h735zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h742zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h743zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h745zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h747zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h750ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h750vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h750xb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h750zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h753zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h755bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h755ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h755xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h755zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h757ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h757bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h757ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h757xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h757zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3lg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7a3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b0ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b0ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b0rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b0vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b0zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32h7b3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",] +stm32l412c8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412k8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412r8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412t8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l412tb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l422cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l422kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l422rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l422tb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l431vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l432kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l432kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l433vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l442kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l443vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l451ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l452ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l462ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l462re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l462ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l471zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l475vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476je = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476jg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476me = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476mg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l476zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l485jc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l485je = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l486jg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l486qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l486rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l486vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l486zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496wg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l496zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4a6zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",] +stm32l4p5ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4p5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4q5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4r9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +stm32l4s9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",] +_dma = [] +_dma_v1 = [] +_dma_v2 = [] +_exti = [] +_exti_v1 = [] +_gpio = [] +_gpio_v2 = [] +_rng = [ "rand_core",] +_rng_v1 = [] +_sdmmc = [ "sdio-host",] +_sdmmc_v2 = [] +_spi = [] +_spi_v1 = [] +_spi_v2 = [] +_stm32f4 = [] +_stm32h7 = [] +_stm32l4 = [] +_stm32l4p = [] +_syscfg = [] +_syscfg_f4 = [] +_syscfg_h7 = [] +_syscfg_l4 = [] +_usart = [] +_usart_v1 = [] +_usart_v2 = [] +# END GENERATED FEATURES diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs new file mode 100644 index 00000000..7a46b3dc --- /dev/null +++ b/embassy-stm32/build.rs @@ -0,0 +1,34 @@ +use regex::Regex; +use std::fmt::Write as _; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +use std::{env, fs}; + +fn main() { + let chip = env::vars_os() + .map(|(a, _)| a.to_string_lossy().to_string()) + .find(|x| x.starts_with("CARGO_FEATURE_STM32")) + .expect("No stm32xx Cargo feature enabled") + .strip_prefix("CARGO_FEATURE_") + .unwrap() + .to_ascii_lowercase(); + + let mut device_x = String::new(); + + let chip_rs = fs::read_to_string(format!("src/pac/{}.rs", chip)).unwrap(); + let re = Regex::new("declare!\\(([a-zA-Z0-9_]+)\\)").unwrap(); + for c in re.captures_iter(&chip_rs) { + let name = c.get(1).unwrap().as_str(); + write!(&mut device_x, "PROVIDE({} = DefaultHandler);\n", name).unwrap(); + } + + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(device_x.as_bytes()) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=src/pac/{}.rs", chip); + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/embassy-stm32/gen.py b/embassy-stm32/gen.py new file mode 100644 index 00000000..3eb570f1 --- /dev/null +++ b/embassy-stm32/gen.py @@ -0,0 +1,279 @@ +import xmltodict +import yaml +import re +import json +import os +import toml +from collections import OrderedDict +from glob import glob + +abspath = os.path.abspath(__file__) +dname = os.path.dirname(abspath) +os.chdir(dname) + +# ======= load chips +chips = {} +for f in sorted(glob('stm32-data/data/chips/*.yaml')): + if 'STM32F4' not in f and 'STM32L4' not in f and 'STM32H7' not in f: + continue + with open(f, 'r') as f: + chip = yaml.load(f, Loader=yaml.CSafeLoader) + chip['name'] = chip['name'].lower() + chip['features'] = set() + family = chip["family"].lower().replace('+', 'p') + chip['features'].add(f'_{family}') + print(chip['name']) + chips[chip['name']] = chip + +# ======= load GPIO AF +gpio_afs = {} +for f in sorted(glob('stm32-data/data/gpio_af/*.yaml')): + name = f.split('/')[-1].split('.')[0] + with open(f, 'r') as f: + af = yaml.load(f, Loader=yaml.CSafeLoader) + gpio_afs[name] = af + +# ========= Generate pac/mod.rs + +with open('src/pac/mod.rs', 'w') as f: + for chip in chips.values(): + f.write( + f'#[cfg_attr(feature="{chip["name"]}", path="{chip["name"]}.rs")]\n') + f.write('mod chip;\n') + f.write('pub use chip::*;\n') + +# ========= Generate pac/stm32xxx.rs + +for chip in chips.values(): + print(f'generating {chip["name"]}') + with open(f'src/pac/{chip["name"]}.rs', 'w') as f: + + f.write(""" + #![allow(dead_code)] + #![allow(unused_imports)] + #![allow(non_snake_case)] + """) + + af = gpio_afs[chip['gpio_af']] + peripheral_names = [] # USART1, PA5, EXTI8 + peripheral_versions = {} # usart -> v1, syscfg -> f4 + pins = set() # set of all present pins. PA4, PA5... + + # TODO this should probably come from the yamls? + # We don't want to hardcode the EXTI peripheral addr + + gpio_base = chip['peripherals']['GPIOA']['address'] + gpio_stride = 0x400 + f.write(f""" + pub fn GPIO(n: usize) -> gpio::Gpio {{ + gpio::Gpio((0x{gpio_base:x} + 0x{gpio_stride:x}*n) as _) + }} + """) + + # ========= peripherals + + peripheral_names.extend((f'EXTI{x}' for x in range(16))) + + for (name, peri) in chip['peripherals'].items(): + if 'block' not in peri: + continue + + block = peri['block'] + block_mod, block_name = block.rsplit('/') + block_mod, block_version = block_mod.rsplit('_') + block_name = block_name.capitalize() + + # Check all peripherals have the same version: it's not OK for the same chip to use both usart_v1 and usart_v2 + if old_version := peripheral_versions.get(block_mod): + if old_version != block_version: + raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}') + peripheral_versions[block_mod] = block_version + + # Set features + chip['features'].add(f'_{block_mod}') + chip['features'].add(f'_{block_mod}_{block_version}') + + f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);') + + custom_singletons = False + + if block_mod == 'usart': + f.write(f'impl_usart!({name});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_RX'): + f.write(f'impl_usart_pin!({name}, RxPin, {pin}, {func});') + if func := funcs.get(f'{name}_TX'): + f.write(f'impl_usart_pin!({name}, TxPin, {pin}, {func});') + if func := funcs.get(f'{name}_CTS'): + f.write(f'impl_usart_pin!({name}, CtsPin, {pin}, {func});') + if func := funcs.get(f'{name}_RTS'): + f.write(f'impl_usart_pin!({name}, RtsPin, {pin}, {func});') + if func := funcs.get(f'{name}_CK'): + f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});') + + if block_mod == 'rng': + if 'RNG' in chip['interrupts']: + f.write(f'impl_rng!({name}, RNG);') + else: + f.write(f'impl_rng!({name}, HASH_RNG);') + + if block_mod == 'spi': + clock = peri['clock'] + f.write(f'impl_spi!({name}, {clock});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_SCK'): + f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});') + if func := funcs.get(f'{name}_MOSI'): + f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});') + if func := funcs.get(f'{name}_MISO'): + f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});') + + if block_mod == 'gpio': + custom_singletons = True + port = name[4:] + port_num = ord(port) - ord('A') + + assert peri['address'] == gpio_base + gpio_stride*port_num + + for pin_num in range(16): + pin = f'P{port}{pin_num}' + pins.add(pin) + peripheral_names.append(pin) + f.write(f'impl_gpio_pin!({pin}, {port_num}, {pin_num}, EXTI{pin_num});') + + if block_mod == 'dma': + custom_singletons = True + dma_num = int(name[3:])-1 # substract 1 because we want DMA1=0, DMA2=1 + for ch_num in range(8): + channel = f'{name}_CH{ch_num}' + peripheral_names.append(channel) + f.write(f'impl_dma_channel!({channel}, {dma_num}, {ch_num});') + + if peri['block'] == 'sdmmc_v2/SDMMC': + f.write(f'impl_sdmmc!({name});') + for pin, funcs in af.items(): + if pin in pins: + if func := funcs.get(f'{name}_CK'): + f.write(f'impl_sdmmc_pin!({name}, CkPin, {pin}, {func});') + if func := funcs.get(f'{name}_CMD'): + f.write(f'impl_sdmmc_pin!({name}, CmdPin, {pin}, {func});') + if func := funcs.get(f'{name}_D0'): + f.write(f'impl_sdmmc_pin!({name}, D0Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D1'): + f.write(f'impl_sdmmc_pin!({name}, D1Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D2'): + f.write(f'impl_sdmmc_pin!({name}, D2Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D3'): + f.write(f'impl_sdmmc_pin!({name}, D3Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D4'): + f.write(f'impl_sdmmc_pin!({name}, D4Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D5'): + f.write(f'impl_sdmmc_pin!({name}, D5Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D6'): + f.write(f'impl_sdmmc_pin!({name}, D6Pin, {pin}, {func});') + if func := funcs.get(f'{name}_D7'): + f.write(f'impl_sdmmc_pin!({name}, D7Pin, {pin}, {func});') + + if not custom_singletons: + peripheral_names.append(name) + + for mod, version in peripheral_versions.items(): + f.write(f'pub use regs::{mod}_{version} as {mod};') + + f.write(f""" + mod regs; + pub use regs::generic; + use embassy_extras::peripherals; + peripherals!({','.join(peripheral_names)}); + """) + + # ========= interrupts + + irq_variants = [] + irq_vectors = [] + irq_fns = [] + irq_declares = [] + + irqs = {num: name for name, num in chip['interrupts'].items()} + irq_count = max(irqs.keys()) + 1 + for num, name in irqs.items(): + irq_variants.append(f'{name} = {num},') + irq_fns.append(f'fn {name}();') + irq_declares.append(f'declare!({name});') + for num in range(irq_count): + if name := irqs.get(num): + irq_vectors.append(f'Vector {{ _handler: {name} }},') + else: + irq_vectors.append(f'Vector {{ _reserved: 0 }},') + + f.write(f""" + pub mod interrupt {{ + pub use cortex_m::interrupt::{{CriticalSection, Mutex}}; + pub use embassy::interrupt::{{declare, take, Interrupt}}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum {{ + {''.join(irq_variants)} + }} + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {{ + #[inline(always)] + fn number(self) -> u16 {{ + self as u16 + }} + }} + + {''.join(irq_declares)} + }} + mod interrupt_vector {{ + extern "C" {{ + {''.join(irq_fns)} + }} + pub union Vector {{ + _handler: unsafe extern "C" fn(), + _reserved: u32, + }} + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; {irq_count}] = [ + {''.join(irq_vectors)} + ]; + }} + """) + + +# ========= Update Cargo features + +feature_optional_deps = {} +feature_optional_deps['_rng'] = ['rand_core'] +feature_optional_deps['_sdmmc'] = ['sdio-host'] + +features = {} +extra_features = set() +for name, chip in chips.items(): + features[name] = sorted(list(chip['features'])) + for feature in chip['features']: + extra_features.add(feature) +for feature in sorted(list(extra_features)): + features[feature] = feature_optional_deps.get(feature) or [] + +SEPARATOR_START = '# BEGIN GENERATED FEATURES\n' +SEPARATOR_END = '# END GENERATED FEATURES\n' + +with open('Cargo.toml', 'r') as f: + cargo = f.read() +before, cargo = cargo.split(SEPARATOR_START, maxsplit=1) +_, after = cargo.split(SEPARATOR_END, maxsplit=1) +cargo = before + SEPARATOR_START + toml.dumps(features) + SEPARATOR_END + after +with open('Cargo.toml', 'w') as f: + f.write(cargo) + +# ========= Generate pac/regs.rs +os.system('cargo run --manifest-path ../../svd2rust/Cargo.toml -- generate --dir stm32-data/data/registers') +os.system('mv lib.rs src/pac/regs.rs') + +# ========= Update Cargo features +os.system('rustfmt src/pac/*') diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs new file mode 100644 index 00000000..feec4a91 --- /dev/null +++ b/embassy-stm32/src/dma/mod.rs @@ -0,0 +1,44 @@ +#![macro_use] + +#[cfg_attr(feature = "_dma_v1", path = "v1.rs")] +#[cfg_attr(feature = "_dma_v2", path = "v2.rs")] +mod _version; +pub use _version::*; + +use crate::pac; + +pub(crate) mod sealed { + use super::*; + + pub trait Channel { + fn num(&self) -> u8; + + fn dma_num(&self) -> u8 { + self.num() / 8 + } + fn ch_num(&self) -> u8 { + self.num() % 8 + } + + fn regs(&self) -> pac::dma::Dma { + match self.dma_num() { + 0 => pac::DMA1, + _ => pac::DMA2, + } + } + } +} + +pub trait Channel: sealed::Channel + Sized {} + +macro_rules! impl_dma_channel { + ($type:ident, $dma_num:expr, $ch_num:expr) => { + impl crate::dma::Channel for peripherals::$type {} + impl crate::dma::sealed::Channel for peripherals::$type { + #[inline] + fn num(&self) -> u8 { + $dma_num * 8 + $ch_num + } + } + }; +} diff --git a/embassy-stm32/src/dma/v1.rs b/embassy-stm32/src/dma/v1.rs new file mode 100644 index 00000000..4544108e --- /dev/null +++ b/embassy-stm32/src/dma/v1.rs @@ -0,0 +1,2 @@ +/// safety: must be called only once +pub(crate) unsafe fn init() {} diff --git a/embassy-stm32/src/dma/v2.rs b/embassy-stm32/src/dma/v2.rs new file mode 100644 index 00000000..63d0586f --- /dev/null +++ b/embassy-stm32/src/dma/v2.rs @@ -0,0 +1,187 @@ +use core::sync::atomic::{AtomicU8, Ordering}; +use core::task::Poll; +use embassy::interrupt::{Interrupt, InterruptExt}; +use embassy::util::AtomicWaker; +use futures::future::poll_fn; + +use super::*; +use crate::fmt::{assert, *}; +use crate::interrupt; +use crate::pac; +use crate::pac::dma::{regs, vals}; + +const DMAS: [pac::dma::Dma; 2] = [pac::DMA1, pac::DMA2]; + +const CH_COUNT: usize = 16; +const CH_STATUS_NONE: u8 = 0; +const CH_STATUS_COMPLETED: u8 = 1; +const CH_STATUS_ERROR: u8 = 2; + +struct State { + ch_wakers: [AtomicWaker; CH_COUNT], + ch_status: [AtomicU8; CH_COUNT], +} + +impl State { + const fn new() -> Self { + const AW: AtomicWaker = AtomicWaker::new(); + const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE); + Self { + ch_wakers: [AW; CH_COUNT], + ch_status: [AU; CH_COUNT], + } + } +} + +static STATE: State = State::new(); + +pub(crate) async unsafe fn transfer_m2p( + ch: &mut impl Channel, + ch_func: u8, + src: &[u8], + dst: *mut u8, +) { + let n = ch.num() as usize; + let r = ch.regs(); + let c = r.st(ch.ch_num() as _); + + // ndtr is max 16 bits. + assert!(src.len() <= 0xFFFF); + + // Reset status + STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Relaxed); + + unsafe { + c.par().write_value(dst as _); + c.m0ar().write_value(src.as_ptr() as _); + c.ndtr().write_value(regs::Ndtr(src.len() as _)); + c.cr().write(|w| { + w.set_dir(vals::Dir::MEMORYTOPERIPHERAL); + w.set_msize(vals::Size::BITS8); + w.set_psize(vals::Size::BITS8); + w.set_minc(vals::Inc::INCREMENTED); + w.set_pinc(vals::Inc::FIXED); + w.set_chsel(ch_func); + w.set_teie(true); + w.set_tcie(true); + w.set_en(true); + }); + } + + let res = poll_fn(|cx| { + STATE.ch_wakers[n].register(cx.waker()); + match STATE.ch_status[n].load(Ordering::Relaxed) { + CH_STATUS_NONE => Poll::Pending, + x => Poll::Ready(x), + } + }) + .await; + + // TODO handle error + assert!(res == CH_STATUS_COMPLETED); +} + +unsafe fn on_irq() { + for (dman, &dma) in DMAS.iter().enumerate() { + for isrn in 0..2 { + let isr = dma.isr(isrn).read(); + dma.ifcr(isrn).write_value(isr); + + for chn in 0..4 { + let n = dman * 8 + isrn * 4 + chn; + if isr.teif(chn) { + STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed); + STATE.ch_wakers[n].wake(); + } else if isr.tcif(chn) { + STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed); + STATE.ch_wakers[n].wake(); + } + } + } + } +} + +#[interrupt] +unsafe fn DMA1_Stream0() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream1() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream2() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream3() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream4() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream5() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream6() { + on_irq() +} +#[interrupt] +unsafe fn DMA1_Stream7() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream0() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream1() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream2() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream3() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream4() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream5() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream6() { + on_irq() +} +#[interrupt] +unsafe fn DMA2_Stream7() { + on_irq() +} + +/// safety: must be called only once +pub(crate) unsafe fn init() { + interrupt::DMA1_Stream0::steal().enable(); + interrupt::DMA1_Stream1::steal().enable(); + interrupt::DMA1_Stream2::steal().enable(); + interrupt::DMA1_Stream3::steal().enable(); + interrupt::DMA1_Stream4::steal().enable(); + interrupt::DMA1_Stream5::steal().enable(); + interrupt::DMA1_Stream6::steal().enable(); + interrupt::DMA1_Stream7::steal().enable(); + interrupt::DMA2_Stream0::steal().enable(); + interrupt::DMA2_Stream1::steal().enable(); + interrupt::DMA2_Stream2::steal().enable(); + interrupt::DMA2_Stream3::steal().enable(); + interrupt::DMA2_Stream4::steal().enable(); + interrupt::DMA2_Stream5::steal().enable(); + interrupt::DMA2_Stream6::steal().enable(); + interrupt::DMA2_Stream7::steal().enable(); +} \ No newline at end of file diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs new file mode 100644 index 00000000..fb1c6cd3 --- /dev/null +++ b/embassy-stm32/src/exti.rs @@ -0,0 +1,263 @@ +#![macro_use] +use core::convert::Infallible; +use core::future::Future; +use core::marker::PhantomData; +use core::pin::Pin; +use core::task::{Context, Poll}; +use embassy::interrupt::{Interrupt, InterruptExt}; +use embassy::traits::gpio::{WaitForAnyEdge, WaitForFallingEdge, WaitForRisingEdge}; +use embassy::util::{AtomicWaker, Unborrow}; +use embassy_extras::impl_unborrow; +use embedded_hal::digital::v2::InputPin; +use pac::exti::{regs, vals}; + +use crate::fmt::*; +use crate::gpio::{AnyPin, Input, Pin as GpioPin}; +use crate::interrupt; +use crate::pac; +use crate::pac::{EXTI, SYSCFG}; +use crate::peripherals; + +const EXTI_COUNT: usize = 16; +const NEW_AW: AtomicWaker = AtomicWaker::new(); +static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [NEW_AW; EXTI_COUNT]; + +#[interrupt] +unsafe fn EXTI0() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI1() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI2() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI3() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI4() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI9_5() { + on_irq() +} + +#[interrupt] +unsafe fn EXTI15_10() { + on_irq() +} + +pub unsafe fn on_irq() { + let bits = EXTI.pr().read().0; + + // Mask all the channels that fired. + EXTI.imr().modify(|w| w.0 &= !bits); + + // Wake the tasks + for pin in BitIter(bits) { + EXTI_WAKERS[pin as usize].wake(); + } + + // Clear pending + EXTI.pr().write_value(regs::Pr(bits)); +} + +struct BitIter(u32); + +impl Iterator for BitIter { + type Item = u32; + + fn next(&mut self) -> Option { + match self.0.trailing_zeros() { + 32 => None, + b => { + self.0 &= !(1 << b); + Some(b) + } + } + } +} + +/// EXTI input driver +pub struct ExtiInput<'d, T: GpioPin> { + pin: Input<'d, T>, +} + +impl<'d, T: GpioPin> Unpin for ExtiInput<'d, T> {} + +impl<'d, T: GpioPin> ExtiInput<'d, T> { + pub fn new(pin: Input<'d, T>, _ch: impl Unborrow + 'd) -> Self { + Self { pin } + } +} + +impl<'d, T: GpioPin> InputPin for ExtiInput<'d, T> { + type Error = Infallible; + + fn is_high(&self) -> Result { + self.pin.is_high() + } + + fn is_low(&self) -> Result { + self.pin.is_low() + } +} + +impl<'d, T: GpioPin> WaitForRisingEdge for ExtiInput<'d, T> { + type Future<'a> = ExtiInputFuture<'a>; + + fn wait_for_rising_edge<'a>(&'a mut self) -> Self::Future<'a> { + ExtiInputFuture::new( + self.pin.pin.pin(), + self.pin.pin.port(), + vals::Tr::ENABLED, + vals::Tr::DISABLED, + ) + } +} + +impl<'d, T: GpioPin> WaitForFallingEdge for ExtiInput<'d, T> { + type Future<'a> = ExtiInputFuture<'a>; + + fn wait_for_falling_edge<'a>(&'a mut self) -> Self::Future<'a> { + ExtiInputFuture::new( + self.pin.pin.pin(), + self.pin.pin.port(), + vals::Tr::DISABLED, + vals::Tr::ENABLED, + ) + } +} + +impl<'d, T: GpioPin> WaitForAnyEdge for ExtiInput<'d, T> { + type Future<'a> = ExtiInputFuture<'a>; + + fn wait_for_any_edge<'a>(&'a mut self) -> Self::Future<'a> { + ExtiInputFuture::new( + self.pin.pin.pin(), + self.pin.pin.port(), + vals::Tr::ENABLED, + vals::Tr::ENABLED, + ) + } +} + +pub struct ExtiInputFuture<'a> { + pin: u8, + phantom: PhantomData<&'a mut AnyPin>, +} + +impl<'a> ExtiInputFuture<'a> { + fn new(pin: u8, port: u8, rising: vals::Tr, falling: vals::Tr) -> Self { + cortex_m::interrupt::free(|_| unsafe { + let pin = pin as usize; + SYSCFG.exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port)); + EXTI.rtsr().modify(|w| w.set_tr(pin, rising)); + EXTI.ftsr().modify(|w| w.set_tr(pin, falling)); + EXTI.pr().write(|w| w.set_pr(pin, true)); // clear pending bit + EXTI.imr().modify(|w| w.set_mr(pin, vals::Mr::UNMASKED)); + }); + + Self { + pin, + phantom: PhantomData, + } + } +} + +impl<'a> Drop for ExtiInputFuture<'a> { + fn drop(&mut self) { + cortex_m::interrupt::free(|_| unsafe { + let pin = self.pin as _; + EXTI.imr().modify(|w| w.set_mr(pin, vals::Mr::MASKED)); + }); + } +} + +impl<'a> Future for ExtiInputFuture<'a> { + type Output = (); + + fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll { + EXTI_WAKERS[self.pin as usize].register(cx.waker()); + + if unsafe { EXTI.imr().read().mr(self.pin as _) == vals::Mr::MASKED } { + Poll::Ready(()) + } else { + Poll::Pending + } + } +} + +pub(crate) mod sealed { + pub trait Channel {} +} + +pub trait Channel: sealed::Channel + Sized { + fn number(&self) -> usize; + fn degrade(self) -> AnyChannel { + AnyChannel { + number: self.number() as u8, + } + } +} + +pub struct AnyChannel { + number: u8, +} +impl_unborrow!(AnyChannel); +impl sealed::Channel for AnyChannel {} +impl Channel for AnyChannel { + fn number(&self) -> usize { + self.number as usize + } +} + +macro_rules! impl_exti { + ($type:ident, $number:expr) => { + impl sealed::Channel for peripherals::$type {} + impl Channel for peripherals::$type { + fn number(&self) -> usize { + $number as usize + } + } + }; +} + +impl_exti!(EXTI0, 0); +impl_exti!(EXTI1, 1); +impl_exti!(EXTI2, 2); +impl_exti!(EXTI3, 3); +impl_exti!(EXTI4, 4); +impl_exti!(EXTI5, 5); +impl_exti!(EXTI6, 6); +impl_exti!(EXTI7, 7); +impl_exti!(EXTI8, 8); +impl_exti!(EXTI9, 9); +impl_exti!(EXTI10, 10); +impl_exti!(EXTI11, 11); +impl_exti!(EXTI12, 12); +impl_exti!(EXTI13, 13); +impl_exti!(EXTI14, 14); +impl_exti!(EXTI15, 15); + +/// safety: must be called only once +pub(crate) unsafe fn init() { + interrupt::EXTI0::steal().enable(); + interrupt::EXTI1::steal().enable(); + interrupt::EXTI2::steal().enable(); + interrupt::EXTI3::steal().enable(); + interrupt::EXTI4::steal().enable(); + interrupt::EXTI9_5::steal().enable(); + interrupt::EXTI15_10::steal().enable(); + interrupt::EXTI15_10::steal().enable(); +} diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs new file mode 100644 index 00000000..d36d4a29 --- /dev/null +++ b/embassy-stm32/src/gpio.rs @@ -0,0 +1,330 @@ +#![macro_use] +use core::convert::Infallible; +use core::marker::PhantomData; +use embassy::util::Unborrow; +use embassy_extras::{impl_unborrow, unborrow}; +use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin}; + +use crate::pac; +use crate::pac::gpio::{self, vals}; + +/// Pull setting for an input. +#[derive(Debug, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Pull { + None, + Up, + Down, +} + +/// GPIO input driver. +pub struct Input<'d, T: Pin> { + pub(crate) pin: T, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Pin> Input<'d, T> { + pub fn new(pin: impl Unborrow + 'd, pull: Pull) -> Self { + unborrow!(pin); + + cortex_m::interrupt::free(|_| unsafe { + let r = pin.block(); + let n = pin.pin() as usize; + let val = match pull { + Pull::None => vals::Pupdr::FLOATING, + Pull::Up => vals::Pupdr::PULLUP, + Pull::Down => vals::Pupdr::PULLDOWN, + }; + r.pupdr().modify(|w| w.set_pupdr(n, val)); + r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL)); + r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT)); + }); + + Self { + pin, + phantom: PhantomData, + } + } +} + +impl<'d, T: Pin> Drop for Input<'d, T> { + fn drop(&mut self) { + cortex_m::interrupt::free(|_| unsafe { + let r = self.pin.block(); + let n = self.pin.pin() as usize; + r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING)); + }); + } +} + +impl<'d, T: Pin> InputPin for Input<'d, T> { + type Error = Infallible; + + fn is_high(&self) -> Result { + self.is_low().map(|v| !v) + } + + fn is_low(&self) -> Result { + let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as _) }; + Ok(state == vals::Idr::LOW) + } +} + +/// Digital input or output level. +#[derive(Debug, Eq, PartialEq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Level { + Low, + High, +} + +/// GPIO output driver. +pub struct Output<'d, T: Pin> { + pub(crate) pin: T, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Pin> Output<'d, T> { + pub fn new(pin: impl Unborrow + 'd, initial_output: Level) -> Self { + unborrow!(pin); + + match initial_output { + Level::High => pin.set_high(), + Level::Low => pin.set_low(), + } + + cortex_m::interrupt::free(|_| unsafe { + let r = pin.block(); + let n = pin.pin() as usize; + r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING)); + r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT)); + }); + + Self { + pin, + phantom: PhantomData, + } + } +} + +impl<'d, T: Pin> Drop for Output<'d, T> { + fn drop(&mut self) { + cortex_m::interrupt::free(|_| unsafe { + let r = self.pin.block(); + let n = self.pin.pin() as usize; + r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING)); + r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT)); + }); + } +} + +impl<'d, T: Pin> OutputPin for Output<'d, T> { + type Error = Infallible; + + /// Set the output as high. + fn set_high(&mut self) -> Result<(), Self::Error> { + self.pin.set_high(); + Ok(()) + } + + /// Set the output as low. + fn set_low(&mut self) -> Result<(), Self::Error> { + self.pin.set_low(); + Ok(()) + } +} + +impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> { + /// Is the output pin set as high? + fn is_set_high(&self) -> Result { + self.is_set_low().map(|v| !v) + } + + /// Is the output pin set as low? + fn is_set_low(&self) -> Result { + let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) }; + Ok(state == vals::Odr::LOW) + } +} + +pub(crate) mod sealed { + use super::*; + + pub trait Pin { + fn pin_port(&self) -> u8; + + #[inline] + fn _pin(&self) -> u8 { + self.pin_port() % 16 + } + #[inline] + fn _port(&self) -> u8 { + self.pin_port() / 16 + } + + #[inline] + fn block(&self) -> gpio::Gpio { + pac::GPIO(self._port() as _) + } + + /// Set the output as high. + #[inline] + fn set_high(&self) { + unsafe { + let n = self._pin() as _; + self.block().bsrr().write(|w| w.set_bs(n, true)); + } + } + + /// Set the output as low. + #[inline] + fn set_low(&self) { + unsafe { + let n = self._pin() as _; + self.block().bsrr().write(|w| w.set_br(n, true)); + } + } + + unsafe fn set_as_af(&self, af_num: u8) { + let pin = self._pin() as usize; + let block = self.block(); + block + .moder() + .modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE)); + block + .afr(pin / 8) + .modify(|w| w.set_afr(pin % 8, vals::Afr(af_num))); + } + + unsafe fn set_as_analog(&self) { + let pin = self._pin() as usize; + let block = self.block(); + block + .moder() + .modify(|w| w.set_moder(pin, vals::Moder::ANALOG)); + } + } + + pub trait OptionalPin {} +} + +pub trait Pin: sealed::Pin + Sized { + type ExtiChannel: crate::exti::Channel; + + /// Number of the pin within the port (0..31) + #[inline] + fn pin(&self) -> u8 { + self._pin() + } + + /// Port of the pin + #[inline] + fn port(&self) -> u8 { + self._port() + } + + /// Convert from concrete pin type PX_XX to type erased `AnyPin`. + #[inline] + fn degrade(self) -> AnyPin { + AnyPin { + pin_port: self.pin_port(), + } + } +} + +// Type-erased GPIO pin +pub struct AnyPin { + pin_port: u8, +} + +impl AnyPin { + #[inline] + pub unsafe fn steal(pin_port: u8) -> Self { + Self { pin_port } + } + + #[inline] + fn _port(&self) -> u8 { + self.pin_port / 16 + } + + #[inline] + pub fn block(&self) -> gpio::Gpio { + pac::GPIO(self._port() as _) + } +} + +impl_unborrow!(AnyPin); +impl Pin for AnyPin { + type ExtiChannel = crate::exti::AnyChannel; +} +impl sealed::Pin for AnyPin { + #[inline] + fn pin_port(&self) -> u8 { + self.pin_port + } +} + +// ==================== + +pub trait OptionalPin: sealed::OptionalPin + Sized { + type Pin: Pin; + fn pin(&self) -> Option<&Self::Pin>; + fn pin_mut(&mut self) -> Option<&mut Self::Pin>; + + /// Convert from concrete pin type PX_XX to type erased `Option`. + #[inline] + fn degrade_optional(mut self) -> Option { + self.pin_mut() + .map(|pin| unsafe { core::ptr::read(pin) }.degrade()) + } +} + +impl sealed::OptionalPin for T {} +impl OptionalPin for T { + type Pin = T; + + #[inline] + fn pin(&self) -> Option<&T> { + Some(self) + } + + #[inline] + fn pin_mut(&mut self) -> Option<&mut T> { + Some(self) + } +} + +#[derive(Clone, Copy, Debug)] +pub struct NoPin; +impl_unborrow!(NoPin); +impl sealed::OptionalPin for NoPin {} +impl OptionalPin for NoPin { + type Pin = AnyPin; + + #[inline] + fn pin(&self) -> Option<&AnyPin> { + None + } + + #[inline] + fn pin_mut(&mut self) -> Option<&mut AnyPin> { + None + } +} + +// ==================== + +macro_rules! impl_gpio_pin { + ($type:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => { + impl crate::gpio::Pin for peripherals::$type { + type ExtiChannel = peripherals::$exti_ch; + } + impl crate::gpio::sealed::Pin for peripherals::$type { + #[inline] + fn pin_port(&self) -> u8 { + $port_num * 16 + $pin_num + } + } + }; +} diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs new file mode 100644 index 00000000..8f11c2f8 --- /dev/null +++ b/embassy-stm32/src/lib.rs @@ -0,0 +1,59 @@ +#![no_std] +#![feature(generic_associated_types)] +#![feature(asm)] +#![feature(min_type_alias_impl_trait)] +#![feature(impl_trait_in_bindings)] +#![feature(type_alias_impl_trait)] +#![allow(incomplete_features)] + +// This must go FIRST so that all the other modules see its macros. +pub mod fmt; + +use embassy::interrupt::{Interrupt, InterruptExt}; + +#[cfg(feature = "_dma")] +pub mod dma; +pub mod exti; +pub mod gpio; +#[cfg(feature = "_rng")] +pub mod rng; +#[cfg(feature = "_sdmmc")] +pub mod sdmmc; +#[cfg(feature = "_spi")] +pub mod spi; +#[cfg(feature = "_usart")] +pub mod usart; + +// This must go LAST so that it sees the `impl_foo!` macros +mod pac; + +pub mod time; + +pub use embassy_macros::interrupt; +pub use pac::{interrupt, peripherals, Peripherals}; + +// workaround for svd2rust-generated code using `use crate::generic::*;` +pub(crate) use pac::generic; + +#[non_exhaustive] +pub struct Config { + _private: (), +} + +impl Default for Config { + fn default() -> Self { + Self { _private: () } + } +} + +/// Initialize embassy. +pub fn init(_config: Config) -> Peripherals { + let p = Peripherals::take(); + + unsafe { + exti::init(); + dma::init(); + } + + p +} diff --git a/embassy-stm32/src/pac/mod.rs b/embassy-stm32/src/pac/mod.rs new file mode 100644 index 00000000..2dfd2962 --- /dev/null +++ b/embassy-stm32/src/pac/mod.rs @@ -0,0 +1,405 @@ +#[cfg_attr(feature = "stm32f401cb", path = "stm32f401cb.rs")] +#[cfg_attr(feature = "stm32f401cc", path = "stm32f401cc.rs")] +#[cfg_attr(feature = "stm32f401cd", path = "stm32f401cd.rs")] +#[cfg_attr(feature = "stm32f401ce", path = "stm32f401ce.rs")] +#[cfg_attr(feature = "stm32f401rb", path = "stm32f401rb.rs")] +#[cfg_attr(feature = "stm32f401rc", path = "stm32f401rc.rs")] +#[cfg_attr(feature = "stm32f401rd", path = "stm32f401rd.rs")] +#[cfg_attr(feature = "stm32f401re", path = "stm32f401re.rs")] +#[cfg_attr(feature = "stm32f401vb", path = "stm32f401vb.rs")] +#[cfg_attr(feature = "stm32f401vc", path = "stm32f401vc.rs")] +#[cfg_attr(feature = "stm32f401vd", path = "stm32f401vd.rs")] +#[cfg_attr(feature = "stm32f401ve", path = "stm32f401ve.rs")] +#[cfg_attr(feature = "stm32f405oe", path = "stm32f405oe.rs")] +#[cfg_attr(feature = "stm32f405og", path = "stm32f405og.rs")] +#[cfg_attr(feature = "stm32f405rg", path = "stm32f405rg.rs")] +#[cfg_attr(feature = "stm32f405vg", path = "stm32f405vg.rs")] +#[cfg_attr(feature = "stm32f405zg", path = "stm32f405zg.rs")] +#[cfg_attr(feature = "stm32f407ie", path = "stm32f407ie.rs")] +#[cfg_attr(feature = "stm32f407ig", path = "stm32f407ig.rs")] +#[cfg_attr(feature = "stm32f407ve", path = "stm32f407ve.rs")] +#[cfg_attr(feature = "stm32f407vg", path = "stm32f407vg.rs")] +#[cfg_attr(feature = "stm32f407ze", path = "stm32f407ze.rs")] +#[cfg_attr(feature = "stm32f407zg", path = "stm32f407zg.rs")] +#[cfg_attr(feature = "stm32f410c8", path = "stm32f410c8.rs")] +#[cfg_attr(feature = "stm32f410cb", path = "stm32f410cb.rs")] +#[cfg_attr(feature = "stm32f410r8", path = "stm32f410r8.rs")] +#[cfg_attr(feature = "stm32f410rb", path = "stm32f410rb.rs")] +#[cfg_attr(feature = "stm32f410t8", path = "stm32f410t8.rs")] +#[cfg_attr(feature = "stm32f410tb", path = "stm32f410tb.rs")] +#[cfg_attr(feature = "stm32f411cc", path = "stm32f411cc.rs")] +#[cfg_attr(feature = "stm32f411ce", path = "stm32f411ce.rs")] +#[cfg_attr(feature = "stm32f411rc", path = "stm32f411rc.rs")] +#[cfg_attr(feature = "stm32f411re", path = "stm32f411re.rs")] +#[cfg_attr(feature = "stm32f411vc", path = "stm32f411vc.rs")] +#[cfg_attr(feature = "stm32f411ve", path = "stm32f411ve.rs")] +#[cfg_attr(feature = "stm32f412ce", path = "stm32f412ce.rs")] +#[cfg_attr(feature = "stm32f412cg", path = "stm32f412cg.rs")] +#[cfg_attr(feature = "stm32f412re", path = "stm32f412re.rs")] +#[cfg_attr(feature = "stm32f412rg", path = "stm32f412rg.rs")] +#[cfg_attr(feature = "stm32f412ve", path = "stm32f412ve.rs")] +#[cfg_attr(feature = "stm32f412vg", path = "stm32f412vg.rs")] +#[cfg_attr(feature = "stm32f412ze", path = "stm32f412ze.rs")] +#[cfg_attr(feature = "stm32f412zg", path = "stm32f412zg.rs")] +#[cfg_attr(feature = "stm32f413cg", path = "stm32f413cg.rs")] +#[cfg_attr(feature = "stm32f413ch", path = "stm32f413ch.rs")] +#[cfg_attr(feature = "stm32f413mg", path = "stm32f413mg.rs")] +#[cfg_attr(feature = "stm32f413mh", path = "stm32f413mh.rs")] +#[cfg_attr(feature = "stm32f413rg", path = "stm32f413rg.rs")] +#[cfg_attr(feature = "stm32f413rh", path = "stm32f413rh.rs")] +#[cfg_attr(feature = "stm32f413vg", path = "stm32f413vg.rs")] +#[cfg_attr(feature = "stm32f413vh", path = "stm32f413vh.rs")] +#[cfg_attr(feature = "stm32f413zg", path = "stm32f413zg.rs")] +#[cfg_attr(feature = "stm32f413zh", path = "stm32f413zh.rs")] +#[cfg_attr(feature = "stm32f415og", path = "stm32f415og.rs")] +#[cfg_attr(feature = "stm32f415rg", path = "stm32f415rg.rs")] +#[cfg_attr(feature = "stm32f415vg", path = "stm32f415vg.rs")] +#[cfg_attr(feature = "stm32f415zg", path = "stm32f415zg.rs")] +#[cfg_attr(feature = "stm32f417ie", path = "stm32f417ie.rs")] +#[cfg_attr(feature = "stm32f417ig", path = "stm32f417ig.rs")] +#[cfg_attr(feature = "stm32f417ve", path = "stm32f417ve.rs")] +#[cfg_attr(feature = "stm32f417vg", path = "stm32f417vg.rs")] +#[cfg_attr(feature = "stm32f417ze", path = "stm32f417ze.rs")] +#[cfg_attr(feature = "stm32f417zg", path = "stm32f417zg.rs")] +#[cfg_attr(feature = "stm32f423ch", path = "stm32f423ch.rs")] +#[cfg_attr(feature = "stm32f423mh", path = "stm32f423mh.rs")] +#[cfg_attr(feature = "stm32f423rh", path = "stm32f423rh.rs")] +#[cfg_attr(feature = "stm32f423vh", path = "stm32f423vh.rs")] +#[cfg_attr(feature = "stm32f423zh", path = "stm32f423zh.rs")] +#[cfg_attr(feature = "stm32f427ag", path = "stm32f427ag.rs")] +#[cfg_attr(feature = "stm32f427ai", path = "stm32f427ai.rs")] +#[cfg_attr(feature = "stm32f427ig", path = "stm32f427ig.rs")] +#[cfg_attr(feature = "stm32f427ii", path = "stm32f427ii.rs")] +#[cfg_attr(feature = "stm32f427vg", path = "stm32f427vg.rs")] +#[cfg_attr(feature = "stm32f427vi", path = "stm32f427vi.rs")] +#[cfg_attr(feature = "stm32f427zg", path = "stm32f427zg.rs")] +#[cfg_attr(feature = "stm32f427zi", path = "stm32f427zi.rs")] +#[cfg_attr(feature = "stm32f429ag", path = "stm32f429ag.rs")] +#[cfg_attr(feature = "stm32f429ai", path = "stm32f429ai.rs")] +#[cfg_attr(feature = "stm32f429be", path = "stm32f429be.rs")] +#[cfg_attr(feature = "stm32f429bg", path = "stm32f429bg.rs")] +#[cfg_attr(feature = "stm32f429bi", path = "stm32f429bi.rs")] +#[cfg_attr(feature = "stm32f429ie", path = "stm32f429ie.rs")] +#[cfg_attr(feature = "stm32f429ig", path = "stm32f429ig.rs")] +#[cfg_attr(feature = "stm32f429ii", path = "stm32f429ii.rs")] +#[cfg_attr(feature = "stm32f429ne", path = "stm32f429ne.rs")] +#[cfg_attr(feature = "stm32f429ng", path = "stm32f429ng.rs")] +#[cfg_attr(feature = "stm32f429ni", path = "stm32f429ni.rs")] +#[cfg_attr(feature = "stm32f429ve", path = "stm32f429ve.rs")] +#[cfg_attr(feature = "stm32f429vg", path = "stm32f429vg.rs")] +#[cfg_attr(feature = "stm32f429vi", path = "stm32f429vi.rs")] +#[cfg_attr(feature = "stm32f429ze", path = "stm32f429ze.rs")] +#[cfg_attr(feature = "stm32f429zg", path = "stm32f429zg.rs")] +#[cfg_attr(feature = "stm32f429zi", path = "stm32f429zi.rs")] +#[cfg_attr(feature = "stm32f437ai", path = "stm32f437ai.rs")] +#[cfg_attr(feature = "stm32f437ig", path = "stm32f437ig.rs")] +#[cfg_attr(feature = "stm32f437ii", path = "stm32f437ii.rs")] +#[cfg_attr(feature = "stm32f437vg", path = "stm32f437vg.rs")] +#[cfg_attr(feature = "stm32f437vi", path = "stm32f437vi.rs")] +#[cfg_attr(feature = "stm32f437zg", path = "stm32f437zg.rs")] +#[cfg_attr(feature = "stm32f437zi", path = "stm32f437zi.rs")] +#[cfg_attr(feature = "stm32f439ai", path = "stm32f439ai.rs")] +#[cfg_attr(feature = "stm32f439bg", path = "stm32f439bg.rs")] +#[cfg_attr(feature = "stm32f439bi", path = "stm32f439bi.rs")] +#[cfg_attr(feature = "stm32f439ig", path = "stm32f439ig.rs")] +#[cfg_attr(feature = "stm32f439ii", path = "stm32f439ii.rs")] +#[cfg_attr(feature = "stm32f439ng", path = "stm32f439ng.rs")] +#[cfg_attr(feature = "stm32f439ni", path = "stm32f439ni.rs")] +#[cfg_attr(feature = "stm32f439vg", path = "stm32f439vg.rs")] +#[cfg_attr(feature = "stm32f439vi", path = "stm32f439vi.rs")] +#[cfg_attr(feature = "stm32f439zg", path = "stm32f439zg.rs")] +#[cfg_attr(feature = "stm32f439zi", path = "stm32f439zi.rs")] +#[cfg_attr(feature = "stm32f446mc", path = "stm32f446mc.rs")] +#[cfg_attr(feature = "stm32f446me", path = "stm32f446me.rs")] +#[cfg_attr(feature = "stm32f446rc", path = "stm32f446rc.rs")] +#[cfg_attr(feature = "stm32f446re", path = "stm32f446re.rs")] +#[cfg_attr(feature = "stm32f446vc", path = "stm32f446vc.rs")] +#[cfg_attr(feature = "stm32f446ve", path = "stm32f446ve.rs")] +#[cfg_attr(feature = "stm32f446zc", path = "stm32f446zc.rs")] +#[cfg_attr(feature = "stm32f446ze", path = "stm32f446ze.rs")] +#[cfg_attr(feature = "stm32f469ae", path = "stm32f469ae.rs")] +#[cfg_attr(feature = "stm32f469ag", path = "stm32f469ag.rs")] +#[cfg_attr(feature = "stm32f469ai", path = "stm32f469ai.rs")] +#[cfg_attr(feature = "stm32f469be", path = "stm32f469be.rs")] +#[cfg_attr(feature = "stm32f469bg", path = "stm32f469bg.rs")] +#[cfg_attr(feature = "stm32f469bi", path = "stm32f469bi.rs")] +#[cfg_attr(feature = "stm32f469ie", path = "stm32f469ie.rs")] +#[cfg_attr(feature = "stm32f469ig", path = "stm32f469ig.rs")] +#[cfg_attr(feature = "stm32f469ii", path = "stm32f469ii.rs")] +#[cfg_attr(feature = "stm32f469ne", path = "stm32f469ne.rs")] +#[cfg_attr(feature = "stm32f469ng", path = "stm32f469ng.rs")] +#[cfg_attr(feature = "stm32f469ni", path = "stm32f469ni.rs")] +#[cfg_attr(feature = "stm32f469ve", path = "stm32f469ve.rs")] +#[cfg_attr(feature = "stm32f469vg", path = "stm32f469vg.rs")] +#[cfg_attr(feature = "stm32f469vi", path = "stm32f469vi.rs")] +#[cfg_attr(feature = "stm32f469ze", path = "stm32f469ze.rs")] +#[cfg_attr(feature = "stm32f469zg", path = "stm32f469zg.rs")] +#[cfg_attr(feature = "stm32f469zi", path = "stm32f469zi.rs")] +#[cfg_attr(feature = "stm32f479ag", path = "stm32f479ag.rs")] +#[cfg_attr(feature = "stm32f479ai", path = "stm32f479ai.rs")] +#[cfg_attr(feature = "stm32f479bg", path = "stm32f479bg.rs")] +#[cfg_attr(feature = "stm32f479bi", path = "stm32f479bi.rs")] +#[cfg_attr(feature = "stm32f479ig", path = "stm32f479ig.rs")] +#[cfg_attr(feature = "stm32f479ii", path = "stm32f479ii.rs")] +#[cfg_attr(feature = "stm32f479ng", path = "stm32f479ng.rs")] +#[cfg_attr(feature = "stm32f479ni", path = "stm32f479ni.rs")] +#[cfg_attr(feature = "stm32f479vg", path = "stm32f479vg.rs")] +#[cfg_attr(feature = "stm32f479vi", path = "stm32f479vi.rs")] +#[cfg_attr(feature = "stm32f479zg", path = "stm32f479zg.rs")] +#[cfg_attr(feature = "stm32f479zi", path = "stm32f479zi.rs")] +#[cfg_attr(feature = "stm32h723ve", path = "stm32h723ve.rs")] +#[cfg_attr(feature = "stm32h723vg", path = "stm32h723vg.rs")] +#[cfg_attr(feature = "stm32h723ze", path = "stm32h723ze.rs")] +#[cfg_attr(feature = "stm32h723zg", path = "stm32h723zg.rs")] +#[cfg_attr(feature = "stm32h725ae", path = "stm32h725ae.rs")] +#[cfg_attr(feature = "stm32h725ag", path = "stm32h725ag.rs")] +#[cfg_attr(feature = "stm32h725ie", path = "stm32h725ie.rs")] +#[cfg_attr(feature = "stm32h725ig", path = "stm32h725ig.rs")] +#[cfg_attr(feature = "stm32h725re", path = "stm32h725re.rs")] +#[cfg_attr(feature = "stm32h725rg", path = "stm32h725rg.rs")] +#[cfg_attr(feature = "stm32h725ve", path = "stm32h725ve.rs")] +#[cfg_attr(feature = "stm32h725vg", path = "stm32h725vg.rs")] +#[cfg_attr(feature = "stm32h725ze", path = "stm32h725ze.rs")] +#[cfg_attr(feature = "stm32h725zg", path = "stm32h725zg.rs")] +#[cfg_attr(feature = "stm32h730ab", path = "stm32h730ab.rs")] +#[cfg_attr(feature = "stm32h730ib", path = "stm32h730ib.rs")] +#[cfg_attr(feature = "stm32h730vb", path = "stm32h730vb.rs")] +#[cfg_attr(feature = "stm32h730zb", path = "stm32h730zb.rs")] +#[cfg_attr(feature = "stm32h733vg", path = "stm32h733vg.rs")] +#[cfg_attr(feature = "stm32h733zg", path = "stm32h733zg.rs")] +#[cfg_attr(feature = "stm32h735ag", path = "stm32h735ag.rs")] +#[cfg_attr(feature = "stm32h735ig", path = "stm32h735ig.rs")] +#[cfg_attr(feature = "stm32h735rg", path = "stm32h735rg.rs")] +#[cfg_attr(feature = "stm32h735vg", path = "stm32h735vg.rs")] +#[cfg_attr(feature = "stm32h735zg", path = "stm32h735zg.rs")] +#[cfg_attr(feature = "stm32h742ag", path = "stm32h742ag.rs")] +#[cfg_attr(feature = "stm32h742ai", path = "stm32h742ai.rs")] +#[cfg_attr(feature = "stm32h742bg", path = "stm32h742bg.rs")] +#[cfg_attr(feature = "stm32h742bi", path = "stm32h742bi.rs")] +#[cfg_attr(feature = "stm32h742ig", path = "stm32h742ig.rs")] +#[cfg_attr(feature = "stm32h742ii", path = "stm32h742ii.rs")] +#[cfg_attr(feature = "stm32h742vg", path = "stm32h742vg.rs")] +#[cfg_attr(feature = "stm32h742vi", path = "stm32h742vi.rs")] +#[cfg_attr(feature = "stm32h742xg", path = "stm32h742xg.rs")] +#[cfg_attr(feature = "stm32h742xi", path = "stm32h742xi.rs")] +#[cfg_attr(feature = "stm32h742zg", path = "stm32h742zg.rs")] +#[cfg_attr(feature = "stm32h742zi", path = "stm32h742zi.rs")] +#[cfg_attr(feature = "stm32h743ag", path = "stm32h743ag.rs")] +#[cfg_attr(feature = "stm32h743ai", path = "stm32h743ai.rs")] +#[cfg_attr(feature = "stm32h743bg", path = "stm32h743bg.rs")] +#[cfg_attr(feature = "stm32h743bi", path = "stm32h743bi.rs")] +#[cfg_attr(feature = "stm32h743ig", path = "stm32h743ig.rs")] +#[cfg_attr(feature = "stm32h743ii", path = "stm32h743ii.rs")] +#[cfg_attr(feature = "stm32h743vg", path = "stm32h743vg.rs")] +#[cfg_attr(feature = "stm32h743vi", path = "stm32h743vi.rs")] +#[cfg_attr(feature = "stm32h743xg", path = "stm32h743xg.rs")] +#[cfg_attr(feature = "stm32h743xi", path = "stm32h743xi.rs")] +#[cfg_attr(feature = "stm32h743zg", path = "stm32h743zg.rs")] +#[cfg_attr(feature = "stm32h743zi", path = "stm32h743zi.rs")] +#[cfg_attr(feature = "stm32h745bg", path = "stm32h745bg.rs")] +#[cfg_attr(feature = "stm32h745bi", path = "stm32h745bi.rs")] +#[cfg_attr(feature = "stm32h745ig", path = "stm32h745ig.rs")] +#[cfg_attr(feature = "stm32h745ii", path = "stm32h745ii.rs")] +#[cfg_attr(feature = "stm32h745xg", path = "stm32h745xg.rs")] +#[cfg_attr(feature = "stm32h745xi", path = "stm32h745xi.rs")] +#[cfg_attr(feature = "stm32h745zg", path = "stm32h745zg.rs")] +#[cfg_attr(feature = "stm32h745zi", path = "stm32h745zi.rs")] +#[cfg_attr(feature = "stm32h747ag", path = "stm32h747ag.rs")] +#[cfg_attr(feature = "stm32h747ai", path = "stm32h747ai.rs")] +#[cfg_attr(feature = "stm32h747bg", path = "stm32h747bg.rs")] +#[cfg_attr(feature = "stm32h747bi", path = "stm32h747bi.rs")] +#[cfg_attr(feature = "stm32h747ig", path = "stm32h747ig.rs")] +#[cfg_attr(feature = "stm32h747ii", path = "stm32h747ii.rs")] +#[cfg_attr(feature = "stm32h747xg", path = "stm32h747xg.rs")] +#[cfg_attr(feature = "stm32h747xi", path = "stm32h747xi.rs")] +#[cfg_attr(feature = "stm32h747zi", path = "stm32h747zi.rs")] +#[cfg_attr(feature = "stm32h750ib", path = "stm32h750ib.rs")] +#[cfg_attr(feature = "stm32h750vb", path = "stm32h750vb.rs")] +#[cfg_attr(feature = "stm32h750xb", path = "stm32h750xb.rs")] +#[cfg_attr(feature = "stm32h750zb", path = "stm32h750zb.rs")] +#[cfg_attr(feature = "stm32h753ai", path = "stm32h753ai.rs")] +#[cfg_attr(feature = "stm32h753bi", path = "stm32h753bi.rs")] +#[cfg_attr(feature = "stm32h753ii", path = "stm32h753ii.rs")] +#[cfg_attr(feature = "stm32h753vi", path = "stm32h753vi.rs")] +#[cfg_attr(feature = "stm32h753xi", path = "stm32h753xi.rs")] +#[cfg_attr(feature = "stm32h753zi", path = "stm32h753zi.rs")] +#[cfg_attr(feature = "stm32h755bi", path = "stm32h755bi.rs")] +#[cfg_attr(feature = "stm32h755ii", path = "stm32h755ii.rs")] +#[cfg_attr(feature = "stm32h755xi", path = "stm32h755xi.rs")] +#[cfg_attr(feature = "stm32h755zi", path = "stm32h755zi.rs")] +#[cfg_attr(feature = "stm32h757ai", path = "stm32h757ai.rs")] +#[cfg_attr(feature = "stm32h757bi", path = "stm32h757bi.rs")] +#[cfg_attr(feature = "stm32h757ii", path = "stm32h757ii.rs")] +#[cfg_attr(feature = "stm32h757xi", path = "stm32h757xi.rs")] +#[cfg_attr(feature = "stm32h757zi", path = "stm32h757zi.rs")] +#[cfg_attr(feature = "stm32h7a3ag", path = "stm32h7a3ag.rs")] +#[cfg_attr(feature = "stm32h7a3ai", path = "stm32h7a3ai.rs")] +#[cfg_attr(feature = "stm32h7a3ig", path = "stm32h7a3ig.rs")] +#[cfg_attr(feature = "stm32h7a3ii", path = "stm32h7a3ii.rs")] +#[cfg_attr(feature = "stm32h7a3lg", path = "stm32h7a3lg.rs")] +#[cfg_attr(feature = "stm32h7a3li", path = "stm32h7a3li.rs")] +#[cfg_attr(feature = "stm32h7a3ng", path = "stm32h7a3ng.rs")] +#[cfg_attr(feature = "stm32h7a3ni", path = "stm32h7a3ni.rs")] +#[cfg_attr(feature = "stm32h7a3qi", path = "stm32h7a3qi.rs")] +#[cfg_attr(feature = "stm32h7a3rg", path = "stm32h7a3rg.rs")] +#[cfg_attr(feature = "stm32h7a3ri", path = "stm32h7a3ri.rs")] +#[cfg_attr(feature = "stm32h7a3vg", path = "stm32h7a3vg.rs")] +#[cfg_attr(feature = "stm32h7a3vi", path = "stm32h7a3vi.rs")] +#[cfg_attr(feature = "stm32h7a3zg", path = "stm32h7a3zg.rs")] +#[cfg_attr(feature = "stm32h7a3zi", path = "stm32h7a3zi.rs")] +#[cfg_attr(feature = "stm32h7b0ab", path = "stm32h7b0ab.rs")] +#[cfg_attr(feature = "stm32h7b0ib", path = "stm32h7b0ib.rs")] +#[cfg_attr(feature = "stm32h7b0rb", path = "stm32h7b0rb.rs")] +#[cfg_attr(feature = "stm32h7b0vb", path = "stm32h7b0vb.rs")] +#[cfg_attr(feature = "stm32h7b0zb", path = "stm32h7b0zb.rs")] +#[cfg_attr(feature = "stm32h7b3ai", path = "stm32h7b3ai.rs")] +#[cfg_attr(feature = "stm32h7b3ii", path = "stm32h7b3ii.rs")] +#[cfg_attr(feature = "stm32h7b3li", path = "stm32h7b3li.rs")] +#[cfg_attr(feature = "stm32h7b3ni", path = "stm32h7b3ni.rs")] +#[cfg_attr(feature = "stm32h7b3qi", path = "stm32h7b3qi.rs")] +#[cfg_attr(feature = "stm32h7b3ri", path = "stm32h7b3ri.rs")] +#[cfg_attr(feature = "stm32h7b3vi", path = "stm32h7b3vi.rs")] +#[cfg_attr(feature = "stm32h7b3zi", path = "stm32h7b3zi.rs")] +#[cfg_attr(feature = "stm32l412c8", path = "stm32l412c8.rs")] +#[cfg_attr(feature = "stm32l412cb", path = "stm32l412cb.rs")] +#[cfg_attr(feature = "stm32l412k8", path = "stm32l412k8.rs")] +#[cfg_attr(feature = "stm32l412kb", path = "stm32l412kb.rs")] +#[cfg_attr(feature = "stm32l412r8", path = "stm32l412r8.rs")] +#[cfg_attr(feature = "stm32l412rb", path = "stm32l412rb.rs")] +#[cfg_attr(feature = "stm32l412t8", path = "stm32l412t8.rs")] +#[cfg_attr(feature = "stm32l412tb", path = "stm32l412tb.rs")] +#[cfg_attr(feature = "stm32l422cb", path = "stm32l422cb.rs")] +#[cfg_attr(feature = "stm32l422kb", path = "stm32l422kb.rs")] +#[cfg_attr(feature = "stm32l422rb", path = "stm32l422rb.rs")] +#[cfg_attr(feature = "stm32l422tb", path = "stm32l422tb.rs")] +#[cfg_attr(feature = "stm32l431cb", path = "stm32l431cb.rs")] +#[cfg_attr(feature = "stm32l431cc", path = "stm32l431cc.rs")] +#[cfg_attr(feature = "stm32l431kb", path = "stm32l431kb.rs")] +#[cfg_attr(feature = "stm32l431kc", path = "stm32l431kc.rs")] +#[cfg_attr(feature = "stm32l431rb", path = "stm32l431rb.rs")] +#[cfg_attr(feature = "stm32l431rc", path = "stm32l431rc.rs")] +#[cfg_attr(feature = "stm32l431vc", path = "stm32l431vc.rs")] +#[cfg_attr(feature = "stm32l432kb", path = "stm32l432kb.rs")] +#[cfg_attr(feature = "stm32l432kc", path = "stm32l432kc.rs")] +#[cfg_attr(feature = "stm32l433cb", path = "stm32l433cb.rs")] +#[cfg_attr(feature = "stm32l433cc", path = "stm32l433cc.rs")] +#[cfg_attr(feature = "stm32l433rb", path = "stm32l433rb.rs")] +#[cfg_attr(feature = "stm32l433rc", path = "stm32l433rc.rs")] +#[cfg_attr(feature = "stm32l433vc", path = "stm32l433vc.rs")] +#[cfg_attr(feature = "stm32l442kc", path = "stm32l442kc.rs")] +#[cfg_attr(feature = "stm32l443cc", path = "stm32l443cc.rs")] +#[cfg_attr(feature = "stm32l443rc", path = "stm32l443rc.rs")] +#[cfg_attr(feature = "stm32l443vc", path = "stm32l443vc.rs")] +#[cfg_attr(feature = "stm32l451cc", path = "stm32l451cc.rs")] +#[cfg_attr(feature = "stm32l451ce", path = "stm32l451ce.rs")] +#[cfg_attr(feature = "stm32l451rc", path = "stm32l451rc.rs")] +#[cfg_attr(feature = "stm32l451re", path = "stm32l451re.rs")] +#[cfg_attr(feature = "stm32l451vc", path = "stm32l451vc.rs")] +#[cfg_attr(feature = "stm32l451ve", path = "stm32l451ve.rs")] +#[cfg_attr(feature = "stm32l452cc", path = "stm32l452cc.rs")] +#[cfg_attr(feature = "stm32l452ce", path = "stm32l452ce.rs")] +#[cfg_attr(feature = "stm32l452rc", path = "stm32l452rc.rs")] +#[cfg_attr(feature = "stm32l452re", path = "stm32l452re.rs")] +#[cfg_attr(feature = "stm32l452vc", path = "stm32l452vc.rs")] +#[cfg_attr(feature = "stm32l452ve", path = "stm32l452ve.rs")] +#[cfg_attr(feature = "stm32l462ce", path = "stm32l462ce.rs")] +#[cfg_attr(feature = "stm32l462re", path = "stm32l462re.rs")] +#[cfg_attr(feature = "stm32l462ve", path = "stm32l462ve.rs")] +#[cfg_attr(feature = "stm32l471qe", path = "stm32l471qe.rs")] +#[cfg_attr(feature = "stm32l471qg", path = "stm32l471qg.rs")] +#[cfg_attr(feature = "stm32l471re", path = "stm32l471re.rs")] +#[cfg_attr(feature = "stm32l471rg", path = "stm32l471rg.rs")] +#[cfg_attr(feature = "stm32l471ve", path = "stm32l471ve.rs")] +#[cfg_attr(feature = "stm32l471vg", path = "stm32l471vg.rs")] +#[cfg_attr(feature = "stm32l471ze", path = "stm32l471ze.rs")] +#[cfg_attr(feature = "stm32l471zg", path = "stm32l471zg.rs")] +#[cfg_attr(feature = "stm32l475rc", path = "stm32l475rc.rs")] +#[cfg_attr(feature = "stm32l475re", path = "stm32l475re.rs")] +#[cfg_attr(feature = "stm32l475rg", path = "stm32l475rg.rs")] +#[cfg_attr(feature = "stm32l475vc", path = "stm32l475vc.rs")] +#[cfg_attr(feature = "stm32l475ve", path = "stm32l475ve.rs")] +#[cfg_attr(feature = "stm32l475vg", path = "stm32l475vg.rs")] +#[cfg_attr(feature = "stm32l476je", path = "stm32l476je.rs")] +#[cfg_attr(feature = "stm32l476jg", path = "stm32l476jg.rs")] +#[cfg_attr(feature = "stm32l476me", path = "stm32l476me.rs")] +#[cfg_attr(feature = "stm32l476mg", path = "stm32l476mg.rs")] +#[cfg_attr(feature = "stm32l476qe", path = "stm32l476qe.rs")] +#[cfg_attr(feature = "stm32l476qg", path = "stm32l476qg.rs")] +#[cfg_attr(feature = "stm32l476rc", path = "stm32l476rc.rs")] +#[cfg_attr(feature = "stm32l476re", path = "stm32l476re.rs")] +#[cfg_attr(feature = "stm32l476rg", path = "stm32l476rg.rs")] +#[cfg_attr(feature = "stm32l476vc", path = "stm32l476vc.rs")] +#[cfg_attr(feature = "stm32l476ve", path = "stm32l476ve.rs")] +#[cfg_attr(feature = "stm32l476vg", path = "stm32l476vg.rs")] +#[cfg_attr(feature = "stm32l476ze", path = "stm32l476ze.rs")] +#[cfg_attr(feature = "stm32l476zg", path = "stm32l476zg.rs")] +#[cfg_attr(feature = "stm32l485jc", path = "stm32l485jc.rs")] +#[cfg_attr(feature = "stm32l485je", path = "stm32l485je.rs")] +#[cfg_attr(feature = "stm32l486jg", path = "stm32l486jg.rs")] +#[cfg_attr(feature = "stm32l486qg", path = "stm32l486qg.rs")] +#[cfg_attr(feature = "stm32l486rg", path = "stm32l486rg.rs")] +#[cfg_attr(feature = "stm32l486vg", path = "stm32l486vg.rs")] +#[cfg_attr(feature = "stm32l486zg", path = "stm32l486zg.rs")] +#[cfg_attr(feature = "stm32l496ae", path = "stm32l496ae.rs")] +#[cfg_attr(feature = "stm32l496ag", path = "stm32l496ag.rs")] +#[cfg_attr(feature = "stm32l496qe", path = "stm32l496qe.rs")] +#[cfg_attr(feature = "stm32l496qg", path = "stm32l496qg.rs")] +#[cfg_attr(feature = "stm32l496re", path = "stm32l496re.rs")] +#[cfg_attr(feature = "stm32l496rg", path = "stm32l496rg.rs")] +#[cfg_attr(feature = "stm32l496ve", path = "stm32l496ve.rs")] +#[cfg_attr(feature = "stm32l496vg", path = "stm32l496vg.rs")] +#[cfg_attr(feature = "stm32l496wg", path = "stm32l496wg.rs")] +#[cfg_attr(feature = "stm32l496ze", path = "stm32l496ze.rs")] +#[cfg_attr(feature = "stm32l496zg", path = "stm32l496zg.rs")] +#[cfg_attr(feature = "stm32l4a6ag", path = "stm32l4a6ag.rs")] +#[cfg_attr(feature = "stm32l4a6qg", path = "stm32l4a6qg.rs")] +#[cfg_attr(feature = "stm32l4a6rg", path = "stm32l4a6rg.rs")] +#[cfg_attr(feature = "stm32l4a6vg", path = "stm32l4a6vg.rs")] +#[cfg_attr(feature = "stm32l4a6zg", path = "stm32l4a6zg.rs")] +#[cfg_attr(feature = "stm32l4p5ae", path = "stm32l4p5ae.rs")] +#[cfg_attr(feature = "stm32l4p5ag", path = "stm32l4p5ag.rs")] +#[cfg_attr(feature = "stm32l4p5ce", path = "stm32l4p5ce.rs")] +#[cfg_attr(feature = "stm32l4p5cg", path = "stm32l4p5cg.rs")] +#[cfg_attr(feature = "stm32l4p5qe", path = "stm32l4p5qe.rs")] +#[cfg_attr(feature = "stm32l4p5qg", path = "stm32l4p5qg.rs")] +#[cfg_attr(feature = "stm32l4p5re", path = "stm32l4p5re.rs")] +#[cfg_attr(feature = "stm32l4p5rg", path = "stm32l4p5rg.rs")] +#[cfg_attr(feature = "stm32l4p5ve", path = "stm32l4p5ve.rs")] +#[cfg_attr(feature = "stm32l4p5vg", path = "stm32l4p5vg.rs")] +#[cfg_attr(feature = "stm32l4p5ze", path = "stm32l4p5ze.rs")] +#[cfg_attr(feature = "stm32l4p5zg", path = "stm32l4p5zg.rs")] +#[cfg_attr(feature = "stm32l4q5ag", path = "stm32l4q5ag.rs")] +#[cfg_attr(feature = "stm32l4q5cg", path = "stm32l4q5cg.rs")] +#[cfg_attr(feature = "stm32l4q5qg", path = "stm32l4q5qg.rs")] +#[cfg_attr(feature = "stm32l4q5rg", path = "stm32l4q5rg.rs")] +#[cfg_attr(feature = "stm32l4q5vg", path = "stm32l4q5vg.rs")] +#[cfg_attr(feature = "stm32l4q5zg", path = "stm32l4q5zg.rs")] +#[cfg_attr(feature = "stm32l4r5ag", path = "stm32l4r5ag.rs")] +#[cfg_attr(feature = "stm32l4r5ai", path = "stm32l4r5ai.rs")] +#[cfg_attr(feature = "stm32l4r5qg", path = "stm32l4r5qg.rs")] +#[cfg_attr(feature = "stm32l4r5qi", path = "stm32l4r5qi.rs")] +#[cfg_attr(feature = "stm32l4r5vg", path = "stm32l4r5vg.rs")] +#[cfg_attr(feature = "stm32l4r5vi", path = "stm32l4r5vi.rs")] +#[cfg_attr(feature = "stm32l4r5zg", path = "stm32l4r5zg.rs")] +#[cfg_attr(feature = "stm32l4r5zi", path = "stm32l4r5zi.rs")] +#[cfg_attr(feature = "stm32l4r7ai", path = "stm32l4r7ai.rs")] +#[cfg_attr(feature = "stm32l4r7vi", path = "stm32l4r7vi.rs")] +#[cfg_attr(feature = "stm32l4r7zi", path = "stm32l4r7zi.rs")] +#[cfg_attr(feature = "stm32l4r9ag", path = "stm32l4r9ag.rs")] +#[cfg_attr(feature = "stm32l4r9ai", path = "stm32l4r9ai.rs")] +#[cfg_attr(feature = "stm32l4r9vg", path = "stm32l4r9vg.rs")] +#[cfg_attr(feature = "stm32l4r9vi", path = "stm32l4r9vi.rs")] +#[cfg_attr(feature = "stm32l4r9zg", path = "stm32l4r9zg.rs")] +#[cfg_attr(feature = "stm32l4r9zi", path = "stm32l4r9zi.rs")] +#[cfg_attr(feature = "stm32l4s5ai", path = "stm32l4s5ai.rs")] +#[cfg_attr(feature = "stm32l4s5qi", path = "stm32l4s5qi.rs")] +#[cfg_attr(feature = "stm32l4s5vi", path = "stm32l4s5vi.rs")] +#[cfg_attr(feature = "stm32l4s5zi", path = "stm32l4s5zi.rs")] +#[cfg_attr(feature = "stm32l4s7ai", path = "stm32l4s7ai.rs")] +#[cfg_attr(feature = "stm32l4s7vi", path = "stm32l4s7vi.rs")] +#[cfg_attr(feature = "stm32l4s7zi", path = "stm32l4s7zi.rs")] +#[cfg_attr(feature = "stm32l4s9ai", path = "stm32l4s9ai.rs")] +#[cfg_attr(feature = "stm32l4s9vi", path = "stm32l4s9vi.rs")] +#[cfg_attr(feature = "stm32l4s9zi", path = "stm32l4s9zi.rs")] +mod chip; +pub use chip::*; diff --git a/embassy-stm32/src/pac/regs.rs b/embassy-stm32/src/pac/regs.rs new file mode 100644 index 00000000..42af348d --- /dev/null +++ b/embassy-stm32/src/pac/regs.rs @@ -0,0 +1,10275 @@ +#![no_std] +#![doc = "Peripheral access API (generated using svd2rust v0.17.0 (22741fa 2021-04-20))"] +pub mod syscfg_h7 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "peripheral mode configuration register"] + pub fn pmcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "compensation cell control/status register"] + pub fn cccsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SYSCFG compensation cell value register"] + pub fn ccvr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "SYSCFG compensation cell code register"] + pub fn cccr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "SYSCFG power control register"] + pub fn pwrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "SYSCFG package register"] + pub fn pkgr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(292usize)) } + } + #[doc = "SYSCFG user register 0"] + pub fn ur0(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(768usize)) } + } + #[doc = "SYSCFG user register 2"] + pub fn ur2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(776usize)) } + } + #[doc = "SYSCFG user register 3"] + pub fn ur3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(780usize)) } + } + #[doc = "SYSCFG user register 4"] + pub fn ur4(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(784usize)) } + } + #[doc = "SYSCFG user register 5"] + pub fn ur5(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(788usize)) } + } + #[doc = "SYSCFG user register 6"] + pub fn ur6(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(792usize)) } + } + #[doc = "SYSCFG user register 7"] + pub fn ur7(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(796usize)) } + } + #[doc = "SYSCFG user register 8"] + pub fn ur8(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(800usize)) } + } + #[doc = "SYSCFG user register 9"] + pub fn ur9(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(804usize)) } + } + #[doc = "SYSCFG user register 10"] + pub fn ur10(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(808usize)) } + } + #[doc = "SYSCFG user register 11"] + pub fn ur11(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(812usize)) } + } + #[doc = "SYSCFG user register 12"] + pub fn ur12(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(816usize)) } + } + #[doc = "SYSCFG user register 13"] + pub fn ur13(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(820usize)) } + } + #[doc = "SYSCFG user register 14"] + pub fn ur14(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(824usize)) } + } + #[doc = "SYSCFG user register 15"] + pub fn ur15(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(828usize)) } + } + #[doc = "SYSCFG user register 16"] + pub fn ur16(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(832usize)) } + } + #[doc = "SYSCFG user register 17"] + pub fn ur17(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(836usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "SYSCFG user register 12"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur12(pub u32); + impl Ur12 { + #[doc = "Secure mode"] + pub const fn secure(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Secure mode"] + pub fn set_secure(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur12 { + fn default() -> Ur12 { + Ur12(0) + } + } + #[doc = "SYSCFG user register 6"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur6(pub u32); + impl Ur6 { + #[doc = "Protected area start address for bank 1"] + pub const fn pa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 1"] + pub fn set_pa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Protected area end address for bank 1"] + pub const fn pa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 1"] + pub fn set_pa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur6 { + fn default() -> Ur6 { + Ur6(0) + } + } + #[doc = "SYSCFG user register 16"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur16(pub u32); + impl Ur16 { + #[doc = "Freeze independent watchdog in Stop mode"] + pub const fn fziwdgstp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Stop mode"] + pub fn set_fziwdgstp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Private key programmed"] + pub const fn pkp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Private key programmed"] + pub fn set_pkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur16 { + fn default() -> Ur16 { + Ur16(0) + } + } + #[doc = "SYSCFG user register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur3(pub u32); + impl Ur3 { + #[doc = "Boot Address 1"] + pub const fn boot_add1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 1"] + pub fn set_boot_add1(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur3 { + fn default() -> Ur3 { + Ur3(0) + } + } + #[doc = "SYSCFG user register 8"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur8(pub u32); + impl Ur8 { + #[doc = "Mass erase protected area disabled for bank 2"] + pub const fn mepad_2(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase protected area disabled for bank 2"] + pub fn set_mepad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub const fn mesad_2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 2"] + pub fn set_mesad_2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur8 { + fn default() -> Ur8 { + Ur8(0) + } + } + #[doc = "SYSCFG compensation cell value register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccvr(pub u32); + impl Ccvr { + #[doc = "NMOS compensation value"] + pub const fn ncv(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation value"] + pub fn set_ncv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation value"] + pub const fn pcv(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation value"] + pub fn set_pcv(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ccvr { + fn default() -> Ccvr { + Ccvr(0) + } + } + #[doc = "SYSCFG user register 11"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur11(pub u32); + impl Ur11 { + #[doc = "Secured area end address for bank 2"] + pub const fn sa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 2"] + pub fn set_sa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Independent Watchdog 1 mode"] + pub const fn iwdg1m(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Independent Watchdog 1 mode"] + pub fn set_iwdg1m(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur11 { + fn default() -> Ur11 { + Ur11(0) + } + } + #[doc = "SYSCFG user register 9"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur9(pub u32); + impl Ur9 { + #[doc = "Write protection for flash bank 2"] + pub const fn wrpn_2(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 2"] + pub fn set_wrpn_2(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Protected area start address for bank 2"] + pub const fn pa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area start address for bank 2"] + pub fn set_pa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur9 { + fn default() -> Ur9 { + Ur9(0) + } + } + #[doc = "SYSCFG power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pwrcr(pub u32); + impl Pwrcr { + #[doc = "Overdrive enable"] + pub const fn oden(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Overdrive enable"] + pub fn set_oden(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pwrcr { + fn default() -> Pwrcr { + Pwrcr(0) + } + } + #[doc = "SYSCFG user register 15"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur15(pub u32); + impl Ur15 { + #[doc = "Freeze independent watchdog in Standby mode"] + pub const fn fziwdgstb(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Freeze independent watchdog in Standby mode"] + pub fn set_fziwdgstb(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur15 { + fn default() -> Ur15 { + Ur15(0) + } + } + #[doc = "SYSCFG compensation cell code register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccr(pub u32); + impl Cccr { + #[doc = "NMOS compensation code"] + pub const fn ncc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "NMOS compensation code"] + pub fn set_ncc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "PMOS compensation code"] + pub const fn pcc(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "PMOS compensation code"] + pub fn set_pcc(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Cccr { + fn default() -> Cccr { + Cccr(0) + } + } + #[doc = "SYSCFG user register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur2(pub u32); + impl Ur2 { + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub const fn borh(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "BOR_LVL Brownout Reset Threshold Level"] + pub fn set_borh(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Boot Address 0"] + pub const fn boot_add0(&self) -> u16 { + let val = (self.0 >> 16usize) & 0xffff; + val as u16 + } + #[doc = "Boot Address 0"] + pub fn set_boot_add0(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize); + } + } + impl Default for Ur2 { + fn default() -> Ur2 { + Ur2(0) + } + } + #[doc = "SYSCFG user register 14"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur14(pub u32); + impl Ur14 { + #[doc = "D1 Stop Reset"] + pub const fn d1stprst(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "D1 Stop Reset"] + pub fn set_d1stprst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur14 { + fn default() -> Ur14 { + Ur14(0) + } + } + #[doc = "SYSCFG user register 0"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur0(pub u32); + impl Ur0 { + #[doc = "Bank Swap"] + pub const fn bks(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Bank Swap"] + pub fn set_bks(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Readout protection"] + pub const fn rdp(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Readout protection"] + pub fn set_rdp(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur0 { + fn default() -> Ur0 { + Ur0(0) + } + } + #[doc = "external interrupt configuration register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration (x = 4 to 7)"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmcr(pub u32); + impl Pmcr { + #[doc = "I2C1 Fm+"] + pub const fn i2c1fmp(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fm+"] + pub fn set_i2c1fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I2C2 Fm+"] + pub const fn i2c2fmp(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fm+"] + pub fn set_i2c2fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "I2C3 Fm+"] + pub const fn i2c3fmp(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fm+"] + pub fn set_i2c3fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "I2C4 Fm+"] + pub const fn i2c4fmp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "I2C4 Fm+"] + pub fn set_i2c4fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "PB(6) Fm+"] + pub const fn pb6fmp(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "PB(6) Fm+"] + pub fn set_pb6fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "PB(7) Fast Mode Plus"] + pub const fn pb7fmp(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "PB(7) Fast Mode Plus"] + pub fn set_pb7fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "PB(8) Fast Mode Plus"] + pub const fn pb8fmp(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "PB(8) Fast Mode Plus"] + pub fn set_pb8fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "PB(9) Fm+"] + pub const fn pb9fmp(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "PB(9) Fm+"] + pub fn set_pb9fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Booster Enable"] + pub const fn booste(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Booster Enable"] + pub fn set_booste(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Analog switch supply voltage selection"] + pub const fn boostvddsel(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Analog switch supply voltage selection"] + pub fn set_boostvddsel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Ethernet PHY Interface Selection"] + pub const fn epis(&self) -> u8 { + let val = (self.0 >> 21usize) & 0x07; + val as u8 + } + #[doc = "Ethernet PHY Interface Selection"] + pub fn set_epis(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize); + } + #[doc = "PA0 Switch Open"] + pub const fn pa0so(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "PA0 Switch Open"] + pub fn set_pa0so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "PA1 Switch Open"] + pub const fn pa1so(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "PA1 Switch Open"] + pub fn set_pa1so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "PC2 Switch Open"] + pub const fn pc2so(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "PC2 Switch Open"] + pub fn set_pc2so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "PC3 Switch Open"] + pub const fn pc3so(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "PC3 Switch Open"] + pub fn set_pc3so(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + } + impl Default for Pmcr { + fn default() -> Pmcr { + Pmcr(0) + } + } + #[doc = "SYSCFG user register 5"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur5(pub u32); + impl Ur5 { + #[doc = "Mass erase secured area disabled for bank 1"] + pub const fn mesad_1(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Mass erase secured area disabled for bank 1"] + pub fn set_mesad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Write protection for flash bank 1"] + pub const fn wrpn_1(&self) -> u8 { + let val = (self.0 >> 16usize) & 0xff; + val as u8 + } + #[doc = "Write protection for flash bank 1"] + pub fn set_wrpn_1(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize); + } + } + impl Default for Ur5 { + fn default() -> Ur5 { + Ur5(0) + } + } + #[doc = "SYSCFG user register 7"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur7(pub u32); + impl Ur7 { + #[doc = "Secured area start address for bank 1"] + pub const fn sa_beg_1(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 1"] + pub fn set_sa_beg_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area end address for bank 1"] + pub const fn sa_end_1(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area end address for bank 1"] + pub fn set_sa_end_1(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur7 { + fn default() -> Ur7 { + Ur7(0) + } + } + #[doc = "SYSCFG user register 13"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur13(pub u32); + impl Ur13 { + #[doc = "Secured DTCM RAM Size"] + pub const fn sdrs(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "Secured DTCM RAM Size"] + pub fn set_sdrs(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "D1 Standby reset"] + pub const fn d1sbrst(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "D1 Standby reset"] + pub fn set_d1sbrst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur13 { + fn default() -> Ur13 { + Ur13(0) + } + } + #[doc = "SYSCFG user register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur4(pub u32); + impl Ur4 { + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub const fn mepad_1(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Mass Erase Protected Area Disabled for bank 1"] + pub fn set_mepad_1(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Ur4 { + fn default() -> Ur4 { + Ur4(0) + } + } + #[doc = "SYSCFG user register 10"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur10(pub u32); + impl Ur10 { + #[doc = "Protected area end address for bank 2"] + pub const fn pa_end_2(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x0fff; + val as u16 + } + #[doc = "Protected area end address for bank 2"] + pub fn set_pa_end_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize); + } + #[doc = "Secured area start address for bank 2"] + pub const fn sa_beg_2(&self) -> u16 { + let val = (self.0 >> 16usize) & 0x0fff; + val as u16 + } + #[doc = "Secured area start address for bank 2"] + pub fn set_sa_beg_2(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 16usize)) | (((val as u32) & 0x0fff) << 16usize); + } + } + impl Default for Ur10 { + fn default() -> Ur10 { + Ur10(0) + } + } + #[doc = "SYSCFG user register 17"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ur17(pub u32); + impl Ur17 { + #[doc = "I/O high speed / low voltage"] + pub const fn io_hslv(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "I/O high speed / low voltage"] + pub fn set_io_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for Ur17 { + fn default() -> Ur17 { + Ur17(0) + } + } + #[doc = "SYSCFG package register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pkgr(pub u32); + impl Pkgr { + #[doc = "Package"] + pub const fn pkg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Package"] + pub fn set_pkg(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + } + impl Default for Pkgr { + fn default() -> Pkgr { + Pkgr(0) + } + } + #[doc = "compensation cell control/status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cccsr(pub u32); + impl Cccsr { + #[doc = "enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Code selection"] + pub const fn cs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Code selection"] + pub fn set_cs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Compensation cell ready flag"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell ready flag"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "High-speed at low-voltage"] + pub const fn hslv(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "High-speed at low-voltage"] + pub fn set_hslv(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cccsr { + fn default() -> Cccsr { + Cccsr(0) + } + } + } +} +pub mod sdmmc_v2 { + use crate::generic::*; + #[doc = "SDMMC"] + #[derive(Copy, Clone)] + pub struct Sdmmc(pub *mut u8); + unsafe impl Send for Sdmmc {} + unsafe impl Sync for Sdmmc {} + impl Sdmmc { + #[doc = "SDMMC power control register"] + pub fn power(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + pub fn clkcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] + pub fn argr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + pub fn cmdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "SDMMC command response register"] + pub fn respcmdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + pub fn respr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(20usize + n * 4usize)) } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + pub fn dtimer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + pub fn dlenr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + pub fn dctrl(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + pub fn dcntr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] + pub fn star(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(52usize)) } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + pub fn icr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(56usize)) } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + pub fn maskr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(60usize)) } + } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + pub fn acktimer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(64usize)) } + } + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] + pub fn idmactrlr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(80usize)) } + } + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + pub fn idmabsizer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(84usize)) } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + pub fn idmabase0r(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(88usize)) } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + pub fn idmabase1r(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(92usize)) } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + pub fn fifor(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(128usize)) } + } + #[doc = "SDMMC IP version register"] + pub fn ver(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(1012usize)) } + } + #[doc = "SDMMC IP identification register"] + pub fn id(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(1016usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp4r(pub u32); + impl Resp4r { + #[doc = "see Table404."] + pub const fn cardstatus4(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus4(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp4r { + fn default() -> Resp4r { + Resp4r(0) + } + } + #[doc = "The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Star(pub u32); + impl Star { + #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ccrcfail(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ccrcfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dcrcfail(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dcrcfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] + pub const fn ctimeout(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods."] + pub fn set_ctimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dtimeout(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dtimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn txunderr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_txunderr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn rxoverr(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_rxoverr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn cmdrend(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_cmdrend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn cmdsent(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_cmdsent(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dataend(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dataend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dhold(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dhold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dbckend(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dbckend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn dabort(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_dabort(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub const fn dpsmact(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub fn set_dpsmact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub const fn cpsmact(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt."] + pub fn set_cpsmact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] + pub const fn txfifohe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full."] + pub fn set_txfifohe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] + pub const fn rxfifohf(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty."] + pub fn set_rxfifohf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] + pub const fn txfifof(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty."] + pub fn set_txfifof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] + pub const fn rxfifof(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO full This bit is cleared when one FIFO location becomes empty."] + pub fn set_rxfifof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] + pub const fn txfifoe(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Transmit FIFO empty This bit is cleared when one FIFO location becomes full."] + pub fn set_txfifoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] + pub const fn rxfifoe(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full."] + pub fn set_rxfifoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] + pub const fn busyd0(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt."] + pub fn set_busyd0(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn busyd0end(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_busyd0end(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn sdioit(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_sdioit(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ackfail(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ackfail(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn acktimeout(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_acktimeout(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn vswend(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_vswend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn ckstop(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_ckstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn idmate(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_idmate(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub const fn idmabtc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR."] + pub fn set_idmabtc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Star { + fn default() -> Star { + Star(0) + } + } + #[doc = "SDMMC power control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Power(pub u32); + impl Power { + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub const fn pwrctrl(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x03; + val as u8 + } + #[doc = "SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11."] + pub fn set_pwrctrl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize); + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub const fn vswitch(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:"] + pub fn set_vswitch(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub const fn vswitchen(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:"] + pub fn set_vswitchen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub const fn dirpol(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)."] + pub fn set_dirpol(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + } + impl Default for Power { + fn default() -> Power { + Power(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp1r(pub u32); + impl Resp1r { + #[doc = "see Table 432"] + pub const fn cardstatus1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table 432"] + pub fn set_cardstatus1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp1r { + fn default() -> Resp1r { + Resp1r(0) + } + } + #[doc = "The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase0r(pub u32); + impl Idmabase0r { + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub const fn idmabase0(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)."] + pub fn set_idmabase0(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase0r { + fn default() -> Idmabase0r { + Idmabase0r(0) + } + } + #[doc = "The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcntr(pub u32); + impl Dcntr { + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub const fn datacount(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect."] + pub fn set_datacount(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dcntr { + fn default() -> Dcntr { + Dcntr(0) + } + } + #[doc = "SDMMC command response register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Respcmdr(pub u32); + impl Respcmdr { + #[doc = "Response command index"] + pub const fn respcmd(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Response command index"] + pub fn set_respcmd(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + } + impl Default for Respcmdr { + fn default() -> Respcmdr { + Respcmdr(0) + } + } + #[doc = "The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabsizer(pub u32); + impl Idmabsizer { + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabndt(&self) -> u8 { + let val = (self.0 >> 5usize) & 0xff; + val as u8 + } + #[doc = "Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabndt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 5usize)) | (((val as u32) & 0xff) << 5usize); + } + } + impl Default for Idmabsizer { + fn default() -> Idmabsizer { + Idmabsizer(0) + } + } + #[doc = "The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Argr(pub u32); + impl Argr { + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub const fn cmdarg(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register."] + pub fn set_cmdarg(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Argr { + fn default() -> Argr { + Argr(0) + } + } + #[doc = "The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmdr(pub u32); + impl Cmdr { + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub const fn cmdindex(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x3f; + val as u8 + } + #[doc = "Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message."] + pub fn set_cmdindex(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 0usize)) | (((val as u32) & 0x3f) << 0usize); + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub const fn cmdtrans(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent."] + pub fn set_cmdtrans(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub const fn cmdstop(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent."] + pub fn set_cmdstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub const fn waitresp(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response."] + pub fn set_waitresp(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub const fn waitint(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode."] + pub fn set_waitint(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub const fn waitpend(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card."] + pub fn set_waitpend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub const fn cpsmen(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0."] + pub fn set_cpsmen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub const fn dthold(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state."] + pub fn set_dthold(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub const fn bootmode(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)"] + pub fn set_bootmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Enable boot mode procedure."] + pub const fn booten(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Enable boot mode procedure."] + pub fn set_booten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub const fn cmdsuspend(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1."] + pub fn set_cmdsuspend(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + } + impl Default for Cmdr { + fn default() -> Cmdr { + Cmdr(0) + } + } + #[doc = "The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmabase1r(pub u32); + impl Idmabase1r { + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub const fn idmabase1(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Buffer 1 memory base address, shall be word aligned (bit [1:0] +are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)."] + pub fn set_idmabase1(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Idmabase1r { + fn default() -> Idmabase1r { + Idmabase1r(0) + } + } + #[doc = "SDMMC IP identification register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Id(pub u32); + impl Id { + #[doc = "SDMMC IP identification."] + pub const fn ip_id(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "SDMMC IP identification."] + pub fn set_ip_id(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Id { + fn default() -> Id { + Id(0) + } + } + #[doc = "The SDMMC_DCTRL register control the data path state machine (DPSM)."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dctrl(pub u32); + impl Dctrl { + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub const fn dten(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards."] + pub fn set_dten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtdir(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtdir(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn dtmode(&self) -> u8 { + let val = (self.0 >> 2usize) & 0x03; + val as u8 + } + #[doc = "Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_dtmode(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 2usize)) | (((val as u32) & 0x03) << 2usize); + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub const fn dblocksize(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)"] + pub fn set_dblocksize(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub const fn rwstart(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Read wait start. If this bit is set, read wait operation starts."] + pub fn set_rwstart(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub const fn rwstop(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state."] + pub fn set_rwstop(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn rwmod(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_rwmod(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub const fn sdioen(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation."] + pub fn set_sdioen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn bootacken(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_bootacken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub const fn fiforst(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs."] + pub fn set_fiforst(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Dctrl { + fn default() -> Dctrl { + Dctrl(0) + } + } + #[doc = "The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dlenr(pub u32); + impl Dlenr { + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub const fn datalength(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0."] + pub fn set_datalength(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Dlenr { + fn default() -> Dlenr { + Dlenr(0) + } + } + #[doc = "The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Clkcr(pub u32); + impl Clkcr { + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub const fn clkdiv(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x03ff; + val as u16 + } + #[doc = "Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.."] + pub fn set_clkdiv(&mut self, val: u16) { + self.0 = (self.0 & !(0x03ff << 0usize)) | (((val as u32) & 0x03ff) << 0usize); + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub const fn pwrsav(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:"] + pub fn set_pwrsav(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn widbus(&self) -> u8 { + let val = (self.0 >> 14usize) & 0x03; + val as u8 + } + #[doc = "Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_widbus(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 14usize)) | (((val as u32) & 0x03) << 14usize); + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub const fn negedge(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division >1 (CLKDIV > 0) & DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge."] + pub fn set_negedge(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub const fn hwfc_en(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11."] + pub fn set_hwfc_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub const fn ddr(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS > 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division >1. (CLKDIV > 0)"] + pub fn set_ddr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn busspeed(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_busspeed(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub const fn selclkrx(&self) -> u8 { + let val = (self.0 >> 20usize) & 0x03; + val as u8 + } + #[doc = "Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)"] + pub fn set_selclkrx(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize); + } + } + impl Default for Clkcr { + fn default() -> Clkcr { + Clkcr(0) + } + } + #[doc = "SDMMC IP version register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ver(pub u32); + impl Ver { + #[doc = "IP minor revision number."] + pub const fn minrev(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "IP minor revision number."] + pub fn set_minrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "IP major revision number."] + pub const fn majrev(&self) -> u8 { + let val = (self.0 >> 4usize) & 0x0f; + val as u8 + } + #[doc = "IP major revision number."] + pub fn set_majrev(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 4usize)) | (((val as u32) & 0x0f) << 4usize); + } + } + impl Default for Ver { + fn default() -> Ver { + Ver(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp3r(pub u32); + impl Resp3r { + #[doc = "see Table404."] + pub const fn cardstatus3(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus3(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp3r { + fn default() -> Resp3r { + Resp3r(0) + } + } + #[doc = "The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Acktimer(pub u32); + impl Acktimer { + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub const fn acktime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x01ff_ffff; + val as u32 + } + #[doc = "Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods."] + pub fn set_acktime(&mut self, val: u32) { + self.0 = + (self.0 & !(0x01ff_ffff << 0usize)) | (((val as u32) & 0x01ff_ffff) << 0usize); + } + } + impl Default for Acktimer { + fn default() -> Acktimer { + Acktimer(0) + } + } + #[doc = "The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Maskr(pub u32); + impl Maskr { + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub const fn ccrcfailie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure."] + pub fn set_ccrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub const fn dcrcfailie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure."] + pub fn set_dcrcfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub const fn ctimeoutie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout."] + pub fn set_ctimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub const fn dtimeoutie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout."] + pub fn set_dtimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub const fn txunderrie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error."] + pub fn set_txunderrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub const fn rxoverrie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error."] + pub fn set_rxoverrie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub const fn cmdrendie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response."] + pub fn set_cmdrendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub const fn cmdsentie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command."] + pub fn set_cmdsentie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub const fn dataendie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end."] + pub fn set_dataendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub const fn dholdie(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state."] + pub fn set_dholdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub const fn dbckendie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end."] + pub fn set_dbckendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub const fn dabortie(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted."] + pub fn set_dabortie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub const fn txfifoheie(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty."] + pub fn set_txfifoheie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub const fn rxfifohfie(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full."] + pub fn set_rxfifohfie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub const fn rxfifofie(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full."] + pub fn set_rxfifofie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub const fn txfifoeie(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty."] + pub fn set_txfifoeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub const fn busyd0endie(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response."] + pub fn set_busyd0endie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub const fn sdioitie(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt."] + pub fn set_sdioitie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub const fn ackfailie(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail."] + pub fn set_ackfailie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub const fn acktimeoutie(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout."] + pub fn set_acktimeoutie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub const fn vswendie(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion."] + pub fn set_vswendie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub const fn ckstopie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped."] + pub fn set_ckstopie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub const fn idmabtcie(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer."] + pub fn set_idmabtcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Maskr { + fn default() -> Maskr { + Maskr(0) + } + } + #[doc = "The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fifor(pub u32); + impl Fifor { + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub const fn fifodata(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words."] + pub fn set_fifodata(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Fifor { + fn default() -> Fifor { + Fifor(0) + } + } + #[doc = "The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Resp2r(pub u32); + impl Resp2r { + #[doc = "see Table404."] + pub const fn cardstatus2(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "see Table404."] + pub fn set_cardstatus2(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Resp2r { + fn default() -> Resp2r { + Resp2r(0) + } + } + #[doc = "The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idmactrlr(pub u32); + impl Idmactrlr { + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub const fn idmabmode(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)."] + pub fn set_idmabmode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub const fn idmabact(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware."] + pub fn set_idmabact(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + } + impl Default for Idmactrlr { + fn default() -> Idmactrlr { + Idmactrlr(0) + } + } + #[doc = "The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Icr(pub u32); + impl Icr { + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub const fn ccrcfailc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag."] + pub fn set_ccrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub const fn dcrcfailc(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag."] + pub fn set_dcrcfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub const fn ctimeoutc(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag."] + pub fn set_ctimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub const fn dtimeoutc(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag."] + pub fn set_dtimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub const fn txunderrc(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "TXUNDERR flag clear bit Set by software to clear TXUNDERR flag."] + pub fn set_txunderrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub const fn rxoverrc(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXOVERR flag clear bit Set by software to clear the RXOVERR flag."] + pub fn set_rxoverrc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub const fn cmdrendc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "CMDREND flag clear bit Set by software to clear the CMDREND flag."] + pub fn set_cmdrendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub const fn cmdsentc(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "CMDSENT flag clear bit Set by software to clear the CMDSENT flag."] + pub fn set_cmdsentc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub const fn dataendc(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "DATAEND flag clear bit Set by software to clear the DATAEND flag."] + pub fn set_dataendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub const fn dholdc(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "DHOLD flag clear bit Set by software to clear the DHOLD flag."] + pub fn set_dholdc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub const fn dbckendc(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "DBCKEND flag clear bit Set by software to clear the DBCKEND flag."] + pub fn set_dbckendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub const fn dabortc(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "DABORT flag clear bit Set by software to clear the DABORT flag."] + pub fn set_dabortc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub const fn busyd0endc(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag."] + pub fn set_busyd0endc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub const fn sdioitc(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "SDIOIT flag clear bit Set by software to clear the SDIOIT flag."] + pub fn set_sdioitc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub const fn ackfailc(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag."] + pub fn set_ackfailc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub const fn acktimeoutc(&self) -> bool { + let val = (self.0 >> 24usize) & 0x01; + val != 0 + } + #[doc = "ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag."] + pub fn set_acktimeoutc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize); + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub const fn vswendc(&self) -> bool { + let val = (self.0 >> 25usize) & 0x01; + val != 0 + } + #[doc = "VSWEND flag clear bit Set by software to clear the VSWEND flag."] + pub fn set_vswendc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize); + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub const fn ckstopc(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "CKSTOP flag clear bit Set by software to clear the CKSTOP flag."] + pub fn set_ckstopc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub const fn idmatec(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "IDMA transfer error clear bit Set by software to clear the IDMATE flag."] + pub fn set_idmatec(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub const fn idmabtcc(&self) -> bool { + let val = (self.0 >> 28usize) & 0x01; + val != 0 + } + #[doc = "IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag."] + pub fn set_idmabtcc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize); + } + } + impl Default for Icr { + fn default() -> Icr { + Icr(0) + } + } + #[doc = "The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set."] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dtimer(pub u32); + impl Dtimer { + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub const fn datatime(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods."] + pub fn set_datatime(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Dtimer { + fn default() -> Dtimer { + Dtimer(0) + } + } + } +} +pub mod syscfg_f4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrm(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "peripheral mode configuration register"] + pub fn pmc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Compensation cell control register"] + pub fn cmpcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "peripheral mode configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pmc(pub u32); + impl Pmc { + #[doc = "ADC1DC2"] + pub const fn adc1dc2(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "ADC1DC2"] + pub fn set_adc1dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "ADC2DC2"] + pub const fn adc2dc2(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "ADC2DC2"] + pub fn set_adc2dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "ADC3DC2"] + pub const fn adc3dc2(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "ADC3DC2"] + pub fn set_adc3dc2(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Ethernet PHY interface selection"] + pub const fn mii_rmii_sel(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Ethernet PHY interface selection"] + pub fn set_mii_rmii_sel(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + } + impl Default for Pmc { + fn default() -> Pmc { + Pmc(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrm(pub u32); + impl Memrm { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "Flash bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FMC memory mapping swap"] + pub const fn swp_fmc(&self) -> u8 { + let val = (self.0 >> 10usize) & 0x03; + val as u8 + } + #[doc = "FMC memory mapping swap"] + pub fn set_swp_fmc(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize); + } + } + impl Default for Memrm { + fn default() -> Memrm { + Memrm(0) + } + } + #[doc = "Compensation cell control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cmpcr(pub u32); + impl Cmpcr { + #[doc = "Compensation cell power-down"] + pub const fn cmp_pd(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Compensation cell power-down"] + pub fn set_cmp_pd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "READY"] + pub const fn ready(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "READY"] + pub fn set_ready(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cmpcr { + fn default() -> Cmpcr { + Cmpcr(0) + } + } + #[doc = "external interrupt configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI x configuration"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI x configuration"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + } +} +pub mod timer_v1 { + use crate::generic::*; + #[doc = "Advanced-timers"] + #[derive(Copy, Clone)] + pub struct TimAdv(pub *mut u8); + unsafe impl Send for TimAdv {} + unsafe impl Sync for TimAdv {} + impl TimAdv { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "repetition counter register"] + pub fn rcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(48usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "break and dead-time register"] + pub fn bdtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(68usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "General purpose 16-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp16(pub *mut u8); + unsafe impl Send for TimGp16 {} + unsafe impl Sync for TimGp16 {} + impl TimGp16 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + #[doc = "Basic timer"] + #[derive(Copy, Clone)] + pub struct TimBasic(pub *mut u8); + unsafe impl Send for TimBasic {} + unsafe impl Sync for TimBasic {} + impl TimBasic { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + } + #[doc = "General purpose 32-bit timer"] + #[derive(Copy, Clone)] + pub struct TimGp32(pub *mut u8); + unsafe impl Send for TimGp32 {} + unsafe impl Sync for TimGp32 {} + impl TimGp32 { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "slave mode control register"] + pub fn smcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA/Interrupt enable register"] + pub fn dier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "event generation register"] + pub fn egr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "capture/compare mode register 1 (input mode)"] + pub fn ccmr_input(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare mode register 1 (output mode)"] + pub fn ccmr_output(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(24usize + n * 4usize)) } + } + #[doc = "capture/compare enable register"] + pub fn ccer(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "counter"] + pub fn cnt(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "prescaler"] + pub fn psc(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + #[doc = "auto-reload register"] + pub fn arr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(44usize)) } + } + #[doc = "capture/compare register"] + pub fn ccr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(52usize + n * 4usize)) } + } + #[doc = "DMA control register"] + pub fn dcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(72usize)) } + } + #[doc = "DMA address for full transfer"] + pub fn dmar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(76usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocpe(pub u8); + impl Ocpe { + #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] + pub const DISABLED: Self = Self(0); + #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msm(pub u8); + impl Msm { + #[doc = "No action"] + pub const NOSYNC: Self = Self(0); + #[doc = "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + pub const SYNC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ocm(pub u8); + impl Ocm { + #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + pub const FROZEN: Self = Self(0); + #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + pub const ACTIVEONMATCH: Self = Self(0x01); + #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + pub const INACTIVEONMATCH: Self = Self(0x02); + #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + pub const TOGGLE: Self = Self(0x03); + #[doc = "OCyREF is forced low"] + pub const FORCEINACTIVE: Self = Self(0x04); + #[doc = "OCyREF is forced high"] + pub const FORCEACTIVE: Self = Self(0x05); + #[doc = "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + pub const PWMMODE1: Self = Self(0x06); + #[doc = "Inversely to PwmMode1"] + pub const PWMMODE2: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mms(pub u8); + impl Mms { + #[doc = "The UG bit from the TIMx_EGR register is used as trigger output"] + pub const RESET: Self = Self(0); + #[doc = "The counter enable signal, CNT_EN, is used as trigger output"] + pub const ENABLE: Self = Self(0x01); + #[doc = "The update event is selected as trigger output"] + pub const UPDATE: Self = Self(0x02); + #[doc = "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + pub const COMPAREPULSE: Self = Self(0x03); + #[doc = "OC1REF signal is used as trigger output"] + pub const COMPAREOC1: Self = Self(0x04); + #[doc = "OC2REF signal is used as trigger output"] + pub const COMPAREOC2: Self = Self(0x05); + #[doc = "OC3REF signal is used as trigger output"] + pub const COMPAREOC3: Self = Self(0x06); + #[doc = "OC4REF signal is used as trigger output"] + pub const COMPAREOC4: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Arpe(pub u8); + impl Arpe { + #[doc = "TIMx_APRR register is not buffered"] + pub const DISABLED: Self = Self(0); + #[doc = "TIMx_APRR register is buffered"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrOutputCcs(pub u8); + impl CcmrOutputCcs { + #[doc = "CCx channel is configured as output"] + pub const OUTPUT: Self = Self(0); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ckd(pub u8); + impl Ckd { + #[doc = "t_DTS = t_CK_INT"] + pub const DIV1: Self = Self(0); + #[doc = "t_DTS = 2 × t_CK_INT"] + pub const DIV2: Self = Self(0x01); + #[doc = "t_DTS = 4 × t_CK_INT"] + pub const DIV4: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Urs(pub u8); + impl Urs { + #[doc = "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + pub const ANYEVENT: Self = Self(0); + #[doc = "Only counter overflow/underflow generates an update interrupt or DMA request"] + pub const COUNTERONLY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etps(pub u8); + impl Etps { + #[doc = "Prescaler OFF"] + pub const DIV1: Self = Self(0); + #[doc = "ETRP frequency divided by 2"] + pub const DIV2: Self = Self(0x01); + #[doc = "ETRP frequency divided by 4"] + pub const DIV4: Self = Self(0x02); + #[doc = "ETRP frequency divided by 8"] + pub const DIV8: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ece(pub u8); + impl Ece { + #[doc = "External clock mode 2 disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Counter used as upcounter"] + pub const UP: Self = Self(0); + #[doc = "Counter used as downcounter"] + pub const DOWN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sms(pub u8); + impl Sms { + #[doc = "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + pub const DISABLED: Self = Self(0); + #[doc = "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + pub const ENCODER_MODE_1: Self = Self(0x01); + #[doc = "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + pub const ENCODER_MODE_2: Self = Self(0x02); + #[doc = "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + pub const ENCODER_MODE_3: Self = Self(0x03); + #[doc = "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + pub const RESET_MODE: Self = Self(0x04); + #[doc = "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + pub const GATED_MODE: Self = Self(0x05); + #[doc = "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + pub const TRIGGER_MODE: Self = Self(0x06); + #[doc = "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + pub const EXT_CLOCK_MODE: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossi(pub u8); + impl Ossi { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are forced to idle level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etp(pub u8); + impl Etp { + #[doc = "ETR is noninverted, active at high level or rising edge"] + pub const NOTINVERTED: Self = Self(0); + #[doc = "ETR is inverted, active at low level or falling edge"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ts(pub u8); + impl Ts { + #[doc = "Internal Trigger 0 (ITR0)"] + pub const ITR0: Self = Self(0); + #[doc = "Internal Trigger 1 (ITR1)"] + pub const ITR1: Self = Self(0x01); + #[doc = "Internal Trigger 2 (ITR2)"] + pub const ITR2: Self = Self(0x02); + #[doc = "TI1 Edge Detector (TI1F_ED)"] + pub const TI1F_ED: Self = Self(0x04); + #[doc = "Filtered Timer Input 1 (TI1FP1)"] + pub const TI1FP1: Self = Self(0x05); + #[doc = "Filtered Timer Input 2 (TI2FP2)"] + pub const TI2FP2: Self = Self(0x06); + #[doc = "External Trigger input (ETRF)"] + pub const ETRF: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ccds(pub u8); + impl Ccds { + #[doc = "CCx DMA request sent when CCx event occurs"] + pub const ONCOMPARE: Self = Self(0); + #[doc = "CCx DMA request sent when update event occurs"] + pub const ONUPDATE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cms(pub u8); + impl Cms { + #[doc = "The counter counts up or down depending on the direction bit"] + pub const EDGEALIGNED: Self = Self(0); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + pub const CENTERALIGNED1: Self = Self(0x01); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + pub const CENTERALIGNED2: Self = Self(0x02); + #[doc = "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + pub const CENTERALIGNED3: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tis(pub u8); + impl Tis { + #[doc = "The TIMx_CH1 pin is connected to TI1 input"] + pub const NORMAL: Self = Self(0); + #[doc = "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + pub const XOR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct CcmrInputCcs(pub u8); + impl CcmrInputCcs { + #[doc = "CCx channel is configured as input, normal mapping: ICx mapped to TIx"] + pub const TI4: Self = Self(0x01); + #[doc = "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)"] + pub const TI3: Self = Self(0x02); + #[doc = "CCx channel is configured as input, ICx is mapped on TRC"] + pub const TRC: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Etf(pub u8); + impl Etf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ossr(pub u8); + impl Ossr { + #[doc = "When inactive, OC/OCN outputs are disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "When inactive, OC/OCN outputs are enabled with their inactive level"] + pub const IDLELEVEL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Icf(pub u8); + impl Icf { + #[doc = "No filter, sampling is done at fDTS"] + pub const NOFILTER: Self = Self(0); + #[doc = "fSAMPLING=fCK_INT, N=2"] + pub const FCK_INT_N2: Self = Self(0x01); + #[doc = "fSAMPLING=fCK_INT, N=4"] + pub const FCK_INT_N4: Self = Self(0x02); + #[doc = "fSAMPLING=fCK_INT, N=8"] + pub const FCK_INT_N8: Self = Self(0x03); + #[doc = "fSAMPLING=fDTS/2, N=6"] + pub const FDTS_DIV2_N6: Self = Self(0x04); + #[doc = "fSAMPLING=fDTS/2, N=8"] + pub const FDTS_DIV2_N8: Self = Self(0x05); + #[doc = "fSAMPLING=fDTS/4, N=6"] + pub const FDTS_DIV4_N6: Self = Self(0x06); + #[doc = "fSAMPLING=fDTS/4, N=8"] + pub const FDTS_DIV4_N8: Self = Self(0x07); + #[doc = "fSAMPLING=fDTS/8, N=6"] + pub const FDTS_DIV8_N6: Self = Self(0x08); + #[doc = "fSAMPLING=fDTS/8, N=8"] + pub const FDTS_DIV8_N8: Self = Self(0x09); + #[doc = "fSAMPLING=fDTS/16, N=5"] + pub const FDTS_DIV16_N5: Self = Self(0x0a); + #[doc = "fSAMPLING=fDTS/16, N=6"] + pub const FDTS_DIV16_N6: Self = Self(0x0b); + #[doc = "fSAMPLING=fDTS/16, N=8"] + pub const FDTS_DIV16_N8: Self = Self(0x0c); + #[doc = "fSAMPLING=fDTS/32, N=5"] + pub const FDTS_DIV32_N5: Self = Self(0x0d); + #[doc = "fSAMPLING=fDTS/32, N=6"] + pub const FDTS_DIV32_N6: Self = Self(0x0e); + #[doc = "fSAMPLING=fDTS/32, N=8"] + pub const FDTS_DIV32_N8: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Opm(pub u8); + impl Opm { + #[doc = "Counter is not stopped at update event"] + pub const DISABLED: Self = Self(0); + #[doc = "Counter stops counting at the next update event (clearing the CEN bit)"] + pub const ENABLED: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "slave mode control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Smcr(pub u32); + impl Smcr { + #[doc = "Slave mode selection"] + pub const fn sms(&self) -> super::vals::Sms { + let val = (self.0 >> 0usize) & 0x07; + super::vals::Sms(val as u8) + } + #[doc = "Slave mode selection"] + pub fn set_sms(&mut self, val: super::vals::Sms) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val.0 as u32) & 0x07) << 0usize); + } + #[doc = "Trigger selection"] + pub const fn ts(&self) -> super::vals::Ts { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Ts(val as u8) + } + #[doc = "Trigger selection"] + pub fn set_ts(&mut self, val: super::vals::Ts) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "Master/Slave mode"] + pub const fn msm(&self) -> super::vals::Msm { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Msm(val as u8) + } + #[doc = "Master/Slave mode"] + pub fn set_msm(&mut self, val: super::vals::Msm) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "External trigger filter"] + pub const fn etf(&self) -> super::vals::Etf { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Etf(val as u8) + } + #[doc = "External trigger filter"] + pub fn set_etf(&mut self, val: super::vals::Etf) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "External trigger prescaler"] + pub const fn etps(&self) -> super::vals::Etps { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Etps(val as u8) + } + #[doc = "External trigger prescaler"] + pub fn set_etps(&mut self, val: super::vals::Etps) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "External clock enable"] + pub const fn ece(&self) -> super::vals::Ece { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Ece(val as u8) + } + #[doc = "External clock enable"] + pub fn set_ece(&mut self, val: super::vals::Ece) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "External trigger polarity"] + pub const fn etp(&self) -> super::vals::Etp { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Etp(val as u8) + } + #[doc = "External trigger polarity"] + pub fn set_etp(&mut self, val: super::vals::Etp) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Smcr { + fn default() -> Smcr { + Smcr(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrGp(pub u32); + impl EgrGp { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrGp { + fn default() -> EgrGp { + EgrGp(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr16(pub u32); + impl Arr16 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Arr16 { + fn default() -> Arr16 { + Arr16(0) + } + } + #[doc = "capture/compare mode register 1 (input mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrInput(pub u32); + impl CcmrInput { + #[doc = "Capture/Compare 1 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrInputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrInputCcs(val as u8) + } + #[doc = "Capture/Compare 1 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrInputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 prescaler"] + pub fn icpsc(&self, n: usize) -> u8 { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + val as u8 + } + #[doc = "Input capture 1 prescaler"] + pub fn set_icpsc(&mut self, n: usize, val: u8) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val as u32) & 0x03) << offs); + } + #[doc = "Input capture 1 filter"] + pub fn icf(&self, n: usize) -> super::vals::Icf { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Icf(val as u8) + } + #[doc = "Input capture 1 filter"] + pub fn set_icf(&mut self, n: usize, val: super::vals::Icf) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for CcmrInput { + fn default() -> CcmrInput { + CcmrInput(0) + } + } + #[doc = "repetition counter register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rcr(pub u32); + impl Rcr { + #[doc = "Repetition counter value"] + pub const fn rep(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Repetition counter value"] + pub fn set_rep(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Rcr { + fn default() -> Rcr { + Rcr(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr32(pub u32); + impl Ccr32 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Ccr32 { + fn default() -> Ccr32 { + Ccr32(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrGp(pub u32); + impl SrGp { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrGp { + fn default() -> SrGp { + SrGp(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Basic(pub u32); + impl Cr1Basic { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr1Basic { + fn default() -> Cr1Basic { + Cr1Basic(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Adv(pub u32); + impl Cr2Adv { + #[doc = "Capture/compare preloaded control"] + pub const fn ccpc(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare preloaded control"] + pub fn set_ccpc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare control update selection"] + pub const fn ccus(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Capture/compare control update selection"] + pub fn set_ccus(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Output Idle state 1"] + pub fn ois(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 8usize + n * 2usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output Idle state 1"] + pub const fn ois1n(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 1"] + pub fn set_ois1n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Output Idle state 2"] + pub const fn ois2n(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 2"] + pub fn set_ois2n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Output Idle state 3"] + pub const fn ois3n(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Output Idle state 3"] + pub fn set_ois3n(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr2Adv { + fn default() -> Cr2Adv { + Cr2Adv(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Gp(pub u32); + impl Cr2Gp { + #[doc = "Capture/compare DMA selection"] + pub const fn ccds(&self) -> super::vals::Ccds { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Ccds(val as u8) + } + #[doc = "Capture/compare DMA selection"] + pub fn set_ccds(&mut self, val: super::vals::Ccds) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + #[doc = "TI1 selection"] + pub const fn ti1s(&self) -> super::vals::Tis { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Tis(val as u8) + } + #[doc = "TI1 selection"] + pub fn set_ti1s(&mut self, val: super::vals::Tis) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2Gp { + fn default() -> Cr2Gp { + Cr2Gp(0) + } + } + #[doc = "capture/compare register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ccr16(pub u32); + impl Ccr16 { + #[doc = "Capture/Compare 1 value"] + pub const fn ccr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Capture/Compare 1 value"] + pub fn set_ccr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ccr16 { + fn default() -> Ccr16 { + Ccr16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierBasic(pub u32); + impl DierBasic { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for DierBasic { + fn default() -> DierBasic { + DierBasic(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt32(pub u32); + impl Cnt32 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Cnt32 { + fn default() -> Cnt32 { + Cnt32(0) + } + } + #[doc = "capture/compare mode register 2 (output mode)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcmrOutput(pub u32); + impl CcmrOutput { + #[doc = "Capture/Compare 3 selection"] + pub fn ccs(&self, n: usize) -> super::vals::CcmrOutputCcs { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + let val = (self.0 >> offs) & 0x03; + super::vals::CcmrOutputCcs(val as u8) + } + #[doc = "Capture/Compare 3 selection"] + pub fn set_ccs(&mut self, n: usize, val: super::vals::CcmrOutputCcs) { + assert!(n < 2usize); + let offs = 0usize + n * 8usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Output compare 3 fast enable"] + pub fn ocfe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 fast enable"] + pub fn set_ocfe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 2usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 preload enable"] + pub fn ocpe(&self, n: usize) -> super::vals::Ocpe { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ocpe(val as u8) + } + #[doc = "Output compare 3 preload enable"] + pub fn set_ocpe(&mut self, n: usize, val: super::vals::Ocpe) { + assert!(n < 2usize); + let offs = 3usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Output compare 3 mode"] + pub fn ocm(&self, n: usize) -> super::vals::Ocm { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + let val = (self.0 >> offs) & 0x07; + super::vals::Ocm(val as u8) + } + #[doc = "Output compare 3 mode"] + pub fn set_ocm(&mut self, n: usize, val: super::vals::Ocm) { + assert!(n < 2usize); + let offs = 4usize + n * 8usize; + self.0 = (self.0 & !(0x07 << offs)) | (((val.0 as u32) & 0x07) << offs); + } + #[doc = "Output compare 3 clear enable"] + pub fn occe(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Output compare 3 clear enable"] + pub fn set_occe(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 7usize + n * 8usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcmrOutput { + fn default() -> CcmrOutput { + CcmrOutput(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1Gp(pub u32); + impl Cr1Gp { + #[doc = "Counter enable"] + pub const fn cen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Counter enable"] + pub fn set_cen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Update disable"] + pub const fn udis(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Update disable"] + pub fn set_udis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Update request source"] + pub const fn urs(&self) -> super::vals::Urs { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Urs(val as u8) + } + #[doc = "Update request source"] + pub fn set_urs(&mut self, val: super::vals::Urs) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "One-pulse mode"] + pub const fn opm(&self) -> super::vals::Opm { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Opm(val as u8) + } + #[doc = "One-pulse mode"] + pub fn set_opm(&mut self, val: super::vals::Opm) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Center-aligned mode selection"] + pub const fn cms(&self) -> super::vals::Cms { + let val = (self.0 >> 5usize) & 0x03; + super::vals::Cms(val as u8) + } + #[doc = "Center-aligned mode selection"] + pub fn set_cms(&mut self, val: super::vals::Cms) { + self.0 = (self.0 & !(0x03 << 5usize)) | (((val.0 as u32) & 0x03) << 5usize); + } + #[doc = "Auto-reload preload enable"] + pub const fn arpe(&self) -> super::vals::Arpe { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Arpe(val as u8) + } + #[doc = "Auto-reload preload enable"] + pub fn set_arpe(&mut self, val: super::vals::Arpe) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Clock division"] + pub const fn ckd(&self) -> super::vals::Ckd { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Ckd(val as u8) + } + #[doc = "Clock division"] + pub fn set_ckd(&mut self, val: super::vals::Ckd) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + } + impl Default for Cr1Gp { + fn default() -> Cr1Gp { + Cr1Gp(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrAdv(pub u32); + impl SrAdv { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn ccif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 interrupt flag"] + pub fn set_ccif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt flag"] + pub const fn comif(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt flag"] + pub fn set_comif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt flag"] + pub const fn tif(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt flag"] + pub fn set_tif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt flag"] + pub const fn bif(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt flag"] + pub fn set_bif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn ccof(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 overcapture flag"] + pub fn set_ccof(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for SrAdv { + fn default() -> SrAdv { + SrAdv(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Basic(pub u32); + impl Cr2Basic { + #[doc = "Master mode selection"] + pub const fn mms(&self) -> super::vals::Mms { + let val = (self.0 >> 4usize) & 0x07; + super::vals::Mms(val as u8) + } + #[doc = "Master mode selection"] + pub fn set_mms(&mut self, val: super::vals::Mms) { + self.0 = (self.0 & !(0x07 << 4usize)) | (((val.0 as u32) & 0x07) << 4usize); + } + } + impl Default for Cr2Basic { + fn default() -> Cr2Basic { + Cr2Basic(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerAdv(pub u32); + impl CcerAdv { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn ccne(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 complementary output enable"] + pub fn set_ccne(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerAdv { + fn default() -> CcerAdv { + CcerAdv(0) + } + } + #[doc = "DMA control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dcr(pub u32); + impl Dcr { + #[doc = "DMA base address"] + pub const fn dba(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x1f; + val as u8 + } + #[doc = "DMA base address"] + pub fn set_dba(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 0usize)) | (((val as u32) & 0x1f) << 0usize); + } + #[doc = "DMA burst length"] + pub const fn dbl(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x1f; + val as u8 + } + #[doc = "DMA burst length"] + pub fn set_dbl(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 8usize)) | (((val as u32) & 0x1f) << 8usize); + } + } + impl Default for Dcr { + fn default() -> Dcr { + Dcr(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierAdv(pub u32); + impl DierAdv { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM interrupt enable"] + pub const fn comie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "COM interrupt enable"] + pub fn set_comie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break interrupt enable"] + pub const fn bie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break interrupt enable"] + pub fn set_bie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "COM DMA request enable"] + pub const fn comde(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "COM DMA request enable"] + pub fn set_comde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierAdv { + fn default() -> DierAdv { + DierAdv(0) + } + } + #[doc = "break and dead-time register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bdtr(pub u32); + impl Bdtr { + #[doc = "Dead-time generator setup"] + pub const fn dtg(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Dead-time generator setup"] + pub fn set_dtg(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Lock configuration"] + pub const fn lock(&self) -> u8 { + let val = (self.0 >> 8usize) & 0x03; + val as u8 + } + #[doc = "Lock configuration"] + pub fn set_lock(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val as u32) & 0x03) << 8usize); + } + #[doc = "Off-state selection for Idle mode"] + pub const fn ossi(&self) -> super::vals::Ossi { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Ossi(val as u8) + } + #[doc = "Off-state selection for Idle mode"] + pub fn set_ossi(&mut self, val: super::vals::Ossi) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Off-state selection for Run mode"] + pub const fn ossr(&self) -> super::vals::Ossr { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Ossr(val as u8) + } + #[doc = "Off-state selection for Run mode"] + pub fn set_ossr(&mut self, val: super::vals::Ossr) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Break enable"] + pub const fn bke(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "Break enable"] + pub fn set_bke(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Break polarity"] + pub const fn bkp(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Break polarity"] + pub fn set_bkp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Automatic output enable"] + pub const fn aoe(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Automatic output enable"] + pub fn set_aoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Main output enable"] + pub const fn moe(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Main output enable"] + pub fn set_moe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + } + impl Default for Bdtr { + fn default() -> Bdtr { + Bdtr(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrAdv(pub u32); + impl EgrAdv { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/compare 1 generation"] + pub fn ccg(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/compare 1 generation"] + pub fn set_ccg(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare control update generation"] + pub const fn comg(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Capture/Compare control update generation"] + pub fn set_comg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Trigger generation"] + pub const fn tg(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger generation"] + pub fn set_tg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Break generation"] + pub const fn bg(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Break generation"] + pub fn set_bg(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for EgrAdv { + fn default() -> EgrAdv { + EgrAdv(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrBasic(pub u32); + impl SrBasic { + #[doc = "Update interrupt flag"] + pub const fn uif(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt flag"] + pub fn set_uif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for SrBasic { + fn default() -> SrBasic { + SrBasic(0) + } + } + #[doc = "auto-reload register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Arr32(pub u32); + impl Arr32 { + #[doc = "Auto-reload value"] + pub const fn arr(&self) -> u32 { + let val = (self.0 >> 0usize) & 0xffff_ffff; + val as u32 + } + #[doc = "Auto-reload value"] + pub fn set_arr(&mut self, val: u32) { + self.0 = + (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize); + } + } + impl Default for Arr32 { + fn default() -> Arr32 { + Arr32(0) + } + } + #[doc = "counter"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cnt16(pub u32); + impl Cnt16 { + #[doc = "counter value"] + pub const fn cnt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "counter value"] + pub fn set_cnt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Cnt16 { + fn default() -> Cnt16 { + Cnt16(0) + } + } + #[doc = "DMA/Interrupt enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct DierGp(pub u32); + impl DierGp { + #[doc = "Update interrupt enable"] + pub const fn uie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update interrupt enable"] + pub fn set_uie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn ccie(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 interrupt enable"] + pub fn set_ccie(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger interrupt enable"] + pub const fn tie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Trigger interrupt enable"] + pub fn set_tie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Update DMA request enable"] + pub const fn ude(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Update DMA request enable"] + pub fn set_ude(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn ccde(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 DMA request enable"] + pub fn set_ccde(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 9usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Trigger DMA request enable"] + pub const fn tde(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Trigger DMA request enable"] + pub fn set_tde(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for DierGp { + fn default() -> DierGp { + DierGp(0) + } + } + #[doc = "prescaler"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Psc(pub u32); + impl Psc { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Psc { + fn default() -> Psc { + Psc(0) + } + } + #[doc = "event generation register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct EgrBasic(pub u32); + impl EgrBasic { + #[doc = "Update generation"] + pub const fn ug(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Update generation"] + pub fn set_ug(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + } + impl Default for EgrBasic { + fn default() -> EgrBasic { + EgrBasic(0) + } + } + #[doc = "DMA address for full transfer"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dmar(pub u32); + impl Dmar { + #[doc = "DMA register for burst accesses"] + pub const fn dmab(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "DMA register for burst accesses"] + pub fn set_dmab(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dmar { + fn default() -> Dmar { + Dmar(0) + } + } + #[doc = "capture/compare enable register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct CcerGp(pub u32); + impl CcerGp { + #[doc = "Capture/Compare 1 output enable"] + pub fn cce(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output enable"] + pub fn set_cce(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn ccnp(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Capture/Compare 1 output Polarity"] + pub fn set_ccnp(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for CcerGp { + fn default() -> CcerGp { + CcerGp(0) + } + } + } +} +pub mod gpio_v1 { + use crate::generic::*; + #[doc = "General purpose I/O"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "Port configuration register low (GPIOn_CRL)"] + pub fn cr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "Port input data register (GPIOn_IDR)"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Port output data register (GPIOn_ODR)"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Port input data register (GPIOn_IDR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "Port bit reset register (GPIOn_BRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Port output data register (GPIOn_ODR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "Port bit set/reset register (GPIOn_BSRR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Set bit"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Set bit"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Reset bit"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Reset bit"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "Port configuration register (GPIOn_CRx)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Port n mode bits"] + pub fn mode(&self, n: usize) -> super::vals::Mode { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Mode(val as u8) + } + #[doc = "Port n mode bits"] + pub fn set_mode(&mut self, n: usize, val: super::vals::Mode) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + #[doc = "Port n configuration bits"] + pub fn cnf(&self, n: usize) -> super::vals::Cnf { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Cnf(val as u8) + } + #[doc = "Port n configuration bits"] + pub fn set_cnf(&mut self, n: usize, val: super::vals::Cnf) { + assert!(n < 8usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "Port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port A Lock bit"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port A Lock bit"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Lock key"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Lock key"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Reset the ODx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cnf(pub u8); + impl Cnf { + #[doc = "Analog mode / Push-Pull mode"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Floating input (reset state) / Open Drain-Mode"] + pub const OPENDRAIN: Self = Self(0x01); + #[doc = "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] + pub const ALTPUSHPULL: Self = Self(0x02); + #[doc = "Alternate Function Open-Drain Mode"] + pub const ALTOPENDRAIN: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "No action on the corresponding ODx bit"] + pub const NOACTION: Self = Self(0); + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mode(pub u8); + impl Mode { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "Output mode 10 MHz"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Output mode 2 MHz"] + pub const OUTPUT2: Self = Self(0x02); + #[doc = "Output mode 50 MHz"] + pub const OUTPUT50: Self = Self(0x03); + } + } +} +pub mod generic { + use core::marker::PhantomData; + #[derive(Copy, Clone)] + pub struct RW; + #[derive(Copy, Clone)] + pub struct R; + #[derive(Copy, Clone)] + pub struct W; + mod sealed { + use super::*; + pub trait Access {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + } + pub trait Access: sealed::Access + Copy {} + impl Access for R {} + impl Access for W {} + impl Access for RW {} + pub trait Read: Access {} + impl Read for RW {} + impl Read for R {} + pub trait Write: Access {} + impl Write for RW {} + impl Write for W {} + #[derive(Copy, Clone)] + pub struct Reg { + ptr: *mut u8, + phantom: PhantomData<*mut (T, A)>, + } + unsafe impl Send for Reg {} + unsafe impl Sync for Reg {} + impl Reg { + pub fn from_ptr(ptr: *mut u8) -> Self { + Self { + ptr, + phantom: PhantomData, + } + } + pub fn ptr(&self) -> *mut T { + self.ptr as _ + } + } + impl Reg { + pub unsafe fn read(&self) -> T { + (self.ptr as *mut T).read_volatile() + } + } + impl Reg { + pub unsafe fn write_value(&self, val: T) { + (self.ptr as *mut T).write_volatile(val) + } + } + impl Reg { + pub unsafe fn write(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = Default::default(); + let res = f(&mut val); + self.write_value(val); + res + } + } + impl Reg { + pub unsafe fn modify(&self, f: impl FnOnce(&mut T) -> R) -> R { + let mut val = self.read(); + let res = f(&mut val); + self.write_value(val); + res + } + } +} +pub mod dma_v1 { + use crate::generic::*; + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "DMA interrupt status register (DMA_ISR)"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + pub fn ifcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + pub fn ch(self, n: usize) -> Ch { + assert!(n < 7usize); + unsafe { Ch(self.0.add(8usize + n * 20usize)) } + } + } + #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] + #[derive(Copy, Clone)] + pub struct Ch(pub *mut u8); + unsafe impl Send for Ch {} + unsafe impl Sync for Ch {} + impl Ch { + #[doc = "DMA channel configuration register (DMA_CCR)"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "DMA channel 1 number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "DMA channel 1 peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "DMA channel 1 memory address register"] + pub fn mar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ifcr(pub u32); + impl Ifcr { + #[doc = "Channel 1 Global interrupt clear"] + pub fn cgif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt clear"] + pub fn set_cgif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn ctcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete clear"] + pub fn set_ctcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn chtif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer clear"] + pub fn set_chtif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn cteif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error clear"] + pub fn set_cteif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ifcr { + fn default() -> Ifcr { + Ifcr(0) + } + } + #[doc = "DMA interrupt status register (DMA_ISR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Isr(pub u32); + impl Isr { + #[doc = "Channel 1 Global interrupt flag"] + pub fn gif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Global interrupt flag"] + pub fn set_gif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Complete flag"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 1usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Half Transfer Complete flag"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 2usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Channel 1 Transfer Error flag"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 7usize); + let offs = 3usize + n * 4usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Isr { + fn default() -> Isr { + Isr(0) + } + } + #[doc = "DMA channel 1 number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "DMA channel configuration register (DMA_CCR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Channel enable"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Channel enable"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Half Transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Half Transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 6usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val.0 as u32) & 0x01) << 6usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Peripheral size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 8usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 8usize)) | (((val.0 as u32) & 0x03) << 8usize); + } + #[doc = "Memory size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 10usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 10usize)) | (((val.0 as u32) & 0x03) << 10usize); + } + #[doc = "Channel Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Channel Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "Memory to memory mode"] + pub const fn mem2mem(&self) -> super::vals::Memmem { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Memmem(val as u8) + } + #[doc = "Memory to memory mode"] + pub fn set_mem2mem(&mut self, val: super::vals::Memmem) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Memmem(pub u8); + impl Memmem { + #[doc = "Memory to memory mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory to memory mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular buffer disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular buffer enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Increment mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Increment mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Read from peripheral"] + pub const FROMPERIPHERAL: Self = Self(0); + #[doc = "Read from memory"] + pub const FROMMEMORY: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "8-bit size"] + pub const BITS8: Self = Self(0); + #[doc = "16-bit size"] + pub const BITS16: Self = Self(0x01); + #[doc = "32-bit size"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low priority"] + pub const LOW: Self = Self(0); + #[doc = "Medium priority"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High priority"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high priority"] + pub const VERYHIGH: Self = Self(0x03); + } + } +} +pub mod gpio_v2 { + use crate::generic::*; + #[doc = "General-purpose I/Os"] + #[derive(Copy, Clone)] + pub struct Gpio(pub *mut u8); + unsafe impl Send for Gpio {} + unsafe impl Sync for Gpio {} + impl Gpio { + #[doc = "GPIO port mode register"] + pub fn moder(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "GPIO port output type register"] + pub fn otyper(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "GPIO port output speed register"] + pub fn ospeedr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "GPIO port pull-up/pull-down register"] + pub fn pupdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "GPIO port input data register"] + pub fn idr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "GPIO port output data register"] + pub fn odr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "GPIO port bit set/reset register"] + pub fn bsrr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "GPIO port configuration lock register"] + pub fn lckr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "GPIO alternate function register (low, high)"] + pub fn afr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(32usize + n * 4usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "GPIO port input data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Idr(pub u32); + impl Idr { + #[doc = "Port input data (y = 0..15)"] + pub fn idr(&self, n: usize) -> super::vals::Idr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Idr(val as u8) + } + #[doc = "Port input data (y = 0..15)"] + pub fn set_idr(&mut self, n: usize, val: super::vals::Idr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Idr { + fn default() -> Idr { + Idr(0) + } + } + #[doc = "GPIO port pull-up/pull-down register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pupdr(pub u32); + impl Pupdr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn pupdr(&self, n: usize) -> super::vals::Pupdr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Pupdr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_pupdr(&mut self, n: usize, val: super::vals::Pupdr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Pupdr { + fn default() -> Pupdr { + Pupdr(0) + } + } + #[doc = "GPIO port output type register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Otyper(pub u32); + impl Otyper { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ot(&self, n: usize) -> super::vals::Ot { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Ot(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ot(&mut self, n: usize, val: super::vals::Ot) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Otyper { + fn default() -> Otyper { + Otyper(0) + } + } + #[doc = "GPIO port bit set/reset register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Bsrr(pub u32); + impl Bsrr { + #[doc = "Port x set bit y (y= 0..15)"] + pub fn bs(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_bs(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn br(&self, n: usize) -> bool { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Port x set bit y (y= 0..15)"] + pub fn set_br(&mut self, n: usize, val: bool) { + assert!(n < 16usize); + let offs = 16usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Bsrr { + fn default() -> Bsrr { + Bsrr(0) + } + } + #[doc = "GPIO port configuration lock register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Lckr(pub u32); + impl Lckr { + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn lck(&self, n: usize) -> super::vals::Lck { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Lck(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lck(&mut self, n: usize, val: super::vals::Lck) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub const fn lckk(&self) -> super::vals::Lckk { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Lckk(val as u8) + } + #[doc = "Port x lock bit y (y= 0..15)"] + pub fn set_lckk(&mut self, val: super::vals::Lckk) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + } + impl Default for Lckr { + fn default() -> Lckr { + Lckr(0) + } + } + #[doc = "GPIO port mode register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Moder(pub u32); + impl Moder { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn moder(&self, n: usize) -> super::vals::Moder { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Moder(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_moder(&mut self, n: usize, val: super::vals::Moder) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Moder { + fn default() -> Moder { + Moder(0) + } + } + #[doc = "GPIO port output data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Odr(pub u32); + impl Odr { + #[doc = "Port output data (y = 0..15)"] + pub fn odr(&self, n: usize) -> super::vals::Odr { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Odr(val as u8) + } + #[doc = "Port output data (y = 0..15)"] + pub fn set_odr(&mut self, n: usize, val: super::vals::Odr) { + assert!(n < 16usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Odr { + fn default() -> Odr { + Odr(0) + } + } + #[doc = "GPIO alternate function register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Afr(pub u32); + impl Afr { + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn afr(&self, n: usize) -> super::vals::Afr { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + super::vals::Afr(val as u8) + } + #[doc = "Alternate function selection for port x bit y (y = 0..15)"] + pub fn set_afr(&mut self, n: usize, val: super::vals::Afr) { + assert!(n < 8usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val.0 as u32) & 0x0f) << offs); + } + } + impl Default for Afr { + fn default() -> Afr { + Afr(0) + } + } + #[doc = "GPIO port output speed register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ospeedr(pub u32); + impl Ospeedr { + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn ospeedr(&self, n: usize) -> super::vals::Ospeedr { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + let val = (self.0 >> offs) & 0x03; + super::vals::Ospeedr(val as u8) + } + #[doc = "Port x configuration bits (y = 0..15)"] + pub fn set_ospeedr(&mut self, n: usize, val: super::vals::Ospeedr) { + assert!(n < 16usize); + let offs = 0usize + n * 2usize; + self.0 = (self.0 & !(0x03 << offs)) | (((val.0 as u32) & 0x03) << offs); + } + } + impl Default for Ospeedr { + fn default() -> Ospeedr { + Ospeedr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Idr(pub u8); + impl Idr { + #[doc = "Input is logic low"] + pub const LOW: Self = Self(0); + #[doc = "Input is logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bsw(pub u8); + impl Bsw { + #[doc = "Sets the corresponding ODRx bit"] + pub const SET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lckk(pub u8); + impl Lckk { + #[doc = "Port configuration lock key not active"] + pub const NOTACTIVE: Self = Self(0); + #[doc = "Port configuration lock key active"] + pub const ACTIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lck(pub u8); + impl Lck { + #[doc = "Port configuration not locked"] + pub const UNLOCKED: Self = Self(0); + #[doc = "Port configuration locked"] + pub const LOCKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Brw(pub u8); + impl Brw { + #[doc = "Resets the corresponding ODRx bit"] + pub const RESET: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ospeedr(pub u8); + impl Ospeedr { + #[doc = "Low speed"] + pub const LOWSPEED: Self = Self(0); + #[doc = "Medium speed"] + pub const MEDIUMSPEED: Self = Self(0x01); + #[doc = "High speed"] + pub const HIGHSPEED: Self = Self(0x02); + #[doc = "Very high speed"] + pub const VERYHIGHSPEED: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ot(pub u8); + impl Ot { + #[doc = "Output push-pull (reset state)"] + pub const PUSHPULL: Self = Self(0); + #[doc = "Output open-drain"] + pub const OPENDRAIN: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Afr(pub u8); + impl Afr { + #[doc = "AF0"] + pub const AF0: Self = Self(0); + #[doc = "AF1"] + pub const AF1: Self = Self(0x01); + #[doc = "AF2"] + pub const AF2: Self = Self(0x02); + #[doc = "AF3"] + pub const AF3: Self = Self(0x03); + #[doc = "AF4"] + pub const AF4: Self = Self(0x04); + #[doc = "AF5"] + pub const AF5: Self = Self(0x05); + #[doc = "AF6"] + pub const AF6: Self = Self(0x06); + #[doc = "AF7"] + pub const AF7: Self = Self(0x07); + #[doc = "AF8"] + pub const AF8: Self = Self(0x08); + #[doc = "AF9"] + pub const AF9: Self = Self(0x09); + #[doc = "AF10"] + pub const AF10: Self = Self(0x0a); + #[doc = "AF11"] + pub const AF11: Self = Self(0x0b); + #[doc = "AF12"] + pub const AF12: Self = Self(0x0c); + #[doc = "AF13"] + pub const AF13: Self = Self(0x0d); + #[doc = "AF14"] + pub const AF14: Self = Self(0x0e); + #[doc = "AF15"] + pub const AF15: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Moder(pub u8); + impl Moder { + #[doc = "Input mode (reset state)"] + pub const INPUT: Self = Self(0); + #[doc = "General purpose output mode"] + pub const OUTPUT: Self = Self(0x01); + #[doc = "Alternate function mode"] + pub const ALTERNATE: Self = Self(0x02); + #[doc = "Analog mode"] + pub const ANALOG: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Odr(pub u8); + impl Odr { + #[doc = "Set output to logic low"] + pub const LOW: Self = Self(0); + #[doc = "Set output to logic high"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pupdr(pub u8); + impl Pupdr { + #[doc = "No pull-up, pull-down"] + pub const FLOATING: Self = Self(0); + #[doc = "Pull-up"] + pub const PULLUP: Self = Self(0x01); + #[doc = "Pull-down"] + pub const PULLDOWN: Self = Self(0x02); + } + } +} +pub mod exti_v1 { + use crate::generic::*; + #[doc = "External interrupt/event controller"] + #[derive(Copy, Clone)] + pub struct Exti(pub *mut u8); + unsafe impl Send for Exti {} + unsafe impl Sync for Exti {} + impl Exti { + #[doc = "Interrupt mask register (EXTI_IMR)"] + pub fn imr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Event mask register (EXTI_EMR)"] + pub fn emr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + pub fn rtsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + pub fn ftsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + pub fn swier(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Pending register (EXTI_PR)"] + pub fn pr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Rising Trigger selection register (EXTI_RTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rtsr(pub u32); + impl Rtsr { + #[doc = "Rising trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Rising trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Rtsr { + fn default() -> Rtsr { + Rtsr(0) + } + } + #[doc = "Interrupt mask register (EXTI_IMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Imr(pub u32); + impl Imr { + #[doc = "Interrupt Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Interrupt Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Imr { + fn default() -> Imr { + Imr(0) + } + } + #[doc = "Software interrupt event register (EXTI_SWIER)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swier(pub u32); + impl Swier { + #[doc = "Software Interrupt on line 0"] + pub fn swier(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Software Interrupt on line 0"] + pub fn set_swier(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swier { + fn default() -> Swier { + Swier(0) + } + } + #[doc = "Event mask register (EXTI_EMR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Emr(pub u32); + impl Emr { + #[doc = "Event Mask on line 0"] + pub fn mr(&self, n: usize) -> super::vals::Mr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Mr(val as u8) + } + #[doc = "Event Mask on line 0"] + pub fn set_mr(&mut self, n: usize, val: super::vals::Mr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Emr { + fn default() -> Emr { + Emr(0) + } + } + #[doc = "Pending register (EXTI_PR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Pr(pub u32); + impl Pr { + #[doc = "Pending bit 0"] + pub fn pr(&self, n: usize) -> bool { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Pending bit 0"] + pub fn set_pr(&mut self, n: usize, val: bool) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Pr { + fn default() -> Pr { + Pr(0) + } + } + #[doc = "Falling Trigger selection register (EXTI_FTSR)"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ftsr(pub u32); + impl Ftsr { + #[doc = "Falling trigger event configuration of line 0"] + pub fn tr(&self, n: usize) -> super::vals::Tr { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Tr(val as u8) + } + #[doc = "Falling trigger event configuration of line 0"] + pub fn set_tr(&mut self, n: usize, val: super::vals::Tr) { + assert!(n < 23usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + } + impl Default for Ftsr { + fn default() -> Ftsr { + Ftsr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prw(pub u8); + impl Prw { + #[doc = "Clears pending bit"] + pub const CLEAR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Prr(pub u8); + impl Prr { + #[doc = "No trigger request occurred"] + pub const NOTPENDING: Self = Self(0); + #[doc = "Selected trigger request occurred"] + pub const PENDING: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Tr(pub u8); + impl Tr { + #[doc = "Falling edge trigger is disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Falling edge trigger is enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mr(pub u8); + impl Mr { + #[doc = "Interrupt request line is masked"] + pub const MASKED: Self = Self(0); + #[doc = "Interrupt request line is unmasked"] + pub const UNMASKED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Swierw(pub u8); + impl Swierw { + #[doc = "Generates an interrupt request"] + pub const PEND: Self = Self(0x01); + } + } +} +pub mod usart_v1 { + use crate::generic::*; + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + #[doc = "Universal asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Uart(pub *mut u8); + unsafe impl Send for Uart {} + unsafe impl Sync for Uart {} + impl Uart { + #[doc = "Status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const HALFDUPLEX: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M(pub u8); + impl M { + #[doc = "8 data bits"] + pub const M8: Self = Self(0); + #[doc = "9 data bits"] + pub const M9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rwu(pub u8); + impl Rwu { + #[doc = "Receiver in active mode"] + pub const ACTIVE: Self = Self(0); + #[doc = "Receiver in mute mode"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bits"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bits"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bits"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "USART wakeup on idle line"] + pub const IDLELINE: Self = Self(0); + #[doc = "USART wakeup on address mark"] + pub const ADDRESSMARK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const LBDL10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const LBDL11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbk(pub u8); + impl Sbk { + #[doc = "No break character is transmitted"] + pub const NOBREAK: Self = Self(0); + #[doc = "Break character transmitted"] + pub const BREAK: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Send break"] + pub const fn sbk(&self) -> super::vals::Sbk { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Sbk(val as u8) + } + #[doc = "Send break"] + pub fn set_sbk(&mut self, val: super::vals::Sbk) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Receiver wakeup"] + pub const fn rwu(&self) -> super::vals::Rwu { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Rwu(val as u8) + } + #[doc = "Receiver wakeup"] + pub fn set_rwu(&mut self, val: super::vals::Rwu) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "TXE interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "TXE interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Wakeup method"] + pub const fn wake(&self) -> super::vals::Wake { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Wake(val as u8) + } + #[doc = "Wakeup method"] + pub fn set_wake(&mut self, val: super::vals::Wake) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m(&self) -> super::vals::M { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M(val as u8) + } + #[doc = "Word length"] + pub fn set_m(&mut self, val: super::vals::M) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "fraction of USARTDIV"] + pub const fn div_fraction(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "fraction of USARTDIV"] + pub fn set_div_fraction(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "mantissa of USARTDIV"] + pub const fn div_mantissa(&self) -> u16 { + let val = (self.0 >> 4usize) & 0x0fff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_div_mantissa(&mut self, val: u16) { + self.0 = (self.0 & !(0x0fff << 4usize)) | (((val as u32) & 0x0fff) << 4usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2Usart(pub u32); + impl Cr2Usart { + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x0f; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize); + } + #[doc = "lin break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "lin break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2Usart { + fn default() -> Cr2Usart { + Cr2Usart(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "Data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct SrUsart(pub u32); + impl SrUsart { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise error flag"] + pub const fn ne(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise error flag"] + pub fn set_ne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbd(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbd(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + } + impl Default for SrUsart { + fn default() -> SrUsart { + SrUsart(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3Usart(pub u32); + impl Cr3Usart { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + } + impl Default for Cr3Usart { + fn default() -> Cr3Usart { + Cr3Usart(0) + } + } + } +} +pub mod usart_v2 { + use crate::generic::*; + #[doc = "Universal synchronous asynchronous receiver transmitter"] + #[derive(Copy, Clone)] + pub struct Usart(pub *mut u8); + unsafe impl Send for Usart {} + unsafe impl Sync for Usart {} + impl Usart { + #[doc = "Control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "Control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "Control register 3"] + pub fn cr3(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "Baud rate register"] + pub fn brr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "Guard time and prescaler register"] + pub fn gtpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "Receiver timeout register"] + pub fn rtor(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "Request register"] + pub fn rqr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "Interrupt & status register"] + pub fn isr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "Interrupt flag clear register"] + pub fn icr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "Receive data register"] + pub fn rdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + #[doc = "Transmit data register"] + pub fn tdr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(40usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Datainv(pub u8); + impl Datainv { + #[doc = "Logical data from the data register are send/received in positive/direct logic"] + pub const POSITIVE: Self = Self(0); + #[doc = "Logical data from the data register are send/received in negative/inverse logic"] + pub const NEGATIVE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ovrdis(pub u8); + impl Ovrdis { + #[doc = "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] + pub const ENABLED: Self = Self(0); + #[doc = "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ddre(pub u8); + impl Ddre { + #[doc = "DMA is not disabled in case of reception error"] + pub const NOTDISABLED: Self = Self(0); + #[doc = "DMA is disabled following a reception error"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M0(pub u8); + impl M0 { + #[doc = "1 start bit, 8 data bits, n stop bits"] + pub const BIT8: Self = Self(0); + #[doc = "1 start bit, 9 data bits, n stop bits"] + pub const BIT9: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Onebit(pub u8); + impl Onebit { + #[doc = "Three sample bit method"] + pub const SAMPLE3: Self = Self(0); + #[doc = "One sample bit method"] + pub const SAMPLE1: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Txinv(pub u8); + impl Txinv { + #[doc = "TX pin signal works using the standard logic levels"] + pub const STANDARD: Self = Self(0); + #[doc = "TX pin signal values are inverted"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ps(pub u8); + impl Ps { + #[doc = "Even parity"] + pub const EVEN: Self = Self(0); + #[doc = "Odd parity"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Abrrq(pub u8); + impl Abrrq { + #[doc = "resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame"] + pub const REQUEST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dep(pub u8); + impl Dep { + #[doc = "DE signal is active high"] + pub const HIGH: Self = Self(0); + #[doc = "DE signal is active low"] + pub const LOW: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Over(pub u8); + impl Over { + #[doc = "Oversampling by 16"] + pub const OVERSAMPLING16: Self = Self(0); + #[doc = "Oversampling by 8"] + pub const OVERSAMPLING8: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxfrq(pub u8); + impl Rxfrq { + #[doc = "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"] + pub const DISCARD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wus(pub u8); + impl Wus { + #[doc = "WUF active on address match"] + pub const ADDRESS: Self = Self(0); + #[doc = "WuF active on Start bit detection"] + pub const START: Self = Self(0x02); + #[doc = "WUF active on RXNE"] + pub const RXNE: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "Steady low value on CK pin outside transmission window"] + pub const LOW: Self = Self(0); + #[doc = "Steady high value on CK pin outside transmission window"] + pub const HIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRST: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECOND: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Wake(pub u8); + impl Wake { + #[doc = "Idle line"] + pub const IDLE: Self = Self(0); + #[doc = "Address mask"] + pub const ADDRESS: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Irlp(pub u8); + impl Irlp { + #[doc = "Normal mode"] + pub const NORMAL: Self = Self(0); + #[doc = "Low-power mode"] + pub const LOWPOWER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Sbkrq(pub u8); + impl Sbkrq { + #[doc = "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] + pub const BREAK: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbcl(pub u8); + impl Lbcl { + #[doc = "The clock pulse of the last data bit is not output to the CK pin"] + pub const NOTOUTPUT: Self = Self(0); + #[doc = "The clock pulse of the last data bit is output to the CK pin"] + pub const OUTPUT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mmrq(pub u8); + impl Mmrq { + #[doc = "Puts the USART in mute mode and sets the RWU flag"] + pub const MUTE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Txfrq(pub u8); + impl Txfrq { + #[doc = "Set the TXE flags. This allows to discard the transmit data"] + pub const DISCARD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxinv(pub u8); + impl Rxinv { + #[doc = "RX pin signal works using the standard logic levels"] + pub const STANDARD: Self = Self(0); + #[doc = "RX pin signal values are inverted"] + pub const INVERTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct M1(pub u8); + impl M1 { + #[doc = "Use M0 to set the data bits"] + pub const M0: Self = Self(0); + #[doc = "1 start bit, 7 data bits, n stop bits"] + pub const BIT7: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Stop(pub u8); + impl Stop { + #[doc = "1 stop bit"] + pub const STOP1: Self = Self(0); + #[doc = "0.5 stop bit"] + pub const STOP0P5: Self = Self(0x01); + #[doc = "2 stop bit"] + pub const STOP2: Self = Self(0x02); + #[doc = "1.5 stop bit"] + pub const STOP1P5: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lbdl(pub u8); + impl Lbdl { + #[doc = "10-bit break detection"] + pub const BIT10: Self = Self(0); + #[doc = "11-bit break detection"] + pub const BIT11: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Addm(pub u8); + impl Addm { + #[doc = "4-bit address detection"] + pub const BIT4: Self = Self(0); + #[doc = "7-bit address detection"] + pub const BIT7: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Swap(pub u8); + impl Swap { + #[doc = "TX/RX pins are used as defined in standard pinout"] + pub const STANDARD: Self = Self(0); + #[doc = "The TX and RX pins functions are swapped"] + pub const SWAPPED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Hdsel(pub u8); + impl Hdsel { + #[doc = "Half duplex mode is not selected"] + pub const NOTSELECTED: Self = Self(0); + #[doc = "Half duplex mode is selected"] + pub const SELECTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Abrmod(pub u8); + impl Abrmod { + #[doc = "Measurement of the start bit is used to detect the baud rate"] + pub const START: Self = Self(0); + #[doc = "Falling edge to falling edge measurement"] + pub const EDGE: Self = Self(0x01); + #[doc = "0x7F frame detection"] + pub const FRAME7F: Self = Self(0x02); + #[doc = "0x55 frame detection"] + pub const FRAME55: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Msbfirst(pub u8); + impl Msbfirst { + #[doc = "data is transmitted/received with data bit 0 first, following the start bit"] + pub const LSB: Self = Self(0); + #[doc = "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] + pub const MSB: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "Guard time and prescaler register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Gtpr(pub u32); + impl Gtpr { + #[doc = "Prescaler value"] + pub const fn psc(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "Prescaler value"] + pub fn set_psc(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + #[doc = "Guard time value"] + pub const fn gt(&self) -> u8 { + let val = (self.0 >> 8usize) & 0xff; + val as u8 + } + #[doc = "Guard time value"] + pub fn set_gt(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize); + } + } + impl Default for Gtpr { + fn default() -> Gtpr { + Gtpr(0) + } + } + #[doc = "Receiver timeout register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rtor(pub u32); + impl Rtor { + #[doc = "Receiver timeout value"] + pub const fn rto(&self) -> u32 { + let val = (self.0 >> 0usize) & 0x00ff_ffff; + val as u32 + } + #[doc = "Receiver timeout value"] + pub fn set_rto(&mut self, val: u32) { + self.0 = + (self.0 & !(0x00ff_ffff << 0usize)) | (((val as u32) & 0x00ff_ffff) << 0usize); + } + #[doc = "Block Length"] + pub const fn blen(&self) -> u8 { + let val = (self.0 >> 24usize) & 0xff; + val as u8 + } + #[doc = "Block Length"] + pub fn set_blen(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize); + } + } + impl Default for Rtor { + fn default() -> Rtor { + Rtor(0) + } + } + #[doc = "Baud rate register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Brr(pub u32); + impl Brr { + #[doc = "mantissa of USARTDIV"] + pub const fn brr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "mantissa of USARTDIV"] + pub fn set_brr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Brr { + fn default() -> Brr { + Brr(0) + } + } + #[doc = "Data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "data value"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0x01ff; + val as u16 + } + #[doc = "data value"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0x01ff << 0usize)) | (((val as u32) & 0x01ff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "Control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "7-bit Address Detection/4-bit Address Detection"] + pub fn addm(&self, n: usize) -> super::vals::Addm { + assert!(n < 1usize); + let offs = 4usize + n * 0usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Addm(val as u8) + } + #[doc = "7-bit Address Detection/4-bit Address Detection"] + pub fn set_addm(&mut self, n: usize, val: super::vals::Addm) { + assert!(n < 1usize); + let offs = 4usize + n * 0usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "LIN break detection length"] + pub const fn lbdl(&self) -> super::vals::Lbdl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Lbdl(val as u8) + } + #[doc = "LIN break detection length"] + pub fn set_lbdl(&mut self, val: super::vals::Lbdl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "LIN break detection interrupt enable"] + pub const fn lbdie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection interrupt enable"] + pub fn set_lbdie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Last bit clock pulse"] + pub const fn lbcl(&self) -> super::vals::Lbcl { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Lbcl(val as u8) + } + #[doc = "Last bit clock pulse"] + pub fn set_lbcl(&mut self, val: super::vals::Lbcl) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); + } + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Clock enable"] + pub const fn clken(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Clock enable"] + pub fn set_clken(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "STOP bits"] + pub const fn stop(&self) -> super::vals::Stop { + let val = (self.0 >> 12usize) & 0x03; + super::vals::Stop(val as u8) + } + #[doc = "STOP bits"] + pub fn set_stop(&mut self, val: super::vals::Stop) { + self.0 = (self.0 & !(0x03 << 12usize)) | (((val.0 as u32) & 0x03) << 12usize); + } + #[doc = "LIN mode enable"] + pub const fn linen(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "LIN mode enable"] + pub fn set_linen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Swap TX/RX pins"] + pub const fn swap(&self) -> super::vals::Swap { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Swap(val as u8) + } + #[doc = "Swap TX/RX pins"] + pub fn set_swap(&mut self, val: super::vals::Swap) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "RX pin active level inversion"] + pub const fn rxinv(&self) -> super::vals::Rxinv { + let val = (self.0 >> 16usize) & 0x01; + super::vals::Rxinv(val as u8) + } + #[doc = "RX pin active level inversion"] + pub fn set_rxinv(&mut self, val: super::vals::Rxinv) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val.0 as u32) & 0x01) << 16usize); + } + #[doc = "TX pin active level inversion"] + pub const fn txinv(&self) -> super::vals::Txinv { + let val = (self.0 >> 17usize) & 0x01; + super::vals::Txinv(val as u8) + } + #[doc = "TX pin active level inversion"] + pub fn set_txinv(&mut self, val: super::vals::Txinv) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val.0 as u32) & 0x01) << 17usize); + } + #[doc = "Binary data inversion"] + pub const fn datainv(&self) -> super::vals::Datainv { + let val = (self.0 >> 18usize) & 0x01; + super::vals::Datainv(val as u8) + } + #[doc = "Binary data inversion"] + pub fn set_datainv(&mut self, val: super::vals::Datainv) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); + } + #[doc = "Most significant bit first"] + pub const fn msbfirst(&self) -> super::vals::Msbfirst { + let val = (self.0 >> 19usize) & 0x01; + super::vals::Msbfirst(val as u8) + } + #[doc = "Most significant bit first"] + pub fn set_msbfirst(&mut self, val: super::vals::Msbfirst) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); + } + #[doc = "Auto baud rate enable"] + pub const fn abren(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Auto baud rate enable"] + pub fn set_abren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "Auto baud rate mode"] + pub const fn abrmod(&self) -> super::vals::Abrmod { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Abrmod(val as u8) + } + #[doc = "Auto baud rate mode"] + pub fn set_abrmod(&mut self, val: super::vals::Abrmod) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); + } + #[doc = "Receiver timeout enable"] + pub const fn rtoen(&self) -> bool { + let val = (self.0 >> 23usize) & 0x01; + val != 0 + } + #[doc = "Receiver timeout enable"] + pub fn set_rtoen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize); + } + #[doc = "Address of the USART node"] + pub const fn add(&self) -> u8 { + let val = (self.0 >> 24usize) & 0xff; + val as u8 + } + #[doc = "Address of the USART node"] + pub fn set_add(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "Control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "USART enable"] + pub const fn ue(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "USART enable"] + pub fn set_ue(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "USART enable in Stop mode"] + pub const fn uesm(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "USART enable in Stop mode"] + pub fn set_uesm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Receiver enable"] + pub const fn re(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Receiver enable"] + pub fn set_re(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Transmitter enable"] + pub const fn te(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Transmitter enable"] + pub fn set_te(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "IDLE interrupt enable"] + pub const fn idleie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "IDLE interrupt enable"] + pub fn set_idleie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "RXNE interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "RXNE interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "PE interrupt enable"] + pub const fn peie(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "PE interrupt enable"] + pub fn set_peie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Parity selection"] + pub const fn ps(&self) -> super::vals::Ps { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Ps(val as u8) + } + #[doc = "Parity selection"] + pub fn set_ps(&mut self, val: super::vals::Ps) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Parity control enable"] + pub const fn pce(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "Parity control enable"] + pub fn set_pce(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Receiver wakeup method"] + pub const fn wake(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Receiver wakeup method"] + pub fn set_wake(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "Word length"] + pub const fn m0(&self) -> super::vals::M0 { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M0(val as u8) + } + #[doc = "Word length"] + pub fn set_m0(&mut self, val: super::vals::M0) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Word length"] + pub const fn m1(&self) -> super::vals::M1 { + let val = (self.0 >> 12usize) & 0x01; + super::vals::M1(val as u8) + } + #[doc = "Word length"] + pub fn set_m1(&mut self, val: super::vals::M1) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Mute mode enable"] + pub const fn mme(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Mute mode enable"] + pub fn set_mme(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Character match interrupt enable"] + pub const fn cmie(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Character match interrupt enable"] + pub fn set_cmie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Oversampling mode"] + pub fn over(&self, n: usize) -> super::vals::Over { + assert!(n < 1usize); + let offs = 15usize + n * 0usize; + let val = (self.0 >> offs) & 0x01; + super::vals::Over(val as u8) + } + #[doc = "Oversampling mode"] + pub fn set_over(&mut self, n: usize, val: super::vals::Over) { + assert!(n < 1usize); + let offs = 15usize + n * 0usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val.0 as u32) & 0x01) << offs); + } + #[doc = "Driver Enable deassertion time"] + pub const fn dedt(&self) -> u8 { + let val = (self.0 >> 16usize) & 0x1f; + val as u8 + } + #[doc = "Driver Enable deassertion time"] + pub fn set_dedt(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 16usize)) | (((val as u32) & 0x1f) << 16usize); + } + #[doc = "Driver Enable assertion time"] + pub const fn deat(&self) -> u8 { + let val = (self.0 >> 21usize) & 0x1f; + val as u8 + } + #[doc = "Driver Enable assertion time"] + pub fn set_deat(&mut self, val: u8) { + self.0 = (self.0 & !(0x1f << 21usize)) | (((val as u32) & 0x1f) << 21usize); + } + #[doc = "Receiver timeout interrupt enable"] + pub const fn rtoie(&self) -> bool { + let val = (self.0 >> 26usize) & 0x01; + val != 0 + } + #[doc = "Receiver timeout interrupt enable"] + pub fn set_rtoie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize); + } + #[doc = "End of Block interrupt enable"] + pub const fn eobie(&self) -> bool { + let val = (self.0 >> 27usize) & 0x01; + val != 0 + } + #[doc = "End of Block interrupt enable"] + pub fn set_eobie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "Interrupt & status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ixr(pub u32); + impl Ixr { + #[doc = "Parity error"] + pub const fn pe(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Parity error"] + pub fn set_pe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Framing error"] + pub const fn fe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Framing error"] + pub fn set_fe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Noise detected flag"] + pub const fn nf(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Noise detected flag"] + pub fn set_nf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Overrun error"] + pub const fn ore(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Overrun error"] + pub fn set_ore(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Idle line detected"] + pub const fn idle(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Idle line detected"] + pub fn set_idle(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Read data register not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Read data register not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Transmission complete"] + pub const fn tc(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Transmission complete"] + pub fn set_tc(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Transmit data register empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Transmit data register empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "LIN break detection flag"] + pub const fn lbdf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "LIN break detection flag"] + pub fn set_lbdf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS interrupt flag"] + pub const fn ctsif(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt flag"] + pub fn set_ctsif(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS flag"] + pub const fn cts(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS flag"] + pub fn set_cts(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "Receiver timeout"] + pub const fn rtof(&self) -> bool { + let val = (self.0 >> 11usize) & 0x01; + val != 0 + } + #[doc = "Receiver timeout"] + pub fn set_rtof(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize); + } + #[doc = "End of block flag"] + pub const fn eobf(&self) -> bool { + let val = (self.0 >> 12usize) & 0x01; + val != 0 + } + #[doc = "End of block flag"] + pub fn set_eobf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize); + } + #[doc = "Auto baud rate error"] + pub const fn abre(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Auto baud rate error"] + pub fn set_abre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Auto baud rate flag"] + pub const fn abrf(&self) -> bool { + let val = (self.0 >> 15usize) & 0x01; + val != 0 + } + #[doc = "Auto baud rate flag"] + pub fn set_abrf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize); + } + #[doc = "Busy flag"] + pub const fn busy(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_busy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "character match flag"] + pub const fn cmf(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "character match flag"] + pub fn set_cmf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Send break flag"] + pub const fn sbkf(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Send break flag"] + pub fn set_sbkf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Receiver wakeup from Mute mode"] + pub const fn rwu(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Receiver wakeup from Mute mode"] + pub fn set_rwu(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "Wakeup from Stop mode flag"] + pub const fn wuf(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "Wakeup from Stop mode flag"] + pub fn set_wuf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "Transmit enable acknowledge flag"] + pub const fn teack(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "Transmit enable acknowledge flag"] + pub fn set_teack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "Receive enable acknowledge flag"] + pub const fn reack(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Receive enable acknowledge flag"] + pub fn set_reack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + } + impl Default for Ixr { + fn default() -> Ixr { + Ixr(0) + } + } + #[doc = "Control register 3"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr3(pub u32); + impl Cr3 { + #[doc = "Error interrupt enable"] + pub const fn eie(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_eie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "IrDA mode enable"] + pub const fn iren(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "IrDA mode enable"] + pub fn set_iren(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "IrDA low-power"] + pub const fn irlp(&self) -> super::vals::Irlp { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Irlp(val as u8) + } + #[doc = "IrDA low-power"] + pub fn set_irlp(&mut self, val: super::vals::Irlp) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Half-duplex selection"] + pub const fn hdsel(&self) -> super::vals::Hdsel { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Hdsel(val as u8) + } + #[doc = "Half-duplex selection"] + pub fn set_hdsel(&mut self, val: super::vals::Hdsel) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Smartcard NACK enable"] + pub const fn nack(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Smartcard NACK enable"] + pub fn set_nack(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Smartcard mode enable"] + pub const fn scen(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Smartcard mode enable"] + pub fn set_scen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "DMA enable receiver"] + pub const fn dmar(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "DMA enable receiver"] + pub fn set_dmar(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "DMA enable transmitter"] + pub const fn dmat(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "DMA enable transmitter"] + pub fn set_dmat(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "RTS enable"] + pub const fn rtse(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "RTS enable"] + pub fn set_rtse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "CTS enable"] + pub const fn ctse(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "CTS enable"] + pub fn set_ctse(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "CTS interrupt enable"] + pub const fn ctsie(&self) -> bool { + let val = (self.0 >> 10usize) & 0x01; + val != 0 + } + #[doc = "CTS interrupt enable"] + pub fn set_ctsie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize); + } + #[doc = "One sample bit method enable"] + pub const fn onebit(&self) -> super::vals::Onebit { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Onebit(val as u8) + } + #[doc = "One sample bit method enable"] + pub fn set_onebit(&mut self, val: super::vals::Onebit) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "Overrun Disable"] + pub const fn ovrdis(&self) -> super::vals::Ovrdis { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Ovrdis(val as u8) + } + #[doc = "Overrun Disable"] + pub fn set_ovrdis(&mut self, val: super::vals::Ovrdis) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "DMA Disable on Reception Error"] + pub const fn ddre(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "DMA Disable on Reception Error"] + pub fn set_ddre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Driver enable mode"] + pub const fn dem(&self) -> bool { + let val = (self.0 >> 14usize) & 0x01; + val != 0 + } + #[doc = "Driver enable mode"] + pub fn set_dem(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize); + } + #[doc = "Driver enable polarity selection"] + pub const fn dep(&self) -> super::vals::Dep { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Dep(val as u8) + } + #[doc = "Driver enable polarity selection"] + pub fn set_dep(&mut self, val: super::vals::Dep) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "Smartcard auto-retry count"] + pub const fn scarcnt(&self) -> u8 { + let val = (self.0 >> 17usize) & 0x07; + val as u8 + } + #[doc = "Smartcard auto-retry count"] + pub fn set_scarcnt(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 17usize)) | (((val as u32) & 0x07) << 17usize); + } + #[doc = "Wakeup from Stop mode interrupt flag selection"] + pub const fn wus(&self) -> super::vals::Wus { + let val = (self.0 >> 20usize) & 0x03; + super::vals::Wus(val as u8) + } + #[doc = "Wakeup from Stop mode interrupt flag selection"] + pub fn set_wus(&mut self, val: super::vals::Wus) { + self.0 = (self.0 & !(0x03 << 20usize)) | (((val.0 as u32) & 0x03) << 20usize); + } + #[doc = "Wakeup from Stop mode interrupt enable"] + pub const fn wufie(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "Wakeup from Stop mode interrupt enable"] + pub fn set_wufie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + } + impl Default for Cr3 { + fn default() -> Cr3 { + Cr3(0) + } + } + #[doc = "Request register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rqr(pub u32); + impl Rqr { + #[doc = "Auto baud rate request"] + pub const fn abrrq(&self) -> super::vals::Abrrq { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Abrrq(val as u8) + } + #[doc = "Auto baud rate request"] + pub fn set_abrrq(&mut self, val: super::vals::Abrrq) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Send break request"] + pub const fn sbkrq(&self) -> super::vals::Sbkrq { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Sbkrq(val as u8) + } + #[doc = "Send break request"] + pub fn set_sbkrq(&mut self, val: super::vals::Sbkrq) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Mute mode request"] + pub const fn mmrq(&self) -> super::vals::Mmrq { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mmrq(val as u8) + } + #[doc = "Mute mode request"] + pub fn set_mmrq(&mut self, val: super::vals::Mmrq) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Receive data flush request"] + pub const fn rxfrq(&self) -> super::vals::Rxfrq { + let val = (self.0 >> 3usize) & 0x01; + super::vals::Rxfrq(val as u8) + } + #[doc = "Receive data flush request"] + pub fn set_rxfrq(&mut self, val: super::vals::Rxfrq) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val.0 as u32) & 0x01) << 3usize); + } + #[doc = "Transmit data flush request"] + pub const fn txfrq(&self) -> super::vals::Txfrq { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Txfrq(val as u8) + } + #[doc = "Transmit data flush request"] + pub fn set_txfrq(&mut self, val: super::vals::Txfrq) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + } + impl Default for Rqr { + fn default() -> Rqr { + Rqr(0) + } + } + } +} +pub mod spi_v1 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "TI frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "TI frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Data frame format"] + pub const fn dff(&self) -> super::vals::Dff { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Dff(val as u8) + } + #[doc = "Data frame format"] + pub fn set_dff(&mut self, val: super::vals::Dff) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dff(pub u8); + impl Dff { + #[doc = "8-bit data frame format is selected for transmission/reception"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit data frame format is selected for transmission/reception"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Iscfg(pub u8); + impl Iscfg { + #[doc = "Slave - transmit"] + pub const SLAVETX: Self = Self(0); + #[doc = "Slave - receive"] + pub const SLAVERX: Self = Self(0x01); + #[doc = "Master - transmit"] + pub const MASTERTX: Self = Self(0x02); + #[doc = "Master - receive"] + pub const MASTERRX: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + } +} +pub mod syscfg_l4 { + use crate::generic::*; + #[doc = "System configuration controller"] + #[derive(Copy, Clone)] + pub struct Syscfg(pub *mut u8); + unsafe impl Send for Syscfg {} + unsafe impl Sync for Syscfg {} + impl Syscfg { + #[doc = "memory remap register"] + pub fn memrmp(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "configuration register 1"] + pub fn cfgr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "external interrupt configuration register 1"] + pub fn exticr(self, n: usize) -> Reg { + assert!(n < 4usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "SCSR"] + pub fn scsr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + #[doc = "CFGR2"] + pub fn cfgr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(28usize)) } + } + #[doc = "SWPR"] + pub fn swpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(32usize)) } + } + #[doc = "SKR"] + pub fn skr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(36usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "CFGR2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr2(pub u32); + impl Cfgr2 { + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub const fn cll(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Cortex LOCKUP (Hardfault) output enable bit"] + pub fn set_cll(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 parity lock bit"] + pub const fn spl(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity lock bit"] + pub fn set_spl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "PVD lock enable bit"] + pub const fn pvdl(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "PVD lock enable bit"] + pub fn set_pvdl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "ECC Lock"] + pub const fn eccl(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "ECC Lock"] + pub fn set_eccl(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "SRAM2 parity error flag"] + pub const fn spf(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 parity error flag"] + pub fn set_spf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Cfgr2 { + fn default() -> Cfgr2 { + Cfgr2(0) + } + } + #[doc = "external interrupt configuration register 4"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Exticr(pub u32); + impl Exticr { + #[doc = "EXTI12 configuration bits"] + pub fn exti(&self, n: usize) -> u8 { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + let val = (self.0 >> offs) & 0x0f; + val as u8 + } + #[doc = "EXTI12 configuration bits"] + pub fn set_exti(&mut self, n: usize, val: u8) { + assert!(n < 4usize); + let offs = 0usize + n * 4usize; + self.0 = (self.0 & !(0x0f << offs)) | (((val as u32) & 0x0f) << offs); + } + } + impl Default for Exticr { + fn default() -> Exticr { + Exticr(0) + } + } + #[doc = "SWPR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Swpr(pub u32); + impl Swpr { + #[doc = "SRAWM2 write protection."] + pub fn pwp(&self, n: usize) -> bool { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "SRAWM2 write protection."] + pub fn set_pwp(&mut self, n: usize, val: bool) { + assert!(n < 32usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Swpr { + fn default() -> Swpr { + Swpr(0) + } + } + #[doc = "SKR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Skr(pub u32); + impl Skr { + #[doc = "SRAM2 write protection key for software erase"] + pub const fn key(&self) -> u8 { + let val = (self.0 >> 0usize) & 0xff; + val as u8 + } + #[doc = "SRAM2 write protection key for software erase"] + pub fn set_key(&mut self, val: u8) { + self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize); + } + } + impl Default for Skr { + fn default() -> Skr { + Skr(0) + } + } + #[doc = "memory remap register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Memrmp(pub u32); + impl Memrmp { + #[doc = "Memory mapping selection"] + pub const fn mem_mode(&self) -> u8 { + let val = (self.0 >> 0usize) & 0x07; + val as u8 + } + #[doc = "Memory mapping selection"] + pub fn set_mem_mode(&mut self, val: u8) { + self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize); + } + #[doc = "QUADSPI memory mapping swap"] + pub const fn qfs(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "QUADSPI memory mapping swap"] + pub fn set_qfs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Flash Bank mode selection"] + pub const fn fb_mode(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Flash Bank mode selection"] + pub fn set_fb_mode(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + } + impl Default for Memrmp { + fn default() -> Memrmp { + Memrmp(0) + } + } + #[doc = "configuration register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cfgr1(pub u32); + impl Cfgr1 { + #[doc = "Firewall disable"] + pub const fn fwdis(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Firewall disable"] + pub fn set_fwdis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "I/O analog switch voltage booster enable"] + pub const fn boosten(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "I/O analog switch voltage booster enable"] + pub fn set_boosten(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub const fn i2c_pb6_fmp(&self) -> bool { + let val = (self.0 >> 16usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB6"] + pub fn set_i2c_pb6_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub const fn i2c_pb7_fmp(&self) -> bool { + let val = (self.0 >> 17usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB7"] + pub fn set_i2c_pb7_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub const fn i2c_pb8_fmp(&self) -> bool { + let val = (self.0 >> 18usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB8"] + pub fn set_i2c_pb8_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize); + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub const fn i2c_pb9_fmp(&self) -> bool { + let val = (self.0 >> 19usize) & 0x01; + val != 0 + } + #[doc = "Fast-mode Plus (Fm+) driving capability activation on PB9"] + pub fn set_i2c_pb9_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize); + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub const fn i2c1_fmp(&self) -> bool { + let val = (self.0 >> 20usize) & 0x01; + val != 0 + } + #[doc = "I2C1 Fast-mode Plus driving capability activation"] + pub fn set_i2c1_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize); + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub const fn i2c2_fmp(&self) -> bool { + let val = (self.0 >> 21usize) & 0x01; + val != 0 + } + #[doc = "I2C2 Fast-mode Plus driving capability activation"] + pub fn set_i2c2_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize); + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub const fn i2c3_fmp(&self) -> bool { + let val = (self.0 >> 22usize) & 0x01; + val != 0 + } + #[doc = "I2C3 Fast-mode Plus driving capability activation"] + pub fn set_i2c3_fmp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize); + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub const fn fpu_ie(&self) -> u8 { + let val = (self.0 >> 26usize) & 0x3f; + val as u8 + } + #[doc = "Floating Point Unit interrupts enable bits"] + pub fn set_fpu_ie(&mut self, val: u8) { + self.0 = (self.0 & !(0x3f << 26usize)) | (((val as u32) & 0x3f) << 26usize); + } + } + impl Default for Cfgr1 { + fn default() -> Cfgr1 { + Cfgr1(0) + } + } + #[doc = "SCSR"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Scsr(pub u32); + impl Scsr { + #[doc = "SRAM2 Erase"] + pub const fn sram2er(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 Erase"] + pub fn set_sram2er(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "SRAM2 busy by erase operation"] + pub const fn sram2bsy(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "SRAM2 busy by erase operation"] + pub fn set_sram2bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + } + impl Default for Scsr { + fn default() -> Scsr { + Scsr(0) + } + } + } +} +pub mod rng_v1 { + use crate::generic::*; + #[doc = "Random number generator"] + #[derive(Copy, Clone)] + pub struct Rng(pub *mut u8); + unsafe impl Send for Rng {} + unsafe impl Sync for Rng {} + impl Rng { + #[doc = "control register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + } + pub mod regs { + use crate::generic::*; + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Data ready"] + pub const fn drdy(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Data ready"] + pub fn set_drdy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Clock error current status"] + pub const fn cecs(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Clock error current status"] + pub fn set_cecs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Seed error current status"] + pub const fn secs(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Seed error current status"] + pub fn set_secs(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Clock error interrupt status"] + pub const fn ceis(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Clock error interrupt status"] + pub fn set_ceis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Seed error interrupt status"] + pub const fn seis(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Seed error interrupt status"] + pub fn set_seis(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Random number generator enable"] + pub const fn rngen(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Random number generator enable"] + pub fn set_rngen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Interrupt enable"] + pub const fn ie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Interrupt enable"] + pub fn set_ie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + } +} +pub mod spi_v2 { + use crate::generic::*; + #[doc = "Serial peripheral interface"] + #[derive(Copy, Clone)] + pub struct Spi(pub *mut u8); + unsafe impl Send for Spi {} + unsafe impl Sync for Spi {} + impl Spi { + #[doc = "control register 1"] + pub fn cr1(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "control register 2"] + pub fn cr2(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "status register"] + pub fn sr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "data register"] + pub fn dr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "CRC polynomial register"] + pub fn crcpr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "RX CRC register"] + pub fn rxcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + #[doc = "TX CRC register"] + pub fn txcrcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ftlvlr(pub u8); + impl Ftlvlr { + #[doc = "Tx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Tx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Tx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Tx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcnext(pub u8); + impl Crcnext { + #[doc = "Next transmit value is from Tx buffer"] + pub const TXBUFFER: Self = Self(0); + #[doc = "Next transmit value is from Tx CRC register"] + pub const CRC: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Rxonly(pub u8); + impl Rxonly { + #[doc = "Full duplex (Transmit and receive)"] + pub const FULLDUPLEX: Self = Self(0); + #[doc = "Output disabled (Receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpol(pub u8); + impl Cpol { + #[doc = "CK to 0 when idle"] + pub const IDLELOW: Self = Self(0); + #[doc = "CK to 1 when idle"] + pub const IDLEHIGH: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frlvlr(pub u8); + impl Frlvlr { + #[doc = "Rx FIFO Empty"] + pub const EMPTY: Self = Self(0); + #[doc = "Rx 1/4 FIFO"] + pub const QUARTER: Self = Self(0x01); + #[doc = "Rx 1/2 FIFO"] + pub const HALF: Self = Self(0x02); + #[doc = "Rx FIFO full"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ds(pub u8); + impl Ds { + #[doc = "4-bit"] + pub const FOURBIT: Self = Self(0x03); + #[doc = "5-bit"] + pub const FIVEBIT: Self = Self(0x04); + #[doc = "6-bit"] + pub const SIXBIT: Self = Self(0x05); + #[doc = "7-bit"] + pub const SEVENBIT: Self = Self(0x06); + #[doc = "8-bit"] + pub const EIGHTBIT: Self = Self(0x07); + #[doc = "9-bit"] + pub const NINEBIT: Self = Self(0x08); + #[doc = "10-bit"] + pub const TENBIT: Self = Self(0x09); + #[doc = "11-bit"] + pub const ELEVENBIT: Self = Self(0x0a); + #[doc = "12-bit"] + pub const TWELVEBIT: Self = Self(0x0b); + #[doc = "13-bit"] + pub const THIRTEENBIT: Self = Self(0x0c); + #[doc = "14-bit"] + pub const FOURTEENBIT: Self = Self(0x0d); + #[doc = "15-bit"] + pub const FIFTEENBIT: Self = Self(0x0e); + #[doc = "16-bit"] + pub const SIXTEENBIT: Self = Self(0x0f); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaRx(pub u8); + impl LdmaRx { + #[doc = "Number of data to transfer for receive is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for receive is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Mstr(pub u8); + impl Mstr { + #[doc = "Slave configuration"] + pub const SLAVE: Self = Self(0); + #[doc = "Master configuration"] + pub const MASTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Crcl(pub u8); + impl Crcl { + #[doc = "8-bit CRC length"] + pub const EIGHTBIT: Self = Self(0); + #[doc = "16-bit CRC length"] + pub const SIXTEENBIT: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidioe(pub u8); + impl Bidioe { + #[doc = "Output disabled (receive-only mode)"] + pub const OUTPUTDISABLED: Self = Self(0); + #[doc = "Output enabled (transmit-only mode)"] + pub const OUTPUTENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frer(pub u8); + impl Frer { + #[doc = "No frame format error"] + pub const NOERROR: Self = Self(0); + #[doc = "A frame format error occurred"] + pub const ERROR: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Bidimode(pub u8); + impl Bidimode { + #[doc = "2-line unidirectional data mode selected"] + pub const UNIDIRECTIONAL: Self = Self(0); + #[doc = "1-line bidirectional data mode selected"] + pub const BIDIRECTIONAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Br(pub u8); + impl Br { + #[doc = "f_PCLK / 2"] + pub const DIV2: Self = Self(0); + #[doc = "f_PCLK / 4"] + pub const DIV4: Self = Self(0x01); + #[doc = "f_PCLK / 8"] + pub const DIV8: Self = Self(0x02); + #[doc = "f_PCLK / 16"] + pub const DIV16: Self = Self(0x03); + #[doc = "f_PCLK / 32"] + pub const DIV32: Self = Self(0x04); + #[doc = "f_PCLK / 64"] + pub const DIV64: Self = Self(0x05); + #[doc = "f_PCLK / 128"] + pub const DIV128: Self = Self(0x06); + #[doc = "f_PCLK / 256"] + pub const DIV256: Self = Self(0x07); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Cpha(pub u8); + impl Cpha { + #[doc = "The first clock transition is the first data capture edge"] + pub const FIRSTEDGE: Self = Self(0); + #[doc = "The second clock transition is the first data capture edge"] + pub const SECONDEDGE: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frxth(pub u8); + impl Frxth { + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] + pub const HALF: Self = Self(0); + #[doc = "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] + pub const QUARTER: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Frf(pub u8); + impl Frf { + #[doc = "SPI Motorola mode"] + pub const MOTOROLA: Self = Self(0); + #[doc = "SPI TI mode"] + pub const TI: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct LdmaTx(pub u8); + impl LdmaTx { + #[doc = "Number of data to transfer for transmit is even"] + pub const EVEN: Self = Self(0); + #[doc = "Number of data to transfer for transmit is odd"] + pub const ODD: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Lsbfirst(pub u8); + impl Lsbfirst { + #[doc = "Data is transmitted/received with the MSB first"] + pub const MSBFIRST: Self = Self(0); + #[doc = "Data is transmitted/received with the LSB first"] + pub const LSBFIRST: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "TX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Txcrcr(pub u32); + impl Txcrcr { + #[doc = "Tx CRC register"] + pub const fn tx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Tx CRC register"] + pub fn set_tx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Txcrcr { + fn default() -> Txcrcr { + Txcrcr(0) + } + } + #[doc = "RX CRC register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Rxcrcr(pub u32); + impl Rxcrcr { + #[doc = "Rx CRC register"] + pub const fn rx_crc(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Rx CRC register"] + pub fn set_rx_crc(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Rxcrcr { + fn default() -> Rxcrcr { + Rxcrcr(0) + } + } + #[doc = "status register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Sr(pub u32); + impl Sr { + #[doc = "Receive buffer not empty"] + pub const fn rxne(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Receive buffer not empty"] + pub fn set_rxne(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Transmit buffer empty"] + pub const fn txe(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Transmit buffer empty"] + pub fn set_txe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "CRC error flag"] + pub const fn crcerr(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "CRC error flag"] + pub fn set_crcerr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Mode fault"] + pub const fn modf(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Mode fault"] + pub fn set_modf(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "Overrun flag"] + pub const fn ovr(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "Overrun flag"] + pub fn set_ovr(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Busy flag"] + pub const fn bsy(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Busy flag"] + pub fn set_bsy(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Frame format error"] + pub const fn fre(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Frame format error"] + pub fn set_fre(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "FIFO reception level"] + pub const fn frlvl(&self) -> u8 { + let val = (self.0 >> 9usize) & 0x03; + val as u8 + } + #[doc = "FIFO reception level"] + pub fn set_frlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 9usize)) | (((val as u32) & 0x03) << 9usize); + } + #[doc = "FIFO Transmission Level"] + pub const fn ftlvl(&self) -> u8 { + let val = (self.0 >> 11usize) & 0x03; + val as u8 + } + #[doc = "FIFO Transmission Level"] + pub fn set_ftlvl(&mut self, val: u8) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize); + } + } + impl Default for Sr { + fn default() -> Sr { + Sr(0) + } + } + #[doc = "data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Dr(pub u32); + impl Dr { + #[doc = "Data register"] + pub const fn dr(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Data register"] + pub fn set_dr(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Dr { + fn default() -> Dr { + Dr(0) + } + } + #[doc = "control register 2"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr2(pub u32); + impl Cr2 { + #[doc = "Rx buffer DMA enable"] + pub const fn rxdmaen(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Rx buffer DMA enable"] + pub fn set_rxdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Tx buffer DMA enable"] + pub const fn txdmaen(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer DMA enable"] + pub fn set_txdmaen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "SS output enable"] + pub const fn ssoe(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "SS output enable"] + pub fn set_ssoe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "NSS pulse management"] + pub const fn nssp(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "NSS pulse management"] + pub fn set_nssp(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Frame format"] + pub const fn frf(&self) -> super::vals::Frf { + let val = (self.0 >> 4usize) & 0x01; + super::vals::Frf(val as u8) + } + #[doc = "Frame format"] + pub fn set_frf(&mut self, val: super::vals::Frf) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val.0 as u32) & 0x01) << 4usize); + } + #[doc = "Error interrupt enable"] + pub const fn errie(&self) -> bool { + let val = (self.0 >> 5usize) & 0x01; + val != 0 + } + #[doc = "Error interrupt enable"] + pub fn set_errie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize); + } + #[doc = "RX buffer not empty interrupt enable"] + pub const fn rxneie(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "RX buffer not empty interrupt enable"] + pub fn set_rxneie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Tx buffer empty interrupt enable"] + pub const fn txeie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "Tx buffer empty interrupt enable"] + pub fn set_txeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + #[doc = "Data size"] + pub const fn ds(&self) -> super::vals::Ds { + let val = (self.0 >> 8usize) & 0x0f; + super::vals::Ds(val as u8) + } + #[doc = "Data size"] + pub fn set_ds(&mut self, val: super::vals::Ds) { + self.0 = (self.0 & !(0x0f << 8usize)) | (((val.0 as u32) & 0x0f) << 8usize); + } + #[doc = "FIFO reception threshold"] + pub const fn frxth(&self) -> super::vals::Frxth { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Frxth(val as u8) + } + #[doc = "FIFO reception threshold"] + pub fn set_frxth(&mut self, val: super::vals::Frxth) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Last DMA transfer for reception"] + pub const fn ldma_rx(&self) -> super::vals::LdmaRx { + let val = (self.0 >> 13usize) & 0x01; + super::vals::LdmaRx(val as u8) + } + #[doc = "Last DMA transfer for reception"] + pub fn set_ldma_rx(&mut self, val: super::vals::LdmaRx) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val.0 as u32) & 0x01) << 13usize); + } + #[doc = "Last DMA transfer for transmission"] + pub const fn ldma_tx(&self) -> super::vals::LdmaTx { + let val = (self.0 >> 14usize) & 0x01; + super::vals::LdmaTx(val as u8) + } + #[doc = "Last DMA transfer for transmission"] + pub fn set_ldma_tx(&mut self, val: super::vals::LdmaTx) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + } + impl Default for Cr2 { + fn default() -> Cr2 { + Cr2(0) + } + } + #[doc = "control register 1"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr1(pub u32); + impl Cr1 { + #[doc = "Clock phase"] + pub const fn cpha(&self) -> super::vals::Cpha { + let val = (self.0 >> 0usize) & 0x01; + super::vals::Cpha(val as u8) + } + #[doc = "Clock phase"] + pub fn set_cpha(&mut self, val: super::vals::Cpha) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val.0 as u32) & 0x01) << 0usize); + } + #[doc = "Clock polarity"] + pub const fn cpol(&self) -> super::vals::Cpol { + let val = (self.0 >> 1usize) & 0x01; + super::vals::Cpol(val as u8) + } + #[doc = "Clock polarity"] + pub fn set_cpol(&mut self, val: super::vals::Cpol) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val.0 as u32) & 0x01) << 1usize); + } + #[doc = "Master selection"] + pub const fn mstr(&self) -> super::vals::Mstr { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Mstr(val as u8) + } + #[doc = "Master selection"] + pub fn set_mstr(&mut self, val: super::vals::Mstr) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "Baud rate control"] + pub const fn br(&self) -> super::vals::Br { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Br(val as u8) + } + #[doc = "Baud rate control"] + pub fn set_br(&mut self, val: super::vals::Br) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "SPI enable"] + pub const fn spe(&self) -> bool { + let val = (self.0 >> 6usize) & 0x01; + val != 0 + } + #[doc = "SPI enable"] + pub fn set_spe(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize); + } + #[doc = "Frame format"] + pub const fn lsbfirst(&self) -> super::vals::Lsbfirst { + let val = (self.0 >> 7usize) & 0x01; + super::vals::Lsbfirst(val as u8) + } + #[doc = "Frame format"] + pub fn set_lsbfirst(&mut self, val: super::vals::Lsbfirst) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val.0 as u32) & 0x01) << 7usize); + } + #[doc = "Internal slave select"] + pub const fn ssi(&self) -> bool { + let val = (self.0 >> 8usize) & 0x01; + val != 0 + } + #[doc = "Internal slave select"] + pub fn set_ssi(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize); + } + #[doc = "Software slave management"] + pub const fn ssm(&self) -> bool { + let val = (self.0 >> 9usize) & 0x01; + val != 0 + } + #[doc = "Software slave management"] + pub fn set_ssm(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize); + } + #[doc = "Receive only"] + pub const fn rxonly(&self) -> super::vals::Rxonly { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Rxonly(val as u8) + } + #[doc = "Receive only"] + pub fn set_rxonly(&mut self, val: super::vals::Rxonly) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "CRC length"] + pub const fn crcl(&self) -> super::vals::Crcl { + let val = (self.0 >> 11usize) & 0x01; + super::vals::Crcl(val as u8) + } + #[doc = "CRC length"] + pub fn set_crcl(&mut self, val: super::vals::Crcl) { + self.0 = (self.0 & !(0x01 << 11usize)) | (((val.0 as u32) & 0x01) << 11usize); + } + #[doc = "CRC transfer next"] + pub const fn crcnext(&self) -> super::vals::Crcnext { + let val = (self.0 >> 12usize) & 0x01; + super::vals::Crcnext(val as u8) + } + #[doc = "CRC transfer next"] + pub fn set_crcnext(&mut self, val: super::vals::Crcnext) { + self.0 = (self.0 & !(0x01 << 12usize)) | (((val.0 as u32) & 0x01) << 12usize); + } + #[doc = "Hardware CRC calculation enable"] + pub const fn crcen(&self) -> bool { + let val = (self.0 >> 13usize) & 0x01; + val != 0 + } + #[doc = "Hardware CRC calculation enable"] + pub fn set_crcen(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize); + } + #[doc = "Output enable in bidirectional mode"] + pub const fn bidioe(&self) -> super::vals::Bidioe { + let val = (self.0 >> 14usize) & 0x01; + super::vals::Bidioe(val as u8) + } + #[doc = "Output enable in bidirectional mode"] + pub fn set_bidioe(&mut self, val: super::vals::Bidioe) { + self.0 = (self.0 & !(0x01 << 14usize)) | (((val.0 as u32) & 0x01) << 14usize); + } + #[doc = "Bidirectional data mode enable"] + pub const fn bidimode(&self) -> super::vals::Bidimode { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Bidimode(val as u8) + } + #[doc = "Bidirectional data mode enable"] + pub fn set_bidimode(&mut self, val: super::vals::Bidimode) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + } + impl Default for Cr1 { + fn default() -> Cr1 { + Cr1(0) + } + } + #[doc = "CRC polynomial register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Crcpr(pub u32); + impl Crcpr { + #[doc = "CRC polynomial register"] + pub const fn crcpoly(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "CRC polynomial register"] + pub fn set_crcpoly(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Crcpr { + fn default() -> Crcpr { + Crcpr(0) + } + } + } +} +pub mod dma_v2 { + use crate::generic::*; + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + #[derive(Copy, Clone)] + pub struct St(pub *mut u8); + unsafe impl Send for St {} + unsafe impl Sync for St {} + impl St { + #[doc = "stream x configuration register"] + pub fn cr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(0usize)) } + } + #[doc = "stream x number of data register"] + pub fn ndtr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(4usize)) } + } + #[doc = "stream x peripheral address register"] + pub fn par(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(8usize)) } + } + #[doc = "stream x memory 0 address register"] + pub fn m0ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(12usize)) } + } + #[doc = "stream x memory 1 address register"] + pub fn m1ar(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(16usize)) } + } + #[doc = "stream x FIFO control register"] + pub fn fcr(self) -> Reg { + unsafe { Reg::from_ptr(self.0.add(20usize)) } + } + } + #[doc = "DMA controller"] + #[derive(Copy, Clone)] + pub struct Dma(pub *mut u8); + unsafe impl Send for Dma {} + unsafe impl Sync for Dma {} + impl Dma { + #[doc = "low interrupt status register"] + pub fn isr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(0usize + n * 4usize)) } + } + #[doc = "low interrupt flag clear register"] + pub fn ifcr(self, n: usize) -> Reg { + assert!(n < 2usize); + unsafe { Reg::from_ptr(self.0.add(8usize + n * 4usize)) } + } + #[doc = "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers"] + pub fn st(self, n: usize) -> St { + assert!(n < 8usize); + unsafe { St(self.0.add(16usize + n * 24usize)) } + } + } + pub mod vals { + use crate::generic::*; + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fs(pub u8); + impl Fs { + #[doc = "0 < fifo_level < 1/4"] + pub const QUARTER1: Self = Self(0); + #[doc = "1/4 <= fifo_level < 1/2"] + pub const QUARTER2: Self = Self(0x01); + #[doc = "1/2 <= fifo_level < 3/4"] + pub const QUARTER3: Self = Self(0x02); + #[doc = "3/4 <= fifo_level < full"] + pub const QUARTER4: Self = Self(0x03); + #[doc = "FIFO is empty"] + pub const EMPTY: Self = Self(0x04); + #[doc = "FIFO is full"] + pub const FULL: Self = Self(0x05); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pfctrl(pub u8); + impl Pfctrl { + #[doc = "The DMA is the flow controller"] + pub const DMA: Self = Self(0); + #[doc = "The peripheral is the flow controller"] + pub const PERIPHERAL: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pl(pub u8); + impl Pl { + #[doc = "Low"] + pub const LOW: Self = Self(0); + #[doc = "Medium"] + pub const MEDIUM: Self = Self(0x01); + #[doc = "High"] + pub const HIGH: Self = Self(0x02); + #[doc = "Very high"] + pub const VERYHIGH: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Size(pub u8); + impl Size { + #[doc = "Byte (8-bit)"] + pub const BITS8: Self = Self(0); + #[doc = "Half-word (16-bit)"] + pub const BITS16: Self = Self(0x01); + #[doc = "Word (32-bit)"] + pub const BITS32: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Circ(pub u8); + impl Circ { + #[doc = "Circular mode disabled"] + pub const DISABLED: Self = Self(0); + #[doc = "Circular mode enabled"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dmdis(pub u8); + impl Dmdis { + #[doc = "Direct mode is enabled"] + pub const ENABLED: Self = Self(0); + #[doc = "Direct mode is disabled"] + pub const DISABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dir(pub u8); + impl Dir { + #[doc = "Peripheral-to-memory"] + pub const PERIPHERALTOMEMORY: Self = Self(0); + #[doc = "Memory-to-peripheral"] + pub const MEMORYTOPERIPHERAL: Self = Self(0x01); + #[doc = "Memory-to-memory"] + pub const MEMORYTOMEMORY: Self = Self(0x02); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Fth(pub u8); + impl Fth { + #[doc = "1/4 full FIFO"] + pub const QUARTER: Self = Self(0); + #[doc = "1/2 full FIFO"] + pub const HALF: Self = Self(0x01); + #[doc = "3/4 full FIFO"] + pub const THREEQUARTERS: Self = Self(0x02); + #[doc = "Full FIFO"] + pub const FULL: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Inc(pub u8); + impl Inc { + #[doc = "Address pointer is fixed"] + pub const FIXED: Self = Self(0); + #[doc = "Address pointer is incremented after each data transfer"] + pub const INCREMENTED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Burst(pub u8); + impl Burst { + #[doc = "Single transfer"] + pub const SINGLE: Self = Self(0); + #[doc = "Incremental burst of 4 beats"] + pub const INCR4: Self = Self(0x01); + #[doc = "Incremental burst of 8 beats"] + pub const INCR8: Self = Self(0x02); + #[doc = "Incremental burst of 16 beats"] + pub const INCR16: Self = Self(0x03); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Pincos(pub u8); + impl Pincos { + #[doc = "The offset size for the peripheral address calculation is linked to the PSIZE"] + pub const PSIZE: Self = Self(0); + #[doc = "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] + pub const FIXED4: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Dbm(pub u8); + impl Dbm { + #[doc = "No buffer switching at the end of transfer"] + pub const DISABLED: Self = Self(0); + #[doc = "Memory target switched at the end of the DMA transfer"] + pub const ENABLED: Self = Self(0x01); + } + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)] + pub struct Ct(pub u8); + impl Ct { + #[doc = "The current target memory is Memory 0"] + pub const MEMORY0: Self = Self(0); + #[doc = "The current target memory is Memory 1"] + pub const MEMORY1: Self = Self(0x01); + } + } + pub mod regs { + use crate::generic::*; + #[doc = "stream x FIFO control register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Fcr(pub u32); + impl Fcr { + #[doc = "FIFO threshold selection"] + pub const fn fth(&self) -> super::vals::Fth { + let val = (self.0 >> 0usize) & 0x03; + super::vals::Fth(val as u8) + } + #[doc = "FIFO threshold selection"] + pub fn set_fth(&mut self, val: super::vals::Fth) { + self.0 = (self.0 & !(0x03 << 0usize)) | (((val.0 as u32) & 0x03) << 0usize); + } + #[doc = "Direct mode disable"] + pub const fn dmdis(&self) -> super::vals::Dmdis { + let val = (self.0 >> 2usize) & 0x01; + super::vals::Dmdis(val as u8) + } + #[doc = "Direct mode disable"] + pub fn set_dmdis(&mut self, val: super::vals::Dmdis) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val.0 as u32) & 0x01) << 2usize); + } + #[doc = "FIFO status"] + pub const fn fs(&self) -> super::vals::Fs { + let val = (self.0 >> 3usize) & 0x07; + super::vals::Fs(val as u8) + } + #[doc = "FIFO status"] + pub fn set_fs(&mut self, val: super::vals::Fs) { + self.0 = (self.0 & !(0x07 << 3usize)) | (((val.0 as u32) & 0x07) << 3usize); + } + #[doc = "FIFO error interrupt enable"] + pub const fn feie(&self) -> bool { + let val = (self.0 >> 7usize) & 0x01; + val != 0 + } + #[doc = "FIFO error interrupt enable"] + pub fn set_feie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize); + } + } + impl Default for Fcr { + fn default() -> Fcr { + Fcr(0) + } + } + #[doc = "stream x number of data register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ndtr(pub u32); + impl Ndtr { + #[doc = "Number of data items to transfer"] + pub const fn ndt(&self) -> u16 { + let val = (self.0 >> 0usize) & 0xffff; + val as u16 + } + #[doc = "Number of data items to transfer"] + pub fn set_ndt(&mut self, val: u16) { + self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize); + } + } + impl Default for Ndtr { + fn default() -> Ndtr { + Ndtr(0) + } + } + #[doc = "stream x configuration register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Cr(pub u32); + impl Cr { + #[doc = "Stream enable / flag stream ready when read low"] + pub const fn en(&self) -> bool { + let val = (self.0 >> 0usize) & 0x01; + val != 0 + } + #[doc = "Stream enable / flag stream ready when read low"] + pub fn set_en(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize); + } + #[doc = "Direct mode error interrupt enable"] + pub const fn dmeie(&self) -> bool { + let val = (self.0 >> 1usize) & 0x01; + val != 0 + } + #[doc = "Direct mode error interrupt enable"] + pub fn set_dmeie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize); + } + #[doc = "Transfer error interrupt enable"] + pub const fn teie(&self) -> bool { + let val = (self.0 >> 2usize) & 0x01; + val != 0 + } + #[doc = "Transfer error interrupt enable"] + pub fn set_teie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize); + } + #[doc = "Half transfer interrupt enable"] + pub const fn htie(&self) -> bool { + let val = (self.0 >> 3usize) & 0x01; + val != 0 + } + #[doc = "Half transfer interrupt enable"] + pub fn set_htie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize); + } + #[doc = "Transfer complete interrupt enable"] + pub const fn tcie(&self) -> bool { + let val = (self.0 >> 4usize) & 0x01; + val != 0 + } + #[doc = "Transfer complete interrupt enable"] + pub fn set_tcie(&mut self, val: bool) { + self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize); + } + #[doc = "Peripheral flow controller"] + pub const fn pfctrl(&self) -> super::vals::Pfctrl { + let val = (self.0 >> 5usize) & 0x01; + super::vals::Pfctrl(val as u8) + } + #[doc = "Peripheral flow controller"] + pub fn set_pfctrl(&mut self, val: super::vals::Pfctrl) { + self.0 = (self.0 & !(0x01 << 5usize)) | (((val.0 as u32) & 0x01) << 5usize); + } + #[doc = "Data transfer direction"] + pub const fn dir(&self) -> super::vals::Dir { + let val = (self.0 >> 6usize) & 0x03; + super::vals::Dir(val as u8) + } + #[doc = "Data transfer direction"] + pub fn set_dir(&mut self, val: super::vals::Dir) { + self.0 = (self.0 & !(0x03 << 6usize)) | (((val.0 as u32) & 0x03) << 6usize); + } + #[doc = "Circular mode"] + pub const fn circ(&self) -> super::vals::Circ { + let val = (self.0 >> 8usize) & 0x01; + super::vals::Circ(val as u8) + } + #[doc = "Circular mode"] + pub fn set_circ(&mut self, val: super::vals::Circ) { + self.0 = (self.0 & !(0x01 << 8usize)) | (((val.0 as u32) & 0x01) << 8usize); + } + #[doc = "Peripheral increment mode"] + pub const fn pinc(&self) -> super::vals::Inc { + let val = (self.0 >> 9usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Peripheral increment mode"] + pub fn set_pinc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 9usize)) | (((val.0 as u32) & 0x01) << 9usize); + } + #[doc = "Memory increment mode"] + pub const fn minc(&self) -> super::vals::Inc { + let val = (self.0 >> 10usize) & 0x01; + super::vals::Inc(val as u8) + } + #[doc = "Memory increment mode"] + pub fn set_minc(&mut self, val: super::vals::Inc) { + self.0 = (self.0 & !(0x01 << 10usize)) | (((val.0 as u32) & 0x01) << 10usize); + } + #[doc = "Peripheral data size"] + pub const fn psize(&self) -> super::vals::Size { + let val = (self.0 >> 11usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Peripheral data size"] + pub fn set_psize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 11usize)) | (((val.0 as u32) & 0x03) << 11usize); + } + #[doc = "Memory data size"] + pub const fn msize(&self) -> super::vals::Size { + let val = (self.0 >> 13usize) & 0x03; + super::vals::Size(val as u8) + } + #[doc = "Memory data size"] + pub fn set_msize(&mut self, val: super::vals::Size) { + self.0 = (self.0 & !(0x03 << 13usize)) | (((val.0 as u32) & 0x03) << 13usize); + } + #[doc = "Peripheral increment offset size"] + pub const fn pincos(&self) -> super::vals::Pincos { + let val = (self.0 >> 15usize) & 0x01; + super::vals::Pincos(val as u8) + } + #[doc = "Peripheral increment offset size"] + pub fn set_pincos(&mut self, val: super::vals::Pincos) { + self.0 = (self.0 & !(0x01 << 15usize)) | (((val.0 as u32) & 0x01) << 15usize); + } + #[doc = "Priority level"] + pub const fn pl(&self) -> super::vals::Pl { + let val = (self.0 >> 16usize) & 0x03; + super::vals::Pl(val as u8) + } + #[doc = "Priority level"] + pub fn set_pl(&mut self, val: super::vals::Pl) { + self.0 = (self.0 & !(0x03 << 16usize)) | (((val.0 as u32) & 0x03) << 16usize); + } + #[doc = "Double buffer mode"] + pub const fn dbm(&self) -> super::vals::Dbm { + let val = (self.0 >> 18usize) & 0x01; + super::vals::Dbm(val as u8) + } + #[doc = "Double buffer mode"] + pub fn set_dbm(&mut self, val: super::vals::Dbm) { + self.0 = (self.0 & !(0x01 << 18usize)) | (((val.0 as u32) & 0x01) << 18usize); + } + #[doc = "Current target (only in double buffer mode)"] + pub const fn ct(&self) -> super::vals::Ct { + let val = (self.0 >> 19usize) & 0x01; + super::vals::Ct(val as u8) + } + #[doc = "Current target (only in double buffer mode)"] + pub fn set_ct(&mut self, val: super::vals::Ct) { + self.0 = (self.0 & !(0x01 << 19usize)) | (((val.0 as u32) & 0x01) << 19usize); + } + #[doc = "Peripheral burst transfer configuration"] + pub const fn pburst(&self) -> super::vals::Burst { + let val = (self.0 >> 21usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Peripheral burst transfer configuration"] + pub fn set_pburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 21usize)) | (((val.0 as u32) & 0x03) << 21usize); + } + #[doc = "Memory burst transfer configuration"] + pub const fn mburst(&self) -> super::vals::Burst { + let val = (self.0 >> 23usize) & 0x03; + super::vals::Burst(val as u8) + } + #[doc = "Memory burst transfer configuration"] + pub fn set_mburst(&mut self, val: super::vals::Burst) { + self.0 = (self.0 & !(0x03 << 23usize)) | (((val.0 as u32) & 0x03) << 23usize); + } + #[doc = "Channel selection"] + pub const fn chsel(&self) -> u8 { + let val = (self.0 >> 25usize) & 0x0f; + val as u8 + } + #[doc = "Channel selection"] + pub fn set_chsel(&mut self, val: u8) { + self.0 = (self.0 & !(0x0f << 25usize)) | (((val as u32) & 0x0f) << 25usize); + } + } + impl Default for Cr { + fn default() -> Cr { + Cr(0) + } + } + #[doc = "interrupt register"] + #[repr(transparent)] + #[derive(Copy, Clone, Eq, PartialEq)] + pub struct Ixr(pub u32); + impl Ixr { + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn feif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x FIFO error interrupt flag (x=3..0)"] + pub fn set_feif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 0usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn dmeif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x direct mode error interrupt flag (x=3..0)"] + pub fn set_dmeif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 2usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn teif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer error interrupt flag (x=3..0)"] + pub fn set_teif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 3usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn htif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x half transfer interrupt flag (x=3..0)"] + pub fn set_htif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 4usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn tcif(&self, n: usize) -> bool { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Stream x transfer complete interrupt flag (x = 3..0)"] + pub fn set_tcif(&mut self, n: usize, val: bool) { + assert!(n < 4usize); + let offs = 5usize + ([0usize, 6usize, 16usize, 22usize][n] as usize); + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } + } + impl Default for Ixr { + fn default() -> Ixr { + Ixr(0) + } + } + } +} diff --git a/embassy-stm32/src/pac/stm32f401cb.rs b/embassy-stm32/src/pac/stm32f401cb.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cb.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401cc.rs b/embassy-stm32/src/pac/stm32f401cc.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cc.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401cd.rs b/embassy-stm32/src/pac/stm32f401cd.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401cd.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401ce.rs b/embassy-stm32/src/pac/stm32f401ce.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401ce.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rb.rs b/embassy-stm32/src/pac/stm32f401rb.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rb.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rc.rs b/embassy-stm32/src/pac/stm32f401rc.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rc.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401rd.rs b/embassy-stm32/src/pac/stm32f401rd.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401rd.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401re.rs b/embassy-stm32/src/pac/stm32f401re.rs new file mode 100644 index 00000000..cf1a81cf --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401re.rs @@ -0,0 +1,532 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vb.rs b/embassy-stm32/src/pac/stm32f401vb.rs new file mode 100644 index 00000000..e14efa82 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vb.rs @@ -0,0 +1,540 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vc.rs b/embassy-stm32/src/pac/stm32f401vc.rs new file mode 100644 index 00000000..e14efa82 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vc.rs @@ -0,0 +1,540 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401vd.rs b/embassy-stm32/src/pac/stm32f401vd.rs new file mode 100644 index 00000000..e14efa82 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401vd.rs @@ -0,0 +1,540 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f401ve.rs b/embassy-stm32/src/pac/stm32f401ve.rs new file mode 100644 index 00000000..e14efa82 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f401ve.rs @@ -0,0 +1,540 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405oe.rs b/embassy-stm32/src/pac/stm32f405oe.rs new file mode 100644 index 00000000..db3aaf80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405oe.rs @@ -0,0 +1,685 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405og.rs b/embassy-stm32/src/pac/stm32f405og.rs new file mode 100644 index 00000000..db3aaf80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405og.rs @@ -0,0 +1,685 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405rg.rs b/embassy-stm32/src/pac/stm32f405rg.rs new file mode 100644 index 00000000..db3aaf80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405rg.rs @@ -0,0 +1,685 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405vg.rs b/embassy-stm32/src/pac/stm32f405vg.rs new file mode 100644 index 00000000..db3aaf80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405vg.rs @@ -0,0 +1,685 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f405zg.rs b/embassy-stm32/src/pac/stm32f405zg.rs new file mode 100644 index 00000000..db3aaf80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f405zg.rs @@ -0,0 +1,685 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ie.rs b/embassy-stm32/src/pac/stm32f407ie.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ie.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ig.rs b/embassy-stm32/src/pac/stm32f407ig.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ig.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ve.rs b/embassy-stm32/src/pac/stm32f407ve.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ve.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407vg.rs b/embassy-stm32/src/pac/stm32f407vg.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407vg.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407ze.rs b/embassy-stm32/src/pac/stm32f407ze.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407ze.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f407zg.rs b/embassy-stm32/src/pac/stm32f407zg.rs new file mode 100644 index 00000000..8c0d1cc6 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f407zg.rs @@ -0,0 +1,694 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410c8.rs b/embassy-stm32/src/pac/stm32f410c8.rs new file mode 100644 index 00000000..e664c681 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410c8.rs @@ -0,0 +1,470 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410cb.rs b/embassy-stm32/src/pac/stm32f410cb.rs new file mode 100644 index 00000000..e664c681 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410cb.rs @@ -0,0 +1,470 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410r8.rs b/embassy-stm32/src/pac/stm32f410r8.rs new file mode 100644 index 00000000..e664c681 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410r8.rs @@ -0,0 +1,470 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410rb.rs b/embassy-stm32/src/pac/stm32f410rb.rs new file mode 100644 index 00000000..e664c681 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410rb.rs @@ -0,0 +1,470 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410t8.rs b/embassy-stm32/src/pac/stm32f410t8.rs new file mode 100644 index 00000000..16d91e9e --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410t8.rs @@ -0,0 +1,454 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f410tb.rs b/embassy-stm32/src/pac/stm32f410tb.rs new file mode 100644 index 00000000..16d91e9e --- /dev/null +++ b/embassy-stm32/src/pac/stm32f410tb.rs @@ -0,0 +1,454 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x40080000 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + LPTIM1 = 97, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP = 25, + TIM5 = 50, + TIM6_DAC = 54, + USART1 = 37, + USART2 = 38, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(LPTIM1); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(USART1); + declare!(USART2); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn LPTIM1(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP(); + fn TIM5(); + fn TIM6_DAC(); + fn USART1(); + fn USART2(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 98] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411cc.rs b/embassy-stm32/src/pac/stm32f411cc.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411cc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411ce.rs b/embassy-stm32/src/pac/stm32f411ce.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411ce.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411rc.rs b/embassy-stm32/src/pac/stm32f411rc.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411rc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411re.rs b/embassy-stm32/src/pac/stm32f411re.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411re.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411vc.rs b/embassy-stm32/src/pac/stm32f411vc.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411vc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f411ve.rs b/embassy-stm32/src/pac/stm32f411ve.rs new file mode 100644 index 00000000..06edeb32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f411ve.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + USART1 = 37, + USART2 = 38, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(USART1); + declare!(USART2); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn USART1(); + fn USART2(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 86] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ce.rs b/embassy-stm32/src/pac/stm32f412ce.rs new file mode 100644 index 00000000..ef966fef --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ce.rs @@ -0,0 +1,608 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, + SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412cg.rs b/embassy-stm32/src/pac/stm32f412cg.rs new file mode 100644 index 00000000..ef966fef --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412cg.rs @@ -0,0 +1,608 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, + SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412re.rs b/embassy-stm32/src/pac/stm32f412re.rs new file mode 100644 index 00000000..12b3976d --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412re.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, + USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412rg.rs b/embassy-stm32/src/pac/stm32f412rg.rs new file mode 100644 index 00000000..12b3976d --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412rg.rs @@ -0,0 +1,641 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, + USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ve.rs b/embassy-stm32/src/pac/stm32f412ve.rs new file mode 100644 index 00000000..adcb48bc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ve.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412vg.rs b/embassy-stm32/src/pac/stm32f412vg.rs new file mode 100644 index 00000000..adcb48bc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412vg.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412ze.rs b/embassy-stm32/src/pac/stm32f412ze.rs new file mode 100644 index 00000000..adcb48bc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412ze.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f412zg.rs b/embassy-stm32/src/pac/stm32f412zg.rs new file mode 100644 index 00000000..adcb48bc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f412zg.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6 = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413cg.rs b/embassy-stm32/src/pac/stm32f413cg.rs new file mode 100644 index 00000000..6ed0d350 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413cg.rs @@ -0,0 +1,761 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413ch.rs b/embassy-stm32/src/pac/stm32f413ch.rs new file mode 100644 index 00000000..6ed0d350 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413ch.rs @@ -0,0 +1,761 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413mg.rs b/embassy-stm32/src/pac/stm32f413mg.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413mg.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413mh.rs b/embassy-stm32/src/pac/stm32f413mh.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413mh.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413rg.rs b/embassy-stm32/src/pac/stm32f413rg.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413rg.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413rh.rs b/embassy-stm32/src/pac/stm32f413rh.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413rh.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413vg.rs b/embassy-stm32/src/pac/stm32f413vg.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413vg.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413vh.rs b/embassy-stm32/src/pac/stm32f413vh.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413vh.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413zg.rs b/embassy-stm32/src/pac/stm32f413zg.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413zg.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f413zh.rs b/embassy-stm32/src/pac/stm32f413zh.rs new file mode 100644 index 00000000..690fb527 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f413zh.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415og.rs b/embassy-stm32/src/pac/stm32f415og.rs new file mode 100644 index 00000000..92a3a71a --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415og.rs @@ -0,0 +1,688 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415rg.rs b/embassy-stm32/src/pac/stm32f415rg.rs new file mode 100644 index 00000000..92a3a71a --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415rg.rs @@ -0,0 +1,688 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415vg.rs b/embassy-stm32/src/pac/stm32f415vg.rs new file mode 100644 index 00000000..92a3a71a --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415vg.rs @@ -0,0 +1,688 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f415zg.rs b/embassy-stm32/src/pac/stm32f415zg.rs new file mode 100644 index 00000000..92a3a71a --- /dev/null +++ b/embassy-stm32/src/pac/stm32f415zg.rs @@ -0,0 +1,688 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _reserved: 0 }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ie.rs b/embassy-stm32/src/pac/stm32f417ie.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ie.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ig.rs b/embassy-stm32/src/pac/stm32f417ig.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ig.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ve.rs b/embassy-stm32/src/pac/stm32f417ve.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ve.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417vg.rs b/embassy-stm32/src/pac/stm32f417vg.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417vg.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417ze.rs b/embassy-stm32/src/pac/stm32f417ze.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417ze.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f417zg.rs b/embassy-stm32/src/pac/stm32f417zg.rs new file mode 100644 index 00000000..3db62128 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f417zg.rs @@ -0,0 +1,697 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + FSMC = 48, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(FSMC); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn FSMC(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FSMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423ch.rs b/embassy-stm32/src/pac/stm32f423ch.rs new file mode 100644 index 00000000..03601799 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423ch.rs @@ -0,0 +1,764 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423mh.rs b/embassy-stm32/src/pac/stm32f423mh.rs new file mode 100644 index 00000000..d21c2a7c --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423mh.rs @@ -0,0 +1,781 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423rh.rs b/embassy-stm32/src/pac/stm32f423rh.rs new file mode 100644 index 00000000..d21c2a7c --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423rh.rs @@ -0,0 +1,781 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423vh.rs b/embassy-stm32/src/pac/stm32f423vh.rs new file mode 100644 index 00000000..d21c2a7c --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423vh.rs @@ -0,0 +1,781 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f423zh.rs b/embassy-stm32/src/pac/stm32f423zh.rs new file mode 100644 index 00000000..d21c2a7c --- /dev/null +++ b/embassy-stm32/src/pac/stm32f423zh.rs @@ -0,0 +1,781 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, MosiPin, PA10, 5); +impl_spi_pin!(SPI2, MisoPin, PA12, 5); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB12, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MosiPin, PA1, 5); +impl_spi_pin!(SPI4, MisoPin, PA11, 6); +impl_spi_pin!(SPI4, SckPin, PB13, 6); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PA10, 6); +impl_spi_pin!(SPI5, MisoPin, PA12, 6); +impl_spi_pin!(SPI5, SckPin, PB0, 6); +impl_spi_pin!(SPI5, MosiPin, PB8, 6); +impl_spi_pin!(SPI5, SckPin, PE12, 6); +impl_spi_pin!(SPI5, MisoPin, PE13, 6); +impl_spi_pin!(SPI5, MosiPin, PE14, 6); +impl_spi_pin!(SPI5, SckPin, PE2, 6); +impl_spi_pin!(SPI5, MisoPin, PE5, 6); +impl_spi_pin!(SPI5, MosiPin, PE6, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, TxPin, PA15, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RxPin, PB3, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 8); +impl_usart_pin!(USART3, CtsPin, PB13, 8); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PA11, 8); +impl_usart_pin!(USART6, RxPin, PA12, 8); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, + USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CAN3_RX0 = 75, + CAN3_RX1 = 76, + CAN3_SCE = 77, + CAN3_TX = 74, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM2_FLT0 = 98, + DFSDM2_FLT1 = 99, + DFSDM2_FLT2 = 100, + DFSDM2_FLT3 = 101, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 97, + OTG_FS = 67, + OTG_FS_WKUP = 42, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART10 = 89, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 88, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CAN3_RX0); + declare!(CAN3_RX1); + declare!(CAN3_SCE); + declare!(CAN3_TX); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM2_FLT0); + declare!(DFSDM2_FLT1); + declare!(DFSDM2_FLT2); + declare!(DFSDM2_FLT3); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART10); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CAN3_RX0(); + fn CAN3_RX1(); + fn CAN3_SCE(); + fn CAN3_TX(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM2_FLT0(); + fn DFSDM2_FLT1(); + fn DFSDM2_FLT2(); + fn DFSDM2_FLT3(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART10(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 102] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _reserved: 0 }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: CAN3_TX }, + Vector { _handler: CAN3_RX0 }, + Vector { _handler: CAN3_RX1 }, + Vector { _handler: CAN3_SCE }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _handler: UART9 }, + Vector { _handler: UART10 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: QUADSPI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + Vector { _handler: LPTIM1 }, + Vector { + _handler: DFSDM2_FLT0, + }, + Vector { + _handler: DFSDM2_FLT1, + }, + Vector { + _handler: DFSDM2_FLT2, + }, + Vector { + _handler: DFSDM2_FLT3, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ag.rs b/embassy-stm32/src/pac/stm32f427ag.rs new file mode 100644 index 00000000..5b239485 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ag.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ai.rs b/embassy-stm32/src/pac/stm32f427ai.rs new file mode 100644 index 00000000..5b239485 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ai.rs @@ -0,0 +1,778 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ig.rs b/embassy-stm32/src/pac/stm32f427ig.rs new file mode 100644 index 00000000..1f93ac32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ig.rs @@ -0,0 +1,783 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427ii.rs b/embassy-stm32/src/pac/stm32f427ii.rs new file mode 100644 index 00000000..1f93ac32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427ii.rs @@ -0,0 +1,783 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427vg.rs b/embassy-stm32/src/pac/stm32f427vg.rs new file mode 100644 index 00000000..fc277ee8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427vg.rs @@ -0,0 +1,770 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427vi.rs b/embassy-stm32/src/pac/stm32f427vi.rs new file mode 100644 index 00000000..fc277ee8 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427vi.rs @@ -0,0 +1,770 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427zg.rs b/embassy-stm32/src/pac/stm32f427zg.rs new file mode 100644 index 00000000..1f93ac32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427zg.rs @@ -0,0 +1,783 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f427zi.rs b/embassy-stm32/src/pac/stm32f427zi.rs new file mode 100644 index 00000000..1f93ac32 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f427zi.rs @@ -0,0 +1,783 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ag.rs b/embassy-stm32/src/pac/stm32f429ag.rs new file mode 100644 index 00000000..3c152fe9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ag.rs @@ -0,0 +1,784 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ai.rs b/embassy-stm32/src/pac/stm32f429ai.rs new file mode 100644 index 00000000..3c152fe9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ai.rs @@ -0,0 +1,784 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429be.rs b/embassy-stm32/src/pac/stm32f429be.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429be.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429bg.rs b/embassy-stm32/src/pac/stm32f429bg.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429bg.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429bi.rs b/embassy-stm32/src/pac/stm32f429bi.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429bi.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ie.rs b/embassy-stm32/src/pac/stm32f429ie.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ie.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ig.rs b/embassy-stm32/src/pac/stm32f429ig.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ig.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ii.rs b/embassy-stm32/src/pac/stm32f429ii.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ii.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ne.rs b/embassy-stm32/src/pac/stm32f429ne.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ne.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ng.rs b/embassy-stm32/src/pac/stm32f429ng.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ng.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ni.rs b/embassy-stm32/src/pac/stm32f429ni.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ni.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ve.rs b/embassy-stm32/src/pac/stm32f429ve.rs new file mode 100644 index 00000000..a47d2b4f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ve.rs @@ -0,0 +1,776 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429vg.rs b/embassy-stm32/src/pac/stm32f429vg.rs new file mode 100644 index 00000000..a47d2b4f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429vg.rs @@ -0,0 +1,776 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429vi.rs b/embassy-stm32/src/pac/stm32f429vi.rs new file mode 100644 index 00000000..a47d2b4f --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429vi.rs @@ -0,0 +1,776 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429ze.rs b/embassy-stm32/src/pac/stm32f429ze.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429ze.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429zg.rs b/embassy-stm32/src/pac/stm32f429zg.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429zg.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f429zi.rs b/embassy-stm32/src/pac/stm32f429zi.rs new file mode 100644 index 00000000..ff31c6c5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f429zi.rs @@ -0,0 +1,789 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ai.rs b/embassy-stm32/src/pac/stm32f437ai.rs new file mode 100644 index 00000000..7c95ba7a --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ai.rs @@ -0,0 +1,781 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ig.rs b/embassy-stm32/src/pac/stm32f437ig.rs new file mode 100644 index 00000000..31688d50 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ig.rs @@ -0,0 +1,786 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437ii.rs b/embassy-stm32/src/pac/stm32f437ii.rs new file mode 100644 index 00000000..31688d50 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437ii.rs @@ -0,0 +1,786 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437vg.rs b/embassy-stm32/src/pac/stm32f437vg.rs new file mode 100644 index 00000000..800c6e61 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437vg.rs @@ -0,0 +1,773 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437vi.rs b/embassy-stm32/src/pac/stm32f437vi.rs new file mode 100644 index 00000000..800c6e61 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437vi.rs @@ -0,0 +1,773 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437zg.rs b/embassy-stm32/src/pac/stm32f437zg.rs new file mode 100644 index 00000000..31688d50 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437zg.rs @@ -0,0 +1,786 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f437zi.rs b/embassy-stm32/src/pac/stm32f437zi.rs new file mode 100644 index 00000000..31688d50 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f437zi.rs @@ -0,0 +1,786 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ai.rs b/embassy-stm32/src/pac/stm32f439ai.rs new file mode 100644 index 00000000..10f4cb27 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ai.rs @@ -0,0 +1,787 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439bg.rs b/embassy-stm32/src/pac/stm32f439bg.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439bg.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439bi.rs b/embassy-stm32/src/pac/stm32f439bi.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439bi.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ig.rs b/embassy-stm32/src/pac/stm32f439ig.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ig.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ii.rs b/embassy-stm32/src/pac/stm32f439ii.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ii.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ng.rs b/embassy-stm32/src/pac/stm32f439ng.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ng.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439ni.rs b/embassy-stm32/src/pac/stm32f439ni.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439ni.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439vg.rs b/embassy-stm32/src/pac/stm32f439vg.rs new file mode 100644 index 00000000..eee391ec --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439vg.rs @@ -0,0 +1,779 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439vi.rs b/embassy-stm32/src/pac/stm32f439vi.rs new file mode 100644 index 00000000..eee391ec --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439vi.rs @@ -0,0 +1,779 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439zg.rs b/embassy-stm32/src/pac/stm32f439zg.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439zg.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f439zi.rs b/embassy-stm32/src/pac/stm32f439zi.rs new file mode 100644 index 00000000..9d7edc86 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f439zi.rs @@ -0,0 +1,792 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _); +impl_spi!(SPI5, APB2); +impl_spi_pin!(SPI5, MosiPin, PF11, 5); +impl_spi_pin!(SPI5, SckPin, PF7, 5); +impl_spi_pin!(SPI5, MisoPin, PF8, 5); +impl_spi_pin!(SPI5, MosiPin, PF9, 5); +impl_spi_pin!(SPI5, SckPin, PH6, 5); +impl_spi_pin!(SPI5, MisoPin, PH7, 5); +pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _); +impl_spi!(SPI6, APB2); +impl_spi_pin!(SPI6, MisoPin, PG12, 5); +impl_spi_pin!(SPI6, SckPin, PG13, 5); +impl_spi_pin!(SPI6, MosiPin, PG14, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446mc.rs b/embassy-stm32/src/pac/stm32f446mc.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446mc.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446me.rs b/embassy-stm32/src/pac/stm32f446me.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446me.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446rc.rs b/embassy-stm32/src/pac/stm32f446rc.rs new file mode 100644 index 00000000..64fc1dbb --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446rc.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446re.rs b/embassy-stm32/src/pac/stm32f446re.rs new file mode 100644 index 00000000..64fc1dbb --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446re.rs @@ -0,0 +1,714 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446vc.rs b/embassy-stm32/src/pac/stm32f446vc.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446vc.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446ve.rs b/embassy-stm32/src/pac/stm32f446ve.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446ve.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446zc.rs b/embassy-stm32/src/pac/stm32f446zc.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446zc.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f446ze.rs b/embassy-stm32/src/pac/stm32f446ze.rs new file mode 100644 index 00000000..4e8597fc --- /dev/null +++ b/embassy-stm32/src/pac/stm32f446ze.rs @@ -0,0 +1,726 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 5); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 7); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PC7, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, MosiPin, PB0, 7); +impl_spi_pin!(SPI3, MosiPin, PB2, 7); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, MosiPin, PC1, 5); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD0, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _); +impl_spi!(SPI4, APB2); +impl_spi_pin!(SPI4, MisoPin, PD0, 5); +impl_spi_pin!(SPI4, SckPin, PE12, 5); +impl_spi_pin!(SPI4, MisoPin, PE13, 5); +impl_spi_pin!(SPI4, MosiPin, PE14, 5); +impl_spi_pin!(SPI4, SckPin, PE2, 5); +impl_spi_pin!(SPI4, MisoPin, PE5, 5); +impl_spi_pin!(SPI4, MosiPin, PE6, 5); +impl_spi_pin!(SPI4, SckPin, PG11, 6); +impl_spi_pin!(SPI4, MisoPin, PG12, 6); +impl_spi_pin!(SPI4, MosiPin, PG13, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::spi_v1 as spi; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CEC = 93, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FMPI2C1_ER = 96, + FMPI2C1_EV = 95, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDIO = 49, + SPDIF_RX = 94, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CEC); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FMPI2C1_ER); + declare!(FMPI2C1_EV); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDIO); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CEC(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FMPI2C1_ER(); + fn FMPI2C1_EV(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDIO(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 97] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FPU }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: CEC }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: FMPI2C1_EV, + }, + Vector { + _handler: FMPI2C1_ER, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ae.rs b/embassy-stm32/src/pac/stm32f469ae.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ae.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ag.rs b/embassy-stm32/src/pac/stm32f469ag.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ag.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ai.rs b/embassy-stm32/src/pac/stm32f469ai.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ai.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469be.rs b/embassy-stm32/src/pac/stm32f469be.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469be.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469bg.rs b/embassy-stm32/src/pac/stm32f469bg.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469bg.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469bi.rs b/embassy-stm32/src/pac/stm32f469bi.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469bi.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ie.rs b/embassy-stm32/src/pac/stm32f469ie.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ie.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ig.rs b/embassy-stm32/src/pac/stm32f469ig.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ig.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ii.rs b/embassy-stm32/src/pac/stm32f469ii.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ii.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ne.rs b/embassy-stm32/src/pac/stm32f469ne.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ne.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ng.rs b/embassy-stm32/src/pac/stm32f469ng.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ng.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ni.rs b/embassy-stm32/src/pac/stm32f469ni.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ni.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ve.rs b/embassy-stm32/src/pac/stm32f469ve.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ve.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469vg.rs b/embassy-stm32/src/pac/stm32f469vg.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469vg.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469vi.rs b/embassy-stm32/src/pac/stm32f469vi.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469vi.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469ze.rs b/embassy-stm32/src/pac/stm32f469ze.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469ze.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469zg.rs b/embassy-stm32/src/pac/stm32f469zg.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469zg.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f469zi.rs b/embassy-stm32/src/pac/stm32f469zi.rs new file mode 100644 index 00000000..669ceb41 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f469zi.rs @@ -0,0 +1,746 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ag.rs b/embassy-stm32/src/pac/stm32f479ag.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ag.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ai.rs b/embassy-stm32/src/pac/stm32f479ai.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ai.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479bg.rs b/embassy-stm32/src/pac/stm32f479bg.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479bg.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479bi.rs b/embassy-stm32/src/pac/stm32f479bi.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479bi.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ig.rs b/embassy-stm32/src/pac/stm32f479ig.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ig.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ii.rs b/embassy-stm32/src/pac/stm32f479ii.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ii.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ng.rs b/embassy-stm32/src/pac/stm32f479ng.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ng.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479ni.rs b/embassy-stm32/src/pac/stm32f479ni.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479ni.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479vg.rs b/embassy-stm32/src/pac/stm32f479vg.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479vg.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479vi.rs b/embassy-stm32/src/pac/stm32f479vi.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479vi.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479zg.rs b/embassy-stm32/src/pac/stm32f479zg.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479zg.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32f479zi.rs b/embassy-stm32/src/pac/stm32f479zi.rs new file mode 100644 index 00000000..59df72c2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32f479zi.rs @@ -0,0 +1,749 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x40020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _); +pub const USART1: usart::Usart = usart::Usart(0x40011000 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub const USART6: usart::Usart = usart::Usart(0x40011400 as _); +impl_usart!(USART6); +impl_usart_pin!(USART6, TxPin, PC6, 8); +impl_usart_pin!(USART6, RxPin, PC7, 8); +impl_usart_pin!(USART6, CkPin, PC8, 8); +impl_usart_pin!(USART6, RtsPin, PG12, 8); +impl_usart_pin!(USART6, CtsPin, PG13, 8); +impl_usart_pin!(USART6, TxPin, PG14, 8); +impl_usart_pin!(USART6, CtsPin, PG15, 8); +impl_usart_pin!(USART6, CkPin, PG7, 8); +impl_usart_pin!(USART6, RtsPin, PG8, 8); +impl_usart_pin!(USART6, RxPin, PG9, 8); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_f4 as syscfg; +pub use regs::usart_v1 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SYSCFG, USART1, USART2, USART3, USART6 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 64, + CAN2_RX1 = 65, + CAN2_SCE = 66, + CAN2_TX = 63, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 92, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LTDC = 88, + LTDC_ER = 89, + OTG_FS = 67, + OTG_FS_WKUP = 42, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD = 1, + QUADSPI = 91, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SDIO = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + TAMP_STAMP = 2, + TIM1_BRK_TIM9 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM11 = 26, + TIM1_UP_TIM10 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OTG_FS); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDIO); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM9); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM11); + declare!(TIM1_UP_TIM10); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LTDC(); + fn LTDC_ER(); + fn OTG_FS(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDIO(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM9(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM11(); + fn TIM1_UP_TIM10(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 93] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM9, + }, + Vector { + _handler: TIM1_UP_TIM10, + }, + Vector { + _handler: TIM1_TRG_COM_TIM11, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDIO }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: QUADSPI }, + Vector { _handler: DSI }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723ve.rs b/embassy-stm32/src/pac/stm32h723ve.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723ve.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723vg.rs b/embassy-stm32/src/pac/stm32h723vg.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723vg.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723ze.rs b/embassy-stm32/src/pac/stm32h723ze.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723ze.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h723zg.rs b/embassy-stm32/src/pac/stm32h723zg.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h723zg.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ae.rs b/embassy-stm32/src/pac/stm32h725ae.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ae.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ag.rs b/embassy-stm32/src/pac/stm32h725ag.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ag.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ie.rs b/embassy-stm32/src/pac/stm32h725ie.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ie.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ig.rs b/embassy-stm32/src/pac/stm32h725ig.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ig.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725re.rs b/embassy-stm32/src/pac/stm32h725re.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725re.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725rg.rs b/embassy-stm32/src/pac/stm32h725rg.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725rg.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ve.rs b/embassy-stm32/src/pac/stm32h725ve.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ve.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725vg.rs b/embassy-stm32/src/pac/stm32h725vg.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725vg.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725ze.rs b/embassy-stm32/src/pac/stm32h725ze.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725ze.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h725zg.rs b/embassy-stm32/src/pac/stm32h725zg.rs new file mode 100644 index 00000000..aedcde8e --- /dev/null +++ b/embassy-stm32/src/pac/stm32h725zg.rs @@ -0,0 +1,927 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730ab.rs b/embassy-stm32/src/pac/stm32h730ab.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730ab.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730ib.rs b/embassy-stm32/src/pac/stm32h730ib.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730ib.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730vb.rs b/embassy-stm32/src/pac/stm32h730vb.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730vb.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h730zb.rs b/embassy-stm32/src/pac/stm32h730zb.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h730zb.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h733vg.rs b/embassy-stm32/src/pac/stm32h733vg.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h733vg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h733zg.rs b/embassy-stm32/src/pac/stm32h733zg.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h733zg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735ag.rs b/embassy-stm32/src/pac/stm32h735ag.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735ag.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735ig.rs b/embassy-stm32/src/pac/stm32h735ig.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735ig.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735rg.rs b/embassy-stm32/src/pac/stm32h735rg.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735rg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735vg.rs b/embassy-stm32/src/pac/stm32h735vg.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735vg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h735zg.rs b/embassy-stm32/src/pac/stm32h735zg.rs new file mode 100644 index 00000000..589a1fd0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h735zg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, + PJ13, PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, + PK14, PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CORDIC = 154, + CRS = 144, + CRYP = 79, + DCMI_PSSI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN3_IT0 = 159, + FDCAN3_IT1 = 160, + FDCAN_CAL = 63, + FLASH = 4, + FMAC = 153, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + I2C5_ER = 158, + I2C5_EV = 157, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM23 = 161, + TIM24 = 162, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 155, + USART1 = 37, + USART10 = 156, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CORDIC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI_PSSI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN3_IT0); + declare!(FDCAN3_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMAC); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(I2C5_ER); + declare!(I2C5_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM23); + declare!(TIM24); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CORDIC(); + fn CRS(); + fn CRYP(); + fn DCMI_PSSI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN3_IT0(); + fn FDCAN3_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMAC(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn I2C5_ER(); + fn I2C5_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM23(); + fn TIM24(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 163] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: FMAC }, + Vector { _handler: CORDIC }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: I2C5_EV }, + Vector { _handler: I2C5_ER }, + Vector { + _handler: FDCAN3_IT0, + }, + Vector { + _handler: FDCAN3_IT1, + }, + Vector { _handler: TIM23 }, + Vector { _handler: TIM24 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ag.rs b/embassy-stm32/src/pac/stm32h742ag.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ag.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ai.rs b/embassy-stm32/src/pac/stm32h742ai.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ai.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742bg.rs b/embassy-stm32/src/pac/stm32h742bg.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742bg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742bi.rs b/embassy-stm32/src/pac/stm32h742bi.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742bi.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ig.rs b/embassy-stm32/src/pac/stm32h742ig.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ig.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742ii.rs b/embassy-stm32/src/pac/stm32h742ii.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742ii.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742vg.rs b/embassy-stm32/src/pac/stm32h742vg.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742vg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742vi.rs b/embassy-stm32/src/pac/stm32h742vi.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742vi.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742xg.rs b/embassy-stm32/src/pac/stm32h742xg.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742xg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742xi.rs b/embassy-stm32/src/pac/stm32h742xi.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742xi.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742zg.rs b/embassy-stm32/src/pac/stm32h742zg.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742zg.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h742zi.rs b/embassy-stm32/src/pac/stm32h742zi.rs new file mode 100644 index 00000000..6277a595 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h742zi.rs @@ -0,0 +1,936 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _reserved: 0 }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ag.rs b/embassy-stm32/src/pac/stm32h743ag.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ag.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ai.rs b/embassy-stm32/src/pac/stm32h743ai.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ai.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743bg.rs b/embassy-stm32/src/pac/stm32h743bg.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743bg.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743bi.rs b/embassy-stm32/src/pac/stm32h743bi.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743bi.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ig.rs b/embassy-stm32/src/pac/stm32h743ig.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ig.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743ii.rs b/embassy-stm32/src/pac/stm32h743ii.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743ii.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743vg.rs b/embassy-stm32/src/pac/stm32h743vg.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743vg.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743vi.rs b/embassy-stm32/src/pac/stm32h743vi.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743vi.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743xg.rs b/embassy-stm32/src/pac/stm32h743xg.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743xg.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743xi.rs b/embassy-stm32/src/pac/stm32h743xi.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743xi.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743zg.rs b/embassy-stm32/src/pac/stm32h743zg.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743zg.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h743zi.rs b/embassy-stm32/src/pac/stm32h743zi.rs new file mode 100644 index 00000000..47e811b4 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h743zi.rs @@ -0,0 +1,945 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745bg.rs b/embassy-stm32/src/pac/stm32h745bg.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745bg.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745bi.rs b/embassy-stm32/src/pac/stm32h745bi.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745bi.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745ig.rs b/embassy-stm32/src/pac/stm32h745ig.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745ig.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745ii.rs b/embassy-stm32/src/pac/stm32h745ii.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745ii.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745xg.rs b/embassy-stm32/src/pac/stm32h745xg.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745xg.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745xi.rs b/embassy-stm32/src/pac/stm32h745xi.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745xi.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745zg.rs b/embassy-stm32/src/pac/stm32h745zg.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745zg.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h745zi.rs b/embassy-stm32/src/pac/stm32h745zi.rs new file mode 100644 index 00000000..3a92848f --- /dev/null +++ b/embassy-stm32/src/pac/stm32h745zi.rs @@ -0,0 +1,959 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ag.rs b/embassy-stm32/src/pac/stm32h747ag.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ag.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ai.rs b/embassy-stm32/src/pac/stm32h747ai.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ai.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747bg.rs b/embassy-stm32/src/pac/stm32h747bg.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747bg.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747bi.rs b/embassy-stm32/src/pac/stm32h747bi.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747bi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ig.rs b/embassy-stm32/src/pac/stm32h747ig.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ig.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747ii.rs b/embassy-stm32/src/pac/stm32h747ii.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747ii.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747xg.rs b/embassy-stm32/src/pac/stm32h747xg.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747xg.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747xi.rs b/embassy-stm32/src/pac/stm32h747xi.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747xi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h747zi.rs b/embassy-stm32/src/pac/stm32h747zi.rs new file mode 100644 index 00000000..ade3d41d --- /dev/null +++ b/embassy-stm32/src/pac/stm32h747zi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750ib.rs b/embassy-stm32/src/pac/stm32h750ib.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750ib.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750vb.rs b/embassy-stm32/src/pac/stm32h750vb.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750vb.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750xb.rs b/embassy-stm32/src/pac/stm32h750xb.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750xb.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h750zb.rs b/embassy-stm32/src/pac/stm32h750zb.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h750zb.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753ai.rs b/embassy-stm32/src/pac/stm32h753ai.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753ai.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753bi.rs b/embassy-stm32/src/pac/stm32h753bi.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753bi.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753ii.rs b/embassy-stm32/src/pac/stm32h753ii.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753ii.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753vi.rs b/embassy-stm32/src/pac/stm32h753vi.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753vi.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753xi.rs b/embassy-stm32/src/pac/stm32h753xi.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753xi.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h753zi.rs b/embassy-stm32/src/pac/stm32h753zi.rs new file mode 100644 index 00000000..cfaf3608 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h753zi.rs @@ -0,0 +1,948 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755bi.rs b/embassy-stm32/src/pac/stm32h755bi.rs new file mode 100644 index 00000000..673440d2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755bi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755ii.rs b/embassy-stm32/src/pac/stm32h755ii.rs new file mode 100644 index 00000000..673440d2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755ii.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755xi.rs b/embassy-stm32/src/pac/stm32h755xi.rs new file mode 100644 index 00000000..673440d2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755xi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h755zi.rs b/embassy-stm32/src/pac/stm32h755zi.rs new file mode 100644 index 00000000..673440d2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h755zi.rs @@ -0,0 +1,962 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757ai.rs b/embassy-stm32/src/pac/stm32h757ai.rs new file mode 100644 index 00000000..66057ae0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757ai.rs @@ -0,0 +1,965 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757bi.rs b/embassy-stm32/src/pac/stm32h757bi.rs new file mode 100644 index 00000000..66057ae0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757bi.rs @@ -0,0 +1,965 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757ii.rs b/embassy-stm32/src/pac/stm32h757ii.rs new file mode 100644 index 00000000..66057ae0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757ii.rs @@ -0,0 +1,965 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757xi.rs b/embassy-stm32/src/pac/stm32h757xi.rs new file mode 100644 index 00000000..66057ae0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757xi.rs @@ -0,0 +1,965 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h757zi.rs b/embassy-stm32/src/pac/stm32h757zi.rs new file mode 100644 index 00000000..66057ae0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h757zi.rs @@ -0,0 +1,965 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + ADC3 = 127, + BDMA_Channel0 = 129, + BDMA_Channel1 = 130, + BDMA_Channel2 = 131, + BDMA_Channel3 = 132, + BDMA_Channel4 = 133, + BDMA_Channel5 = 134, + BDMA_Channel6 = 135, + BDMA_Channel7 = 136, + CEC = 94, + CM4_SEV = 65, + CM7_SEV = 64, + CRS = 144, + CRYP = 79, + DCMI = 78, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DSI = 123, + ECC = 145, + ETH = 61, + ETH_WKUP = 62, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + HOLD_CORE = 148, + HRTIM1_FLT = 109, + HRTIM1_Master = 103, + HRTIM1_TIMA = 104, + HRTIM1_TIMB = 105, + HRTIM1_TIMC = 106, + HRTIM1_TIMD = 107, + HRTIM1_TIME = 108, + HSEM1 = 125, + HSEM2 = 126, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPTIM4 = 140, + LPTIM5 = 141, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OTG_FS = 101, + OTG_FS_EP1_IN = 99, + OTG_FS_EP1_OUT = 98, + OTG_FS_WKUP = 100, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_AVD = 1, + QUADSPI = 92, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SAI3 = 114, + SAI4 = 146, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TAMP_STAMP = 2, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(ADC3); + declare!(BDMA_Channel0); + declare!(BDMA_Channel1); + declare!(BDMA_Channel2); + declare!(BDMA_Channel3); + declare!(BDMA_Channel4); + declare!(BDMA_Channel5); + declare!(BDMA_Channel6); + declare!(BDMA_Channel7); + declare!(CEC); + declare!(CM4_SEV); + declare!(CM7_SEV); + declare!(CRS); + declare!(CRYP); + declare!(DCMI); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DSI); + declare!(ECC); + declare!(ETH); + declare!(ETH_WKUP); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(HOLD_CORE); + declare!(HRTIM1_FLT); + declare!(HRTIM1_Master); + declare!(HRTIM1_TIMA); + declare!(HRTIM1_TIMB); + declare!(HRTIM1_TIMC); + declare!(HRTIM1_TIMD); + declare!(HRTIM1_TIME); + declare!(HSEM1); + declare!(HSEM2); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPTIM4); + declare!(LPTIM5); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OTG_FS); + declare!(OTG_FS_EP1_IN); + declare!(OTG_FS_EP1_OUT); + declare!(OTG_FS_WKUP); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_AVD); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SAI3); + declare!(SAI4); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn ADC3(); + fn BDMA_Channel0(); + fn BDMA_Channel1(); + fn BDMA_Channel2(); + fn BDMA_Channel3(); + fn BDMA_Channel4(); + fn BDMA_Channel5(); + fn BDMA_Channel6(); + fn BDMA_Channel7(); + fn CEC(); + fn CM4_SEV(); + fn CM7_SEV(); + fn CRS(); + fn CRYP(); + fn DCMI(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DSI(); + fn ECC(); + fn ETH(); + fn ETH_WKUP(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn HOLD_CORE(); + fn HRTIM1_FLT(); + fn HRTIM1_Master(); + fn HRTIM1_TIMA(); + fn HRTIM1_TIMB(); + fn HRTIM1_TIMC(); + fn HRTIM1_TIMD(); + fn HRTIM1_TIME(); + fn HSEM1(); + fn HSEM2(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPTIM4(); + fn LPTIM5(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OTG_FS(); + fn OTG_FS_EP1_IN(); + fn OTG_FS_EP1_OUT(); + fn OTG_FS_WKUP(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_AVD(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SAI3(); + fn SAI4(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 150] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_AVD }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _handler: ETH }, + Vector { _handler: ETH_WKUP }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { _handler: CM7_SEV }, + Vector { _handler: CM4_SEV }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { _handler: DCMI }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: QUADSPI }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { + _handler: OTG_FS_EP1_OUT, + }, + Vector { + _handler: OTG_FS_EP1_IN, + }, + Vector { + _handler: OTG_FS_WKUP, + }, + Vector { _handler: OTG_FS }, + Vector { _reserved: 0 }, + Vector { + _handler: HRTIM1_Master, + }, + Vector { + _handler: HRTIM1_TIMA, + }, + Vector { + _handler: HRTIM1_TIMB, + }, + Vector { + _handler: HRTIM1_TIMC, + }, + Vector { + _handler: HRTIM1_TIMD, + }, + Vector { + _handler: HRTIM1_TIME, + }, + Vector { + _handler: HRTIM1_FLT, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SAI3 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _handler: DSI }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _handler: HSEM2 }, + Vector { _handler: ADC3 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA_Channel0, + }, + Vector { + _handler: BDMA_Channel1, + }, + Vector { + _handler: BDMA_Channel2, + }, + Vector { + _handler: BDMA_Channel3, + }, + Vector { + _handler: BDMA_Channel4, + }, + Vector { + _handler: BDMA_Channel5, + }, + Vector { + _handler: BDMA_Channel6, + }, + Vector { + _handler: BDMA_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: LPTIM4 }, + Vector { _handler: LPTIM5 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _handler: SAI4 }, + Vector { _reserved: 0 }, + Vector { + _handler: HOLD_CORE, + }, + Vector { + _handler: WAKEUP_PIN, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ag.rs b/embassy-stm32/src/pac/stm32h7a3ag.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ag.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ai.rs b/embassy-stm32/src/pac/stm32h7a3ai.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ai.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ig.rs b/embassy-stm32/src/pac/stm32h7a3ig.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ig.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ii.rs b/embassy-stm32/src/pac/stm32h7a3ii.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ii.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3lg.rs b/embassy-stm32/src/pac/stm32h7a3lg.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3lg.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3li.rs b/embassy-stm32/src/pac/stm32h7a3li.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3li.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ng.rs b/embassy-stm32/src/pac/stm32h7a3ng.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ng.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ni.rs b/embassy-stm32/src/pac/stm32h7a3ni.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ni.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3qi.rs b/embassy-stm32/src/pac/stm32h7a3qi.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3qi.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3rg.rs b/embassy-stm32/src/pac/stm32h7a3rg.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3rg.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3ri.rs b/embassy-stm32/src/pac/stm32h7a3ri.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3ri.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3vg.rs b/embassy-stm32/src/pac/stm32h7a3vg.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3vg.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3vi.rs b/embassy-stm32/src/pac/stm32h7a3vi.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3vi.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3zg.rs b/embassy-stm32/src/pac/stm32h7a3zg.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3zg.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7a3zi.rs b/embassy-stm32/src/pac/stm32h7a3zi.rs new file mode 100644 index 00000000..cc3b10a9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7a3zi.rs @@ -0,0 +1,929 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0ab.rs b/embassy-stm32/src/pac/stm32h7b0ab.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0ab.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0ib.rs b/embassy-stm32/src/pac/stm32h7b0ib.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0ib.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0rb.rs b/embassy-stm32/src/pac/stm32h7b0rb.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0rb.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0vb.rs b/embassy-stm32/src/pac/stm32h7b0vb.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0vb.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b0zb.rs b/embassy-stm32/src/pac/stm32h7b0zb.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b0zb.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ai.rs b/embassy-stm32/src/pac/stm32h7b3ai.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ai.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ii.rs b/embassy-stm32/src/pac/stm32h7b3ii.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ii.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3li.rs b/embassy-stm32/src/pac/stm32h7b3li.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3li.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ni.rs b/embassy-stm32/src/pac/stm32h7b3ni.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ni.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3qi.rs b/embassy-stm32/src/pac/stm32h7b3qi.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3qi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3ri.rs b/embassy-stm32/src/pac/stm32h7b3ri.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3ri.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3vi.rs b/embassy-stm32/src/pac/stm32h7b3vi.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3vi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32h7b3zi.rs b/embassy-stm32/src/pac/stm32h7b3zi.rs new file mode 100644 index 00000000..cba2c71b --- /dev/null +++ b/embassy-stm32/src/pac/stm32h7b3zi.rs @@ -0,0 +1,938 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x58020000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x58000000 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x58020000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x58020400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x58020800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x58020c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x58021000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x58021400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x58021800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x58021c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x58022000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x58022400 as _); +impl_gpio_pin!(PJ0, 9, 0, EXTI0); +impl_gpio_pin!(PJ1, 9, 1, EXTI1); +impl_gpio_pin!(PJ2, 9, 2, EXTI2); +impl_gpio_pin!(PJ3, 9, 3, EXTI3); +impl_gpio_pin!(PJ4, 9, 4, EXTI4); +impl_gpio_pin!(PJ5, 9, 5, EXTI5); +impl_gpio_pin!(PJ6, 9, 6, EXTI6); +impl_gpio_pin!(PJ7, 9, 7, EXTI7); +impl_gpio_pin!(PJ8, 9, 8, EXTI8); +impl_gpio_pin!(PJ9, 9, 9, EXTI9); +impl_gpio_pin!(PJ10, 9, 10, EXTI10); +impl_gpio_pin!(PJ11, 9, 11, EXTI11); +impl_gpio_pin!(PJ12, 9, 12, EXTI12); +impl_gpio_pin!(PJ13, 9, 13, EXTI13); +impl_gpio_pin!(PJ14, 9, 14, EXTI14); +impl_gpio_pin!(PJ15, 9, 15, EXTI15); +pub const GPIOK: gpio::Gpio = gpio::Gpio(0x58022800 as _); +impl_gpio_pin!(PK0, 10, 0, EXTI0); +impl_gpio_pin!(PK1, 10, 1, EXTI1); +impl_gpio_pin!(PK2, 10, 2, EXTI2); +impl_gpio_pin!(PK3, 10, 3, EXTI3); +impl_gpio_pin!(PK4, 10, 4, EXTI4); +impl_gpio_pin!(PK5, 10, 5, EXTI5); +impl_gpio_pin!(PK6, 10, 6, EXTI6); +impl_gpio_pin!(PK7, 10, 7, EXTI7); +impl_gpio_pin!(PK8, 10, 8, EXTI8); +impl_gpio_pin!(PK9, 10, 9, EXTI9); +impl_gpio_pin!(PK10, 10, 10, EXTI10); +impl_gpio_pin!(PK11, 10, 11, EXTI11); +impl_gpio_pin!(PK12, 10, 12, EXTI12); +impl_gpio_pin!(PK13, 10, 13, EXTI13); +impl_gpio_pin!(PK14, 10, 14, EXTI14); +impl_gpio_pin!(PK15, 10, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x48021800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SDMMC1: sdmmc::Sdmmc = sdmmc::Sdmmc(0x52007000 as _); +impl_sdmmc!(SDMMC1); +impl_sdmmc_pin!(SDMMC1, D0Pin, PB13, 12); +impl_sdmmc_pin!(SDMMC1, D4Pin, PB8, 12); +impl_sdmmc_pin!(SDMMC1, D5Pin, PB9, 12); +impl_sdmmc_pin!(SDMMC1, D2Pin, PC10, 12); +impl_sdmmc_pin!(SDMMC1, D3Pin, PC11, 12); +impl_sdmmc_pin!(SDMMC1, CkPin, PC12, 12); +impl_sdmmc_pin!(SDMMC1, D6Pin, PC6, 12); +impl_sdmmc_pin!(SDMMC1, D7Pin, PC7, 12); +impl_sdmmc_pin!(SDMMC1, D0Pin, PC8, 12); +impl_sdmmc_pin!(SDMMC1, D1Pin, PC9, 12); +impl_sdmmc_pin!(SDMMC1, CmdPin, PD2, 12); +pub const SDMMC2: sdmmc::Sdmmc = sdmmc::Sdmmc(0x48022400 as _); +impl_sdmmc!(SDMMC2); +impl_sdmmc_pin!(SDMMC2, CmdPin, PA0, 9); +impl_sdmmc_pin!(SDMMC2, D0Pin, PB14, 9); +impl_sdmmc_pin!(SDMMC2, D1Pin, PB15, 9); +impl_sdmmc_pin!(SDMMC2, D2Pin, PB3, 9); +impl_sdmmc_pin!(SDMMC2, D3Pin, PB4, 9); +impl_sdmmc_pin!(SDMMC2, D4Pin, PB8, 10); +impl_sdmmc_pin!(SDMMC2, D5Pin, PB9, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PC1, 9); +impl_sdmmc_pin!(SDMMC2, D6Pin, PC6, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PC7, 10); +impl_sdmmc_pin!(SDMMC2, CkPin, PD6, 11); +impl_sdmmc_pin!(SDMMC2, CmdPin, PD7, 11); +impl_sdmmc_pin!(SDMMC2, D1Pin, PG10, 11); +impl_sdmmc_pin!(SDMMC2, D2Pin, PG11, 10); +impl_sdmmc_pin!(SDMMC2, D3Pin, PG12, 10); +impl_sdmmc_pin!(SDMMC2, D6Pin, PG13, 10); +impl_sdmmc_pin!(SDMMC2, D7Pin, PG14, 10); +impl_sdmmc_pin!(SDMMC2, D0Pin, PG9, 11); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x58000400 as _); +pub use regs::dma_v2 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::sdmmc_v2 as sdmmc; +pub use regs::syscfg_h7 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13, + PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14, + PK15, RNG, SDMMC1, SDMMC2, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC = 18, + BDMA1 = 154, + BDMA2_Channel0 = 129, + BDMA2_Channel1 = 130, + BDMA2_Channel2 = 131, + BDMA2_Channel3 = 132, + BDMA2_Channel4 = 133, + BDMA2_Channel5 = 134, + BDMA2_Channel6 = 135, + BDMA2_Channel7 = 136, + CEC = 94, + CRS = 144, + CRYP = 79, + DAC2 = 127, + DCMI_PSSI = 78, + DFSDM1_FLT4 = 64, + DFSDM1_FLT5 = 65, + DFSDM1_FLT6 = 66, + DFSDM1_FLT7 = 67, + DFSDM2 = 42, + DMA1_Stream0 = 11, + DMA1_Stream1 = 12, + DMA1_Stream2 = 13, + DMA1_Stream3 = 14, + DMA1_Stream4 = 15, + DMA1_Stream5 = 16, + DMA1_Stream6 = 17, + DMA1_Stream7 = 47, + DMA2D = 90, + DMA2_Stream0 = 56, + DMA2_Stream1 = 57, + DMA2_Stream2 = 58, + DMA2_Stream3 = 59, + DMA2_Stream4 = 60, + DMA2_Stream5 = 68, + DMA2_Stream6 = 69, + DMA2_Stream7 = 70, + DTS = 147, + ECC = 145, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FDCAN1_IT0 = 19, + FDCAN1_IT1 = 21, + FDCAN2_IT0 = 20, + FDCAN2_IT1 = 22, + FDCAN_CAL = 63, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 153, + HASH_RNG = 80, + HSEM1 = 125, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 96, + I2C4_EV = 95, + JPEG = 121, + LPTIM1 = 93, + LPTIM2 = 138, + LPTIM3 = 139, + LPUART1 = 142, + LTDC = 88, + LTDC_ER = 89, + MDIOS = 120, + MDIOS_WKUP = 119, + MDMA = 122, + OCTOSPI1 = 92, + OCTOSPI2 = 150, + OTFDEC1 = 151, + OTFDEC2 = 152, + OTG_HS = 77, + OTG_HS_EP1_IN = 75, + OTG_HS_EP1_OUT = 74, + OTG_HS_WKUP = 76, + PVD_PVM = 1, + RCC = 5, + RTC_Alarm = 41, + RTC_TAMP_STAMP_CSS_LSE = 2, + RTC_WKUP = 3, + SAI1 = 87, + SAI2 = 91, + SDMMC1 = 49, + SDMMC2 = 124, + SPDIF_RX = 97, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SPI4 = 84, + SPI5 = 85, + SPI6 = 86, + SWPMI1 = 115, + TIM15 = 116, + TIM16 = 117, + TIM17 = 118, + TIM1_BRK = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK_TIM12 = 43, + TIM8_CC = 46, + TIM8_TRG_COM_TIM14 = 45, + TIM8_UP_TIM13 = 44, + UART4 = 52, + UART5 = 53, + UART7 = 82, + UART8 = 83, + UART9 = 140, + USART1 = 37, + USART10 = 141, + USART2 = 38, + USART3 = 39, + USART6 = 71, + WAKEUP_PIN = 149, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC); + declare!(BDMA1); + declare!(BDMA2_Channel0); + declare!(BDMA2_Channel1); + declare!(BDMA2_Channel2); + declare!(BDMA2_Channel3); + declare!(BDMA2_Channel4); + declare!(BDMA2_Channel5); + declare!(BDMA2_Channel6); + declare!(BDMA2_Channel7); + declare!(CEC); + declare!(CRS); + declare!(CRYP); + declare!(DAC2); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT4); + declare!(DFSDM1_FLT5); + declare!(DFSDM1_FLT6); + declare!(DFSDM1_FLT7); + declare!(DFSDM2); + declare!(DMA1_Stream0); + declare!(DMA1_Stream1); + declare!(DMA1_Stream2); + declare!(DMA1_Stream3); + declare!(DMA1_Stream4); + declare!(DMA1_Stream5); + declare!(DMA1_Stream6); + declare!(DMA1_Stream7); + declare!(DMA2D); + declare!(DMA2_Stream0); + declare!(DMA2_Stream1); + declare!(DMA2_Stream2); + declare!(DMA2_Stream3); + declare!(DMA2_Stream4); + declare!(DMA2_Stream5); + declare!(DMA2_Stream6); + declare!(DMA2_Stream7); + declare!(DTS); + declare!(ECC); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FDCAN1_IT0); + declare!(FDCAN1_IT1); + declare!(FDCAN2_IT0); + declare!(FDCAN2_IT1); + declare!(FDCAN_CAL); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_RNG); + declare!(HSEM1); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(JPEG); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPTIM3); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(MDIOS); + declare!(MDIOS_WKUP); + declare!(MDMA); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTFDEC1); + declare!(OTFDEC2); + declare!(OTG_HS); + declare!(OTG_HS_EP1_IN); + declare!(OTG_HS_EP1_OUT); + declare!(OTG_HS_WKUP); + declare!(PVD_PVM); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_TAMP_STAMP_CSS_LSE); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPDIF_RX); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SPI4); + declare!(SPI5); + declare!(SPI6); + declare!(SWPMI1); + declare!(TIM15); + declare!(TIM16); + declare!(TIM17); + declare!(TIM1_BRK); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK_TIM12); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM_TIM14); + declare!(TIM8_UP_TIM13); + declare!(UART4); + declare!(UART5); + declare!(UART7); + declare!(UART8); + declare!(UART9); + declare!(USART1); + declare!(USART10); + declare!(USART2); + declare!(USART3); + declare!(USART6); + declare!(WAKEUP_PIN); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC(); + fn BDMA1(); + fn BDMA2_Channel0(); + fn BDMA2_Channel1(); + fn BDMA2_Channel2(); + fn BDMA2_Channel3(); + fn BDMA2_Channel4(); + fn BDMA2_Channel5(); + fn BDMA2_Channel6(); + fn BDMA2_Channel7(); + fn CEC(); + fn CRS(); + fn CRYP(); + fn DAC2(); + fn DCMI_PSSI(); + fn DFSDM1_FLT4(); + fn DFSDM1_FLT5(); + fn DFSDM1_FLT6(); + fn DFSDM1_FLT7(); + fn DFSDM2(); + fn DMA1_Stream0(); + fn DMA1_Stream1(); + fn DMA1_Stream2(); + fn DMA1_Stream3(); + fn DMA1_Stream4(); + fn DMA1_Stream5(); + fn DMA1_Stream6(); + fn DMA1_Stream7(); + fn DMA2D(); + fn DMA2_Stream0(); + fn DMA2_Stream1(); + fn DMA2_Stream2(); + fn DMA2_Stream3(); + fn DMA2_Stream4(); + fn DMA2_Stream5(); + fn DMA2_Stream6(); + fn DMA2_Stream7(); + fn DTS(); + fn ECC(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FDCAN1_IT0(); + fn FDCAN1_IT1(); + fn FDCAN2_IT0(); + fn FDCAN2_IT1(); + fn FDCAN_CAL(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_RNG(); + fn HSEM1(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn JPEG(); + fn LPTIM1(); + fn LPTIM2(); + fn LPTIM3(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn MDIOS(); + fn MDIOS_WKUP(); + fn MDMA(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTFDEC1(); + fn OTFDEC2(); + fn OTG_HS(); + fn OTG_HS_EP1_IN(); + fn OTG_HS_EP1_OUT(); + fn OTG_HS_WKUP(); + fn PVD_PVM(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_TAMP_STAMP_CSS_LSE(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPDIF_RX(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SPI4(); + fn SPI5(); + fn SPI6(); + fn SWPMI1(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM1_BRK(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK_TIM12(); + fn TIM8_CC(); + fn TIM8_TRG_COM_TIM14(); + fn TIM8_UP_TIM13(); + fn UART4(); + fn UART5(); + fn UART7(); + fn UART8(); + fn UART9(); + fn USART1(); + fn USART10(); + fn USART2(); + fn USART3(); + fn USART6(); + fn WAKEUP_PIN(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 155] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: RTC_TAMP_STAMP_CSS_LSE, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Stream0, + }, + Vector { + _handler: DMA1_Stream1, + }, + Vector { + _handler: DMA1_Stream2, + }, + Vector { + _handler: DMA1_Stream3, + }, + Vector { + _handler: DMA1_Stream4, + }, + Vector { + _handler: DMA1_Stream5, + }, + Vector { + _handler: DMA1_Stream6, + }, + Vector { _handler: ADC }, + Vector { + _handler: FDCAN1_IT0, + }, + Vector { + _handler: FDCAN2_IT0, + }, + Vector { + _handler: FDCAN1_IT1, + }, + Vector { + _handler: FDCAN2_IT1, + }, + Vector { _handler: EXTI9_5 }, + Vector { _handler: TIM1_BRK }, + Vector { _handler: TIM1_UP }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _handler: DFSDM2 }, + Vector { + _handler: TIM8_BRK_TIM12, + }, + Vector { + _handler: TIM8_UP_TIM13, + }, + Vector { + _handler: TIM8_TRG_COM_TIM14, + }, + Vector { _handler: TIM8_CC }, + Vector { + _handler: DMA1_Stream7, + }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Stream0, + }, + Vector { + _handler: DMA2_Stream1, + }, + Vector { + _handler: DMA2_Stream2, + }, + Vector { + _handler: DMA2_Stream3, + }, + Vector { + _handler: DMA2_Stream4, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: FDCAN_CAL, + }, + Vector { + _handler: DFSDM1_FLT4, + }, + Vector { + _handler: DFSDM1_FLT5, + }, + Vector { + _handler: DFSDM1_FLT6, + }, + Vector { + _handler: DFSDM1_FLT7, + }, + Vector { + _handler: DMA2_Stream5, + }, + Vector { + _handler: DMA2_Stream6, + }, + Vector { + _handler: DMA2_Stream7, + }, + Vector { _handler: USART6 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { + _handler: OTG_HS_EP1_OUT, + }, + Vector { + _handler: OTG_HS_EP1_IN, + }, + Vector { + _handler: OTG_HS_WKUP, + }, + Vector { _handler: OTG_HS }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: CRYP }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: UART7 }, + Vector { _handler: UART8 }, + Vector { _handler: SPI4 }, + Vector { _handler: SPI5 }, + Vector { _handler: SPI6 }, + Vector { _handler: SAI1 }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: DMA2D }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: LPTIM1 }, + Vector { _handler: CEC }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: SPDIF_RX }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { + _handler: MDIOS_WKUP, + }, + Vector { _handler: MDIOS }, + Vector { _handler: JPEG }, + Vector { _handler: MDMA }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC2 }, + Vector { _handler: HSEM1 }, + Vector { _reserved: 0 }, + Vector { _handler: DAC2 }, + Vector { _reserved: 0 }, + Vector { + _handler: BDMA2_Channel0, + }, + Vector { + _handler: BDMA2_Channel1, + }, + Vector { + _handler: BDMA2_Channel2, + }, + Vector { + _handler: BDMA2_Channel3, + }, + Vector { + _handler: BDMA2_Channel4, + }, + Vector { + _handler: BDMA2_Channel5, + }, + Vector { + _handler: BDMA2_Channel6, + }, + Vector { + _handler: BDMA2_Channel7, + }, + Vector { _reserved: 0 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: LPTIM3 }, + Vector { _handler: UART9 }, + Vector { _handler: USART10 }, + Vector { _handler: LPUART1 }, + Vector { _reserved: 0 }, + Vector { _handler: CRS }, + Vector { _handler: ECC }, + Vector { _reserved: 0 }, + Vector { _handler: DTS }, + Vector { _reserved: 0 }, + Vector { + _handler: WAKEUP_PIN, + }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: OTFDEC1 }, + Vector { _handler: OTFDEC2 }, + Vector { _handler: GFXMMU }, + Vector { _handler: BDMA1 }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412c8.rs b/embassy-stm32/src/pac/stm32l412c8.rs new file mode 100644 index 00000000..375c6c33 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412c8.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412cb.rs b/embassy-stm32/src/pac/stm32l412cb.rs new file mode 100644 index 00000000..375c6c33 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412cb.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412k8.rs b/embassy-stm32/src/pac/stm32l412k8.rs new file mode 100644 index 00000000..fda1af22 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412k8.rs @@ -0,0 +1,474 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412kb.rs b/embassy-stm32/src/pac/stm32l412kb.rs new file mode 100644 index 00000000..fda1af22 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412kb.rs @@ -0,0 +1,474 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412r8.rs b/embassy-stm32/src/pac/stm32l412r8.rs new file mode 100644 index 00000000..375c6c33 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412r8.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412rb.rs b/embassy-stm32/src/pac/stm32l412rb.rs new file mode 100644 index 00000000..375c6c33 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412rb.rs @@ -0,0 +1,491 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412t8.rs b/embassy-stm32/src/pac/stm32l412t8.rs new file mode 100644 index 00000000..fda1af22 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412t8.rs @@ -0,0 +1,474 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l412tb.rs b/embassy-stm32/src/pac/stm32l412tb.rs new file mode 100644 index 00000000..fda1af22 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l412tb.rs @@ -0,0 +1,474 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422cb.rs b/embassy-stm32/src/pac/stm32l422cb.rs new file mode 100644 index 00000000..8b640bfd --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422cb.rs @@ -0,0 +1,494 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422kb.rs b/embassy-stm32/src/pac/stm32l422kb.rs new file mode 100644 index 00000000..8f407c05 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422kb.rs @@ -0,0 +1,477 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422rb.rs b/embassy-stm32/src/pac/stm32l422rb.rs new file mode 100644 index 00000000..8b640bfd --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422rb.rs @@ -0,0 +1,494 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l422tb.rs b/embassy-stm32/src/pac/stm32l422tb.rs new file mode 100644 index 00000000..8f407c05 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l422tb.rs @@ -0,0 +1,477 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, + PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SPI1 = 35, + SPI2 = 36, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6 = 54, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SPI1); + declare!(SPI2); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SPI1(); + fn SPI2(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431cb.rs b/embassy-stm32/src/pac/stm32l431cb.rs new file mode 100644 index 00000000..fc01e44d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431cb.rs @@ -0,0 +1,577 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431cc.rs b/embassy-stm32/src/pac/stm32l431cc.rs new file mode 100644 index 00000000..fc01e44d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431cc.rs @@ -0,0 +1,577 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431kb.rs b/embassy-stm32/src/pac/stm32l431kb.rs new file mode 100644 index 00000000..f569524f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431kb.rs @@ -0,0 +1,544 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431kc.rs b/embassy-stm32/src/pac/stm32l431kc.rs new file mode 100644 index 00000000..f569524f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431kc.rs @@ -0,0 +1,544 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431rb.rs b/embassy-stm32/src/pac/stm32l431rb.rs new file mode 100644 index 00000000..fc01e44d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431rb.rs @@ -0,0 +1,577 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431rc.rs b/embassy-stm32/src/pac/stm32l431rc.rs new file mode 100644 index 00000000..fc01e44d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431rc.rs @@ -0,0 +1,577 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l431vc.rs b/embassy-stm32/src/pac/stm32l431vc.rs new file mode 100644 index 00000000..fc01e44d --- /dev/null +++ b/embassy-stm32/src/pac/stm32l431vc.rs @@ -0,0 +1,577 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l432kb.rs b/embassy-stm32/src/pac/stm32l432kb.rs new file mode 100644 index 00000000..83a08971 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l432kb.rs @@ -0,0 +1,489 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l432kc.rs b/embassy-stm32/src/pac/stm32l432kc.rs new file mode 100644 index 00000000..83a08971 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l432kc.rs @@ -0,0 +1,489 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433cb.rs b/embassy-stm32/src/pac/stm32l433cb.rs new file mode 100644 index 00000000..1257e699 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433cb.rs @@ -0,0 +1,583 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433cc.rs b/embassy-stm32/src/pac/stm32l433cc.rs new file mode 100644 index 00000000..1257e699 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433cc.rs @@ -0,0 +1,583 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433rb.rs b/embassy-stm32/src/pac/stm32l433rb.rs new file mode 100644 index 00000000..1257e699 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433rb.rs @@ -0,0 +1,583 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433rc.rs b/embassy-stm32/src/pac/stm32l433rc.rs new file mode 100644 index 00000000..1257e699 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433rc.rs @@ -0,0 +1,583 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l433vc.rs b/embassy-stm32/src/pac/stm32l433vc.rs new file mode 100644 index 00000000..1257e699 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l433vc.rs @@ -0,0 +1,583 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l442kc.rs b/embassy-stm32/src/pac/stm32l442kc.rs new file mode 100644 index 00000000..11e64acd --- /dev/null +++ b/embassy-stm32/src/pac/stm32l442kc.rs @@ -0,0 +1,492 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5, + PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI3, SYSCFG, USART1, + USART2 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SPI1 = 35, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SPI1); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SPI1(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _reserved: 0 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _reserved: 0 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443cc.rs b/embassy-stm32/src/pac/stm32l443cc.rs new file mode 100644 index 00000000..07bcb8f2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443cc.rs @@ -0,0 +1,586 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443rc.rs b/embassy-stm32/src/pac/stm32l443rc.rs new file mode 100644 index 00000000..07bcb8f2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443rc.rs @@ -0,0 +1,586 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l443vc.rs b/embassy-stm32/src/pac/stm32l443vc.rs new file mode 100644 index 00000000..07bcb8f2 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l443vc.rs @@ -0,0 +1,586 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM6_DAC = 54, + TIM7 = 55, + TSC = 77, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TSC); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM6_DAC(); + fn TIM7(); + fn TSC(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 83] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451cc.rs b/embassy-stm32/src/pac/stm32l451cc.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451cc.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451ce.rs b/embassy-stm32/src/pac/stm32l451ce.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451ce.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451rc.rs b/embassy-stm32/src/pac/stm32l451rc.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451rc.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451re.rs b/embassy-stm32/src/pac/stm32l451re.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451re.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451vc.rs b/embassy-stm32/src/pac/stm32l451vc.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451vc.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l451ve.rs b/embassy-stm32/src/pac/stm32l451ve.rs new file mode 100644 index 00000000..d90f1ff7 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l451ve.rs @@ -0,0 +1,561 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452cc.rs b/embassy-stm32/src/pac/stm32l452cc.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452cc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452ce.rs b/embassy-stm32/src/pac/stm32l452ce.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452ce.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452rc.rs b/embassy-stm32/src/pac/stm32l452rc.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452rc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452re.rs b/embassy-stm32/src/pac/stm32l452re.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452re.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452vc.rs b/embassy-stm32/src/pac/stm32l452vc.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452vc.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l452ve.rs b/embassy-stm32/src/pac/stm32l452ve.rs new file mode 100644 index 00000000..34e55cda --- /dev/null +++ b/embassy-stm32/src/pac/stm32l452ve.rs @@ -0,0 +1,564 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462ce.rs b/embassy-stm32/src/pac/stm32l462ce.rs new file mode 100644 index 00000000..6a25f7e0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462ce.rs @@ -0,0 +1,567 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462re.rs b/embassy-stm32/src/pac/stm32l462re.rs new file mode 100644 index 00000000..6a25f7e0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462re.rs @@ -0,0 +1,567 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l462ve.rs b/embassy-stm32/src/pac/stm32l462ve.rs new file mode 100644 index 00000000..6a25f7e0 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l462ve.rs @@ -0,0 +1,567 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, + PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM6_DAC = 54, + TSC = 77, + UART4 = 52, + USART1 = 37, + USART2 = 38, + USART3 = 39, + USB = 67, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM6_DAC); + declare!(TSC); + declare!(UART4); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(USB); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM6_DAC(); + fn TSC(); + fn UART4(); + fn USART1(); + fn USART2(); + fn USART3(); + fn USB(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 85] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _reserved: 0 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: SDMMC1 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _reserved: 0 }, + Vector { _handler: TIM6_DAC }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: USB }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471qe.rs b/embassy-stm32/src/pac/stm32l471qe.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471qe.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471qg.rs b/embassy-stm32/src/pac/stm32l471qg.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471qg.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471re.rs b/embassy-stm32/src/pac/stm32l471re.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471re.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471rg.rs b/embassy-stm32/src/pac/stm32l471rg.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471rg.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471ve.rs b/embassy-stm32/src/pac/stm32l471ve.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471ve.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471vg.rs b/embassy-stm32/src/pac/stm32l471vg.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471vg.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471ze.rs b/embassy-stm32/src/pac/stm32l471ze.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471ze.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l471zg.rs b/embassy-stm32/src/pac/stm32l471zg.rs new file mode 100644 index 00000000..27c3ac06 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l471zg.rs @@ -0,0 +1,636 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475rc.rs b/embassy-stm32/src/pac/stm32l475rc.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475rc.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475re.rs b/embassy-stm32/src/pac/stm32l475re.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475re.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475rg.rs b/embassy-stm32/src/pac/stm32l475rg.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475rg.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475vc.rs b/embassy-stm32/src/pac/stm32l475vc.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475vc.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475ve.rs b/embassy-stm32/src/pac/stm32l475ve.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475ve.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l475vg.rs b/embassy-stm32/src/pac/stm32l475vg.rs new file mode 100644 index 00000000..4a6d511f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l475vg.rs @@ -0,0 +1,639 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476je.rs b/embassy-stm32/src/pac/stm32l476je.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476je.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476jg.rs b/embassy-stm32/src/pac/stm32l476jg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476jg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476me.rs b/embassy-stm32/src/pac/stm32l476me.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476me.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476mg.rs b/embassy-stm32/src/pac/stm32l476mg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476mg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476qe.rs b/embassy-stm32/src/pac/stm32l476qe.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476qe.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476qg.rs b/embassy-stm32/src/pac/stm32l476qg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476qg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476rc.rs b/embassy-stm32/src/pac/stm32l476rc.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476rc.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476re.rs b/embassy-stm32/src/pac/stm32l476re.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476re.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476rg.rs b/embassy-stm32/src/pac/stm32l476rg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476rg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476vc.rs b/embassy-stm32/src/pac/stm32l476vc.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476vc.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476ve.rs b/embassy-stm32/src/pac/stm32l476ve.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476ve.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476vg.rs b/embassy-stm32/src/pac/stm32l476vg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476vg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476ze.rs b/embassy-stm32/src/pac/stm32l476ze.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476ze.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l476zg.rs b/embassy-stm32/src/pac/stm32l476zg.rs new file mode 100644 index 00000000..6ab0659f --- /dev/null +++ b/embassy-stm32/src/pac/stm32l476zg.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l485jc.rs b/embassy-stm32/src/pac/stm32l485jc.rs new file mode 100644 index 00000000..028c2503 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l485jc.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l485je.rs b/embassy-stm32/src/pac/stm32l485je.rs new file mode 100644 index 00000000..028c2503 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l485je.rs @@ -0,0 +1,642 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486jg.rs b/embassy-stm32/src/pac/stm32l486jg.rs new file mode 100644 index 00000000..78cf49a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486jg.rs @@ -0,0 +1,645 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486qg.rs b/embassy-stm32/src/pac/stm32l486qg.rs new file mode 100644 index 00000000..78cf49a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486qg.rs @@ -0,0 +1,645 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486rg.rs b/embassy-stm32/src/pac/stm32l486rg.rs new file mode 100644 index 00000000..78cf49a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486rg.rs @@ -0,0 +1,645 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486vg.rs b/embassy-stm32/src/pac/stm32l486vg.rs new file mode 100644 index 00000000..78cf49a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486vg.rs @@ -0,0 +1,645 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l486zg.rs b/embassy-stm32/src/pac/stm32l486zg.rs new file mode 100644 index 00000000..78cf49a5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l486zg.rs @@ -0,0 +1,645 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 82] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ae.rs b/embassy-stm32/src/pac/stm32l496ae.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ae.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ag.rs b/embassy-stm32/src/pac/stm32l496ag.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ag.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496qe.rs b/embassy-stm32/src/pac/stm32l496qe.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496qe.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496qg.rs b/embassy-stm32/src/pac/stm32l496qg.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496qg.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496re.rs b/embassy-stm32/src/pac/stm32l496re.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496re.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496rg.rs b/embassy-stm32/src/pac/stm32l496rg.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496rg.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ve.rs b/embassy-stm32/src/pac/stm32l496ve.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ve.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496vg.rs b/embassy-stm32/src/pac/stm32l496vg.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496vg.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496wg.rs b/embassy-stm32/src/pac/stm32l496wg.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496wg.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496ze.rs b/embassy-stm32/src/pac/stm32l496ze.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496ze.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l496zg.rs b/embassy-stm32/src/pac/stm32l496zg.rs new file mode 100644 index 00000000..7d569ed5 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l496zg.rs @@ -0,0 +1,744 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6ag.rs b/embassy-stm32/src/pac/stm32l4a6ag.rs new file mode 100644 index 00000000..b28bbe80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6ag.rs @@ -0,0 +1,747 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6qg.rs b/embassy-stm32/src/pac/stm32l4a6qg.rs new file mode 100644 index 00000000..b28bbe80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6qg.rs @@ -0,0 +1,747 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6rg.rs b/embassy-stm32/src/pac/stm32l4a6rg.rs new file mode 100644 index 00000000..b28bbe80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6rg.rs @@ -0,0 +1,747 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6vg.rs b/embassy-stm32/src/pac/stm32l4a6vg.rs new file mode 100644 index 00000000..b28bbe80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6vg.rs @@ -0,0 +1,747 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4a6zg.rs b/embassy-stm32/src/pac/stm32l4a6zg.rs new file mode 100644 index 00000000..b28bbe80 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4a6zg.rs @@ -0,0 +1,747 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, HASH_RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub const USART1: usart::Usart = usart::Usart(0x40013800 as _); +impl_usart!(USART1); +impl_usart_pin!(USART1, RxPin, PA10, 7); +impl_usart_pin!(USART1, CtsPin, PA11, 7); +impl_usart_pin!(USART1, RtsPin, PA12, 7); +impl_usart_pin!(USART1, CkPin, PA8, 7); +impl_usart_pin!(USART1, TxPin, PA9, 7); +impl_usart_pin!(USART1, RtsPin, PB3, 7); +impl_usart_pin!(USART1, CtsPin, PB4, 7); +impl_usart_pin!(USART1, CkPin, PB5, 7); +impl_usart_pin!(USART1, TxPin, PB6, 7); +impl_usart_pin!(USART1, RxPin, PB7, 7); +impl_usart_pin!(USART1, RxPin, PG10, 7); +impl_usart_pin!(USART1, CtsPin, PG11, 7); +impl_usart_pin!(USART1, RtsPin, PG12, 7); +impl_usart_pin!(USART1, CkPin, PG13, 7); +impl_usart_pin!(USART1, TxPin, PG9, 7); +pub const USART2: usart::Usart = usart::Usart(0x40004400 as _); +impl_usart!(USART2); +impl_usart_pin!(USART2, CtsPin, PA0, 7); +impl_usart_pin!(USART2, RtsPin, PA1, 7); +impl_usart_pin!(USART2, RxPin, PA15, 3); +impl_usart_pin!(USART2, TxPin, PA2, 7); +impl_usart_pin!(USART2, RxPin, PA3, 7); +impl_usart_pin!(USART2, CkPin, PA4, 7); +impl_usart_pin!(USART2, CtsPin, PD3, 7); +impl_usart_pin!(USART2, RtsPin, PD4, 7); +impl_usart_pin!(USART2, TxPin, PD5, 7); +impl_usart_pin!(USART2, RxPin, PD6, 7); +impl_usart_pin!(USART2, CkPin, PD7, 7); +pub const USART3: usart::Usart = usart::Usart(0x40004800 as _); +impl_usart!(USART3); +impl_usart_pin!(USART3, RtsPin, PA15, 7); +impl_usart_pin!(USART3, CtsPin, PA6, 7); +impl_usart_pin!(USART3, CkPin, PB0, 7); +impl_usart_pin!(USART3, RtsPin, PB1, 7); +impl_usart_pin!(USART3, TxPin, PB10, 7); +impl_usart_pin!(USART3, RxPin, PB11, 7); +impl_usart_pin!(USART3, CkPin, PB12, 7); +impl_usart_pin!(USART3, CtsPin, PB13, 7); +impl_usart_pin!(USART3, RtsPin, PB14, 7); +impl_usart_pin!(USART3, TxPin, PC10, 7); +impl_usart_pin!(USART3, RxPin, PC11, 7); +impl_usart_pin!(USART3, CkPin, PC12, 7); +impl_usart_pin!(USART3, TxPin, PC4, 7); +impl_usart_pin!(USART3, RxPin, PC5, 7); +impl_usart_pin!(USART3, CkPin, PD10, 7); +impl_usart_pin!(USART3, CtsPin, PD11, 7); +impl_usart_pin!(USART3, RtsPin, PD12, 7); +impl_usart_pin!(USART3, RtsPin, PD2, 7); +impl_usart_pin!(USART3, TxPin, PD8, 7); +impl_usart_pin!(USART3, RxPin, PD9, 7); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +pub use regs::usart_v2 as usart; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3 +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + ADC3 = 47, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + CAN2_RX0 = 87, + CAN2_RX1 = 88, + CAN2_SCE = 89, + CAN2_TX = 86, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_RNG = 80, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 84, + I2C4_EV = 83, + LCD = 78, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OTG_FS = 67, + PVD_PVM = 1, + QUADSPI = 71, + RCC = 5, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + SWPMI1 = 76, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(ADC3); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(CAN2_RX0); + declare!(CAN2_RX1); + declare!(CAN2_SCE); + declare!(CAN2_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_RNG); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LCD); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(QUADSPI); + declare!(RCC); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(SWPMI1); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn ADC3(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn CAN2_RX0(); + fn CAN2_RX1(); + fn CAN2_SCE(); + fn CAN2_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_RNG(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LCD(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OTG_FS(); + fn PVD_PVM(); + fn QUADSPI(); + fn RCC(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn SWPMI1(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 91] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: ADC3 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: QUADSPI }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: SWPMI1 }, + Vector { _handler: TSC }, + Vector { _handler: LCD }, + Vector { _handler: AES }, + Vector { _handler: HASH_RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_EV }, + Vector { _handler: I2C4_ER }, + Vector { _handler: DCMI }, + Vector { _handler: CAN2_TX }, + Vector { _handler: CAN2_RX0 }, + Vector { _handler: CAN2_RX1 }, + Vector { _handler: CAN2_SCE }, + Vector { _handler: DMA2D }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ae.rs b/embassy-stm32/src/pac/stm32l4p5ae.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ae.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ag.rs b/embassy-stm32/src/pac/stm32l4p5ag.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ag.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ce.rs b/embassy-stm32/src/pac/stm32l4p5ce.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ce.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5cg.rs b/embassy-stm32/src/pac/stm32l4p5cg.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5cg.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5qe.rs b/embassy-stm32/src/pac/stm32l4p5qe.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5qe.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5qg.rs b/embassy-stm32/src/pac/stm32l4p5qg.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5qg.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5re.rs b/embassy-stm32/src/pac/stm32l4p5re.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5re.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5rg.rs b/embassy-stm32/src/pac/stm32l4p5rg.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5rg.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ve.rs b/embassy-stm32/src/pac/stm32l4p5ve.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ve.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5vg.rs b/embassy-stm32/src/pac/stm32l4p5vg.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5vg.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5ze.rs b/embassy-stm32/src/pac/stm32l4p5ze.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5ze.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4p5zg.rs b/embassy-stm32/src/pac/stm32l4p5zg.rs new file mode 100644 index 00000000..e5554d64 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4p5zg.rs @@ -0,0 +1,684 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5ag.rs b/embassy-stm32/src/pac/stm32l4q5ag.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5ag.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5cg.rs b/embassy-stm32/src/pac/stm32l4q5cg.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5cg.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5qg.rs b/embassy-stm32/src/pac/stm32l4q5qg.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5qg.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5rg.rs b/embassy-stm32/src/pac/stm32l4q5rg.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5rg.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5vg.rs b/embassy-stm32/src/pac/stm32l4q5vg.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5vg.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4q5zg.rs b/embassy-stm32/src/pac/stm32l4q5zg.rs new file mode 100644 index 00000000..b60fa840 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4q5zg.rs @@ -0,0 +1,690 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1_2 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI_PSSI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PKA = 86, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SDMMC2 = 47, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1_2); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI_PSSI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PKA); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SDMMC2); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1_2(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI_PSSI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PKA(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SDMMC2(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1_2 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { _reserved: 0 }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _handler: SDMMC2 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { _reserved: 0 }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { + _handler: DCMI_PSSI, + }, + Vector { _handler: PKA }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5ag.rs b/embassy-stm32/src/pac/stm32l4r5ag.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5ag.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5ai.rs b/embassy-stm32/src/pac/stm32l4r5ai.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5ai.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5qg.rs b/embassy-stm32/src/pac/stm32l4r5qg.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5qg.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5qi.rs b/embassy-stm32/src/pac/stm32l4r5qi.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5qi.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5vg.rs b/embassy-stm32/src/pac/stm32l4r5vg.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5vg.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5vi.rs b/embassy-stm32/src/pac/stm32l4r5vi.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5vi.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5zg.rs b/embassy-stm32/src/pac/stm32l4r5zg.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5zg.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r5zi.rs b/embassy-stm32/src/pac/stm32l4r5zi.rs new file mode 100644 index 00000000..5d6d3b8a --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r5zi.rs @@ -0,0 +1,683 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7ai.rs b/embassy-stm32/src/pac/stm32l4r7ai.rs new file mode 100644 index 00000000..ce8e20c9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7ai.rs @@ -0,0 +1,692 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7vi.rs b/embassy-stm32/src/pac/stm32l4r7vi.rs new file mode 100644 index 00000000..ce8e20c9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7vi.rs @@ -0,0 +1,692 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r7zi.rs b/embassy-stm32/src/pac/stm32l4r7zi.rs new file mode 100644 index 00000000..ce8e20c9 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r7zi.rs @@ -0,0 +1,692 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9ag.rs b/embassy-stm32/src/pac/stm32l4r9ag.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9ag.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9ai.rs b/embassy-stm32/src/pac/stm32l4r9ai.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9ai.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9vg.rs b/embassy-stm32/src/pac/stm32l4r9vg.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9vg.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9vi.rs b/embassy-stm32/src/pac/stm32l4r9vi.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9vi.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9zg.rs b/embassy-stm32/src/pac/stm32l4r9zg.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9zg.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4r9zi.rs b/embassy-stm32/src/pac/stm32l4r9zi.rs new file mode 100644 index 00000000..8dc7f9aa --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4r9zi.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + CRS = 82, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(CRS); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn CRS(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _reserved: 0 }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5ai.rs b/embassy-stm32/src/pac/stm32l4s5ai.rs new file mode 100644 index 00000000..1b8ae228 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5ai.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5qi.rs b/embassy-stm32/src/pac/stm32l4s5qi.rs new file mode 100644 index 00000000..1b8ae228 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5qi.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5vi.rs b/embassy-stm32/src/pac/stm32l4s5vi.rs new file mode 100644 index 00000000..1b8ae228 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5vi.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s5zi.rs b/embassy-stm32/src/pac/stm32l4s5zi.rs new file mode 100644 index 00000000..1b8ae228 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s5zi.rs @@ -0,0 +1,686 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7ai.rs b/embassy-stm32/src/pac/stm32l4s7ai.rs new file mode 100644 index 00000000..8758dc15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7ai.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7vi.rs b/embassy-stm32/src/pac/stm32l4s7vi.rs new file mode 100644 index 00000000..8758dc15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7vi.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s7zi.rs b/embassy-stm32/src/pac/stm32l4s7zi.rs new file mode 100644 index 00000000..8758dc15 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s7zi.rs @@ -0,0 +1,695 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _reserved: 0 }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9ai.rs b/embassy-stm32/src/pac/stm32l4s9ai.rs new file mode 100644 index 00000000..8daaab62 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9ai.rs @@ -0,0 +1,698 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9vi.rs b/embassy-stm32/src/pac/stm32l4s9vi.rs new file mode 100644 index 00000000..8daaab62 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9vi.rs @@ -0,0 +1,698 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/pac/stm32l4s9zi.rs b/embassy-stm32/src/pac/stm32l4s9zi.rs new file mode 100644 index 00000000..8daaab62 --- /dev/null +++ b/embassy-stm32/src/pac/stm32l4s9zi.rs @@ -0,0 +1,698 @@ +#![allow(dead_code)] +#![allow(unused_imports)] +#![allow(non_snake_case)] + +pub fn GPIO(n: usize) -> gpio::Gpio { + gpio::Gpio((0x48000000 + 0x400 * n) as _) +} +pub const DMA1: dma::Dma = dma::Dma(0x40020000 as _); +impl_dma_channel!(DMA1_CH0, 0, 0); +impl_dma_channel!(DMA1_CH1, 0, 1); +impl_dma_channel!(DMA1_CH2, 0, 2); +impl_dma_channel!(DMA1_CH3, 0, 3); +impl_dma_channel!(DMA1_CH4, 0, 4); +impl_dma_channel!(DMA1_CH5, 0, 5); +impl_dma_channel!(DMA1_CH6, 0, 6); +impl_dma_channel!(DMA1_CH7, 0, 7); +pub const DMA2: dma::Dma = dma::Dma(0x40020400 as _); +impl_dma_channel!(DMA2_CH0, 1, 0); +impl_dma_channel!(DMA2_CH1, 1, 1); +impl_dma_channel!(DMA2_CH2, 1, 2); +impl_dma_channel!(DMA2_CH3, 1, 3); +impl_dma_channel!(DMA2_CH4, 1, 4); +impl_dma_channel!(DMA2_CH5, 1, 5); +impl_dma_channel!(DMA2_CH6, 1, 6); +impl_dma_channel!(DMA2_CH7, 1, 7); +pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _); +pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _); +impl_gpio_pin!(PA0, 0, 0, EXTI0); +impl_gpio_pin!(PA1, 0, 1, EXTI1); +impl_gpio_pin!(PA2, 0, 2, EXTI2); +impl_gpio_pin!(PA3, 0, 3, EXTI3); +impl_gpio_pin!(PA4, 0, 4, EXTI4); +impl_gpio_pin!(PA5, 0, 5, EXTI5); +impl_gpio_pin!(PA6, 0, 6, EXTI6); +impl_gpio_pin!(PA7, 0, 7, EXTI7); +impl_gpio_pin!(PA8, 0, 8, EXTI8); +impl_gpio_pin!(PA9, 0, 9, EXTI9); +impl_gpio_pin!(PA10, 0, 10, EXTI10); +impl_gpio_pin!(PA11, 0, 11, EXTI11); +impl_gpio_pin!(PA12, 0, 12, EXTI12); +impl_gpio_pin!(PA13, 0, 13, EXTI13); +impl_gpio_pin!(PA14, 0, 14, EXTI14); +impl_gpio_pin!(PA15, 0, 15, EXTI15); +pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _); +impl_gpio_pin!(PB0, 1, 0, EXTI0); +impl_gpio_pin!(PB1, 1, 1, EXTI1); +impl_gpio_pin!(PB2, 1, 2, EXTI2); +impl_gpio_pin!(PB3, 1, 3, EXTI3); +impl_gpio_pin!(PB4, 1, 4, EXTI4); +impl_gpio_pin!(PB5, 1, 5, EXTI5); +impl_gpio_pin!(PB6, 1, 6, EXTI6); +impl_gpio_pin!(PB7, 1, 7, EXTI7); +impl_gpio_pin!(PB8, 1, 8, EXTI8); +impl_gpio_pin!(PB9, 1, 9, EXTI9); +impl_gpio_pin!(PB10, 1, 10, EXTI10); +impl_gpio_pin!(PB11, 1, 11, EXTI11); +impl_gpio_pin!(PB12, 1, 12, EXTI12); +impl_gpio_pin!(PB13, 1, 13, EXTI13); +impl_gpio_pin!(PB14, 1, 14, EXTI14); +impl_gpio_pin!(PB15, 1, 15, EXTI15); +pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _); +impl_gpio_pin!(PC0, 2, 0, EXTI0); +impl_gpio_pin!(PC1, 2, 1, EXTI1); +impl_gpio_pin!(PC2, 2, 2, EXTI2); +impl_gpio_pin!(PC3, 2, 3, EXTI3); +impl_gpio_pin!(PC4, 2, 4, EXTI4); +impl_gpio_pin!(PC5, 2, 5, EXTI5); +impl_gpio_pin!(PC6, 2, 6, EXTI6); +impl_gpio_pin!(PC7, 2, 7, EXTI7); +impl_gpio_pin!(PC8, 2, 8, EXTI8); +impl_gpio_pin!(PC9, 2, 9, EXTI9); +impl_gpio_pin!(PC10, 2, 10, EXTI10); +impl_gpio_pin!(PC11, 2, 11, EXTI11); +impl_gpio_pin!(PC12, 2, 12, EXTI12); +impl_gpio_pin!(PC13, 2, 13, EXTI13); +impl_gpio_pin!(PC14, 2, 14, EXTI14); +impl_gpio_pin!(PC15, 2, 15, EXTI15); +pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _); +impl_gpio_pin!(PD0, 3, 0, EXTI0); +impl_gpio_pin!(PD1, 3, 1, EXTI1); +impl_gpio_pin!(PD2, 3, 2, EXTI2); +impl_gpio_pin!(PD3, 3, 3, EXTI3); +impl_gpio_pin!(PD4, 3, 4, EXTI4); +impl_gpio_pin!(PD5, 3, 5, EXTI5); +impl_gpio_pin!(PD6, 3, 6, EXTI6); +impl_gpio_pin!(PD7, 3, 7, EXTI7); +impl_gpio_pin!(PD8, 3, 8, EXTI8); +impl_gpio_pin!(PD9, 3, 9, EXTI9); +impl_gpio_pin!(PD10, 3, 10, EXTI10); +impl_gpio_pin!(PD11, 3, 11, EXTI11); +impl_gpio_pin!(PD12, 3, 12, EXTI12); +impl_gpio_pin!(PD13, 3, 13, EXTI13); +impl_gpio_pin!(PD14, 3, 14, EXTI14); +impl_gpio_pin!(PD15, 3, 15, EXTI15); +pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _); +impl_gpio_pin!(PE0, 4, 0, EXTI0); +impl_gpio_pin!(PE1, 4, 1, EXTI1); +impl_gpio_pin!(PE2, 4, 2, EXTI2); +impl_gpio_pin!(PE3, 4, 3, EXTI3); +impl_gpio_pin!(PE4, 4, 4, EXTI4); +impl_gpio_pin!(PE5, 4, 5, EXTI5); +impl_gpio_pin!(PE6, 4, 6, EXTI6); +impl_gpio_pin!(PE7, 4, 7, EXTI7); +impl_gpio_pin!(PE8, 4, 8, EXTI8); +impl_gpio_pin!(PE9, 4, 9, EXTI9); +impl_gpio_pin!(PE10, 4, 10, EXTI10); +impl_gpio_pin!(PE11, 4, 11, EXTI11); +impl_gpio_pin!(PE12, 4, 12, EXTI12); +impl_gpio_pin!(PE13, 4, 13, EXTI13); +impl_gpio_pin!(PE14, 4, 14, EXTI14); +impl_gpio_pin!(PE15, 4, 15, EXTI15); +pub const GPIOF: gpio::Gpio = gpio::Gpio(0x48001400 as _); +impl_gpio_pin!(PF0, 5, 0, EXTI0); +impl_gpio_pin!(PF1, 5, 1, EXTI1); +impl_gpio_pin!(PF2, 5, 2, EXTI2); +impl_gpio_pin!(PF3, 5, 3, EXTI3); +impl_gpio_pin!(PF4, 5, 4, EXTI4); +impl_gpio_pin!(PF5, 5, 5, EXTI5); +impl_gpio_pin!(PF6, 5, 6, EXTI6); +impl_gpio_pin!(PF7, 5, 7, EXTI7); +impl_gpio_pin!(PF8, 5, 8, EXTI8); +impl_gpio_pin!(PF9, 5, 9, EXTI9); +impl_gpio_pin!(PF10, 5, 10, EXTI10); +impl_gpio_pin!(PF11, 5, 11, EXTI11); +impl_gpio_pin!(PF12, 5, 12, EXTI12); +impl_gpio_pin!(PF13, 5, 13, EXTI13); +impl_gpio_pin!(PF14, 5, 14, EXTI14); +impl_gpio_pin!(PF15, 5, 15, EXTI15); +pub const GPIOG: gpio::Gpio = gpio::Gpio(0x48001800 as _); +impl_gpio_pin!(PG0, 6, 0, EXTI0); +impl_gpio_pin!(PG1, 6, 1, EXTI1); +impl_gpio_pin!(PG2, 6, 2, EXTI2); +impl_gpio_pin!(PG3, 6, 3, EXTI3); +impl_gpio_pin!(PG4, 6, 4, EXTI4); +impl_gpio_pin!(PG5, 6, 5, EXTI5); +impl_gpio_pin!(PG6, 6, 6, EXTI6); +impl_gpio_pin!(PG7, 6, 7, EXTI7); +impl_gpio_pin!(PG8, 6, 8, EXTI8); +impl_gpio_pin!(PG9, 6, 9, EXTI9); +impl_gpio_pin!(PG10, 6, 10, EXTI10); +impl_gpio_pin!(PG11, 6, 11, EXTI11); +impl_gpio_pin!(PG12, 6, 12, EXTI12); +impl_gpio_pin!(PG13, 6, 13, EXTI13); +impl_gpio_pin!(PG14, 6, 14, EXTI14); +impl_gpio_pin!(PG15, 6, 15, EXTI15); +pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _); +impl_gpio_pin!(PH0, 7, 0, EXTI0); +impl_gpio_pin!(PH1, 7, 1, EXTI1); +impl_gpio_pin!(PH2, 7, 2, EXTI2); +impl_gpio_pin!(PH3, 7, 3, EXTI3); +impl_gpio_pin!(PH4, 7, 4, EXTI4); +impl_gpio_pin!(PH5, 7, 5, EXTI5); +impl_gpio_pin!(PH6, 7, 6, EXTI6); +impl_gpio_pin!(PH7, 7, 7, EXTI7); +impl_gpio_pin!(PH8, 7, 8, EXTI8); +impl_gpio_pin!(PH9, 7, 9, EXTI9); +impl_gpio_pin!(PH10, 7, 10, EXTI10); +impl_gpio_pin!(PH11, 7, 11, EXTI11); +impl_gpio_pin!(PH12, 7, 12, EXTI12); +impl_gpio_pin!(PH13, 7, 13, EXTI13); +impl_gpio_pin!(PH14, 7, 14, EXTI14); +impl_gpio_pin!(PH15, 7, 15, EXTI15); +pub const GPIOI: gpio::Gpio = gpio::Gpio(0x48002000 as _); +impl_gpio_pin!(PI0, 8, 0, EXTI0); +impl_gpio_pin!(PI1, 8, 1, EXTI1); +impl_gpio_pin!(PI2, 8, 2, EXTI2); +impl_gpio_pin!(PI3, 8, 3, EXTI3); +impl_gpio_pin!(PI4, 8, 4, EXTI4); +impl_gpio_pin!(PI5, 8, 5, EXTI5); +impl_gpio_pin!(PI6, 8, 6, EXTI6); +impl_gpio_pin!(PI7, 8, 7, EXTI7); +impl_gpio_pin!(PI8, 8, 8, EXTI8); +impl_gpio_pin!(PI9, 8, 9, EXTI9); +impl_gpio_pin!(PI10, 8, 10, EXTI10); +impl_gpio_pin!(PI11, 8, 11, EXTI11); +impl_gpio_pin!(PI12, 8, 12, EXTI12); +impl_gpio_pin!(PI13, 8, 13, EXTI13); +impl_gpio_pin!(PI14, 8, 14, EXTI14); +impl_gpio_pin!(PI15, 8, 15, EXTI15); +pub const RNG: rng::Rng = rng::Rng(0x50060800 as _); +impl_rng!(RNG, RNG); +pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _); +impl_spi!(SPI1, APB2); +impl_spi_pin!(SPI1, SckPin, PA1, 5); +impl_spi_pin!(SPI1, MisoPin, PA11, 5); +impl_spi_pin!(SPI1, MosiPin, PA12, 5); +impl_spi_pin!(SPI1, SckPin, PA5, 5); +impl_spi_pin!(SPI1, MisoPin, PA6, 5); +impl_spi_pin!(SPI1, MosiPin, PA7, 5); +impl_spi_pin!(SPI1, SckPin, PB3, 5); +impl_spi_pin!(SPI1, MisoPin, PB4, 5); +impl_spi_pin!(SPI1, MosiPin, PB5, 5); +impl_spi_pin!(SPI1, SckPin, PE13, 5); +impl_spi_pin!(SPI1, MisoPin, PE14, 5); +impl_spi_pin!(SPI1, MosiPin, PE15, 5); +impl_spi_pin!(SPI1, SckPin, PG2, 5); +impl_spi_pin!(SPI1, MisoPin, PG3, 5); +impl_spi_pin!(SPI1, MosiPin, PG4, 5); +pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _); +impl_spi!(SPI2, APB1); +impl_spi_pin!(SPI2, SckPin, PA9, 3); +impl_spi_pin!(SPI2, SckPin, PB10, 5); +impl_spi_pin!(SPI2, SckPin, PB13, 5); +impl_spi_pin!(SPI2, MisoPin, PB14, 5); +impl_spi_pin!(SPI2, MosiPin, PB15, 5); +impl_spi_pin!(SPI2, MosiPin, PC1, 3); +impl_spi_pin!(SPI2, MisoPin, PC2, 5); +impl_spi_pin!(SPI2, MosiPin, PC3, 5); +impl_spi_pin!(SPI2, SckPin, PD1, 5); +impl_spi_pin!(SPI2, SckPin, PD3, 3); +impl_spi_pin!(SPI2, MisoPin, PD3, 5); +impl_spi_pin!(SPI2, MosiPin, PD4, 5); +impl_spi_pin!(SPI2, SckPin, PI1, 5); +impl_spi_pin!(SPI2, MisoPin, PI2, 5); +impl_spi_pin!(SPI2, MosiPin, PI3, 5); +pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _); +impl_spi!(SPI3, APB1); +impl_spi_pin!(SPI3, SckPin, PB3, 6); +impl_spi_pin!(SPI3, MisoPin, PB4, 6); +impl_spi_pin!(SPI3, MosiPin, PB5, 6); +impl_spi_pin!(SPI3, SckPin, PC10, 6); +impl_spi_pin!(SPI3, MisoPin, PC11, 6); +impl_spi_pin!(SPI3, MosiPin, PC12, 6); +impl_spi_pin!(SPI3, MosiPin, PD6, 5); +impl_spi_pin!(SPI3, MisoPin, PG10, 6); +impl_spi_pin!(SPI3, MosiPin, PG11, 6); +impl_spi_pin!(SPI3, SckPin, PG9, 6); +pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _); +pub use regs::dma_v1 as dma; +pub use regs::exti_v1 as exti; +pub use regs::gpio_v2 as gpio; +pub use regs::rng_v1 as rng; +pub use regs::spi_v2 as spi; +pub use regs::syscfg_l4 as syscfg; +mod regs; +use embassy_extras::peripherals; +pub use regs::generic; +peripherals!( + EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12, + EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6, + DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI, + PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1, + PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3, + PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5, + PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9, + PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10, + PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, + PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12, + PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG +); + +pub mod interrupt { + pub use cortex_m::interrupt::{CriticalSection, Mutex}; + pub use embassy::interrupt::{declare, take, Interrupt}; + pub use embassy_extras::interrupt::Priority4 as Priority; + + #[derive(Copy, Clone, Debug, PartialEq, Eq)] + #[allow(non_camel_case_types)] + pub enum InterruptEnum { + ADC1 = 18, + AES = 79, + CAN1_RX0 = 20, + CAN1_RX1 = 21, + CAN1_SCE = 22, + CAN1_TX = 19, + COMP = 64, + DCMI = 85, + DFSDM1_FLT0 = 61, + DFSDM1_FLT1 = 62, + DFSDM1_FLT2 = 63, + DFSDM1_FLT3 = 42, + DMA1_Channel1 = 11, + DMA1_Channel2 = 12, + DMA1_Channel3 = 13, + DMA1_Channel4 = 14, + DMA1_Channel5 = 15, + DMA1_Channel6 = 16, + DMA1_Channel7 = 17, + DMA2D = 90, + DMA2_Channel1 = 56, + DMA2_Channel2 = 57, + DMA2_Channel3 = 58, + DMA2_Channel4 = 59, + DMA2_Channel5 = 60, + DMA2_Channel6 = 68, + DMA2_Channel7 = 69, + DMAMUX1_OVR = 94, + DSI = 78, + EXTI0 = 6, + EXTI1 = 7, + EXTI15_10 = 40, + EXTI2 = 8, + EXTI3 = 9, + EXTI4 = 10, + EXTI9_5 = 23, + FLASH = 4, + FMC = 48, + FPU = 81, + GFXMMU = 93, + HASH_CRS = 82, + I2C1_ER = 32, + I2C1_EV = 31, + I2C2_ER = 34, + I2C2_EV = 33, + I2C3_ER = 73, + I2C3_EV = 72, + I2C4_ER = 83, + I2C4_EV = 84, + LPTIM1 = 65, + LPTIM2 = 66, + LPUART1 = 70, + LTDC = 91, + LTDC_ER = 92, + OCTOSPI1 = 71, + OCTOSPI2 = 76, + OTG_FS = 67, + PVD_PVM = 1, + RCC = 5, + RNG = 80, + RTC_Alarm = 41, + RTC_WKUP = 3, + SAI1 = 74, + SAI2 = 75, + SDMMC1 = 49, + SPI1 = 35, + SPI2 = 36, + SPI3 = 51, + TAMP_STAMP = 2, + TIM1_BRK_TIM15 = 24, + TIM1_CC = 27, + TIM1_TRG_COM_TIM17 = 26, + TIM1_UP_TIM16 = 25, + TIM2 = 28, + TIM3 = 29, + TIM4 = 30, + TIM5 = 50, + TIM6_DAC = 54, + TIM7 = 55, + TIM8_BRK = 43, + TIM8_CC = 46, + TIM8_TRG_COM = 45, + TIM8_UP = 44, + TSC = 77, + UART4 = 52, + UART5 = 53, + USART1 = 37, + USART2 = 38, + USART3 = 39, + WWDG = 0, + } + unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } + } + + declare!(ADC1); + declare!(AES); + declare!(CAN1_RX0); + declare!(CAN1_RX1); + declare!(CAN1_SCE); + declare!(CAN1_TX); + declare!(COMP); + declare!(DCMI); + declare!(DFSDM1_FLT0); + declare!(DFSDM1_FLT1); + declare!(DFSDM1_FLT2); + declare!(DFSDM1_FLT3); + declare!(DMA1_Channel1); + declare!(DMA1_Channel2); + declare!(DMA1_Channel3); + declare!(DMA1_Channel4); + declare!(DMA1_Channel5); + declare!(DMA1_Channel6); + declare!(DMA1_Channel7); + declare!(DMA2D); + declare!(DMA2_Channel1); + declare!(DMA2_Channel2); + declare!(DMA2_Channel3); + declare!(DMA2_Channel4); + declare!(DMA2_Channel5); + declare!(DMA2_Channel6); + declare!(DMA2_Channel7); + declare!(DMAMUX1_OVR); + declare!(DSI); + declare!(EXTI0); + declare!(EXTI1); + declare!(EXTI15_10); + declare!(EXTI2); + declare!(EXTI3); + declare!(EXTI4); + declare!(EXTI9_5); + declare!(FLASH); + declare!(FMC); + declare!(FPU); + declare!(GFXMMU); + declare!(HASH_CRS); + declare!(I2C1_ER); + declare!(I2C1_EV); + declare!(I2C2_ER); + declare!(I2C2_EV); + declare!(I2C3_ER); + declare!(I2C3_EV); + declare!(I2C4_ER); + declare!(I2C4_EV); + declare!(LPTIM1); + declare!(LPTIM2); + declare!(LPUART1); + declare!(LTDC); + declare!(LTDC_ER); + declare!(OCTOSPI1); + declare!(OCTOSPI2); + declare!(OTG_FS); + declare!(PVD_PVM); + declare!(RCC); + declare!(RNG); + declare!(RTC_Alarm); + declare!(RTC_WKUP); + declare!(SAI1); + declare!(SAI2); + declare!(SDMMC1); + declare!(SPI1); + declare!(SPI2); + declare!(SPI3); + declare!(TAMP_STAMP); + declare!(TIM1_BRK_TIM15); + declare!(TIM1_CC); + declare!(TIM1_TRG_COM_TIM17); + declare!(TIM1_UP_TIM16); + declare!(TIM2); + declare!(TIM3); + declare!(TIM4); + declare!(TIM5); + declare!(TIM6_DAC); + declare!(TIM7); + declare!(TIM8_BRK); + declare!(TIM8_CC); + declare!(TIM8_TRG_COM); + declare!(TIM8_UP); + declare!(TSC); + declare!(UART4); + declare!(UART5); + declare!(USART1); + declare!(USART2); + declare!(USART3); + declare!(WWDG); +} +mod interrupt_vector { + extern "C" { + fn ADC1(); + fn AES(); + fn CAN1_RX0(); + fn CAN1_RX1(); + fn CAN1_SCE(); + fn CAN1_TX(); + fn COMP(); + fn DCMI(); + fn DFSDM1_FLT0(); + fn DFSDM1_FLT1(); + fn DFSDM1_FLT2(); + fn DFSDM1_FLT3(); + fn DMA1_Channel1(); + fn DMA1_Channel2(); + fn DMA1_Channel3(); + fn DMA1_Channel4(); + fn DMA1_Channel5(); + fn DMA1_Channel6(); + fn DMA1_Channel7(); + fn DMA2D(); + fn DMA2_Channel1(); + fn DMA2_Channel2(); + fn DMA2_Channel3(); + fn DMA2_Channel4(); + fn DMA2_Channel5(); + fn DMA2_Channel6(); + fn DMA2_Channel7(); + fn DMAMUX1_OVR(); + fn DSI(); + fn EXTI0(); + fn EXTI1(); + fn EXTI15_10(); + fn EXTI2(); + fn EXTI3(); + fn EXTI4(); + fn EXTI9_5(); + fn FLASH(); + fn FMC(); + fn FPU(); + fn GFXMMU(); + fn HASH_CRS(); + fn I2C1_ER(); + fn I2C1_EV(); + fn I2C2_ER(); + fn I2C2_EV(); + fn I2C3_ER(); + fn I2C3_EV(); + fn I2C4_ER(); + fn I2C4_EV(); + fn LPTIM1(); + fn LPTIM2(); + fn LPUART1(); + fn LTDC(); + fn LTDC_ER(); + fn OCTOSPI1(); + fn OCTOSPI2(); + fn OTG_FS(); + fn PVD_PVM(); + fn RCC(); + fn RNG(); + fn RTC_Alarm(); + fn RTC_WKUP(); + fn SAI1(); + fn SAI2(); + fn SDMMC1(); + fn SPI1(); + fn SPI2(); + fn SPI3(); + fn TAMP_STAMP(); + fn TIM1_BRK_TIM15(); + fn TIM1_CC(); + fn TIM1_TRG_COM_TIM17(); + fn TIM1_UP_TIM16(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6_DAC(); + fn TIM7(); + fn TIM8_BRK(); + fn TIM8_CC(); + fn TIM8_TRG_COM(); + fn TIM8_UP(); + fn TSC(); + fn UART4(); + fn UART5(); + fn USART1(); + fn USART2(); + fn USART3(); + fn WWDG(); + } + pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, + } + #[link_section = ".vector_table.interrupts"] + #[no_mangle] + pub static __INTERRUPTS: [Vector; 95] = [ + Vector { _handler: WWDG }, + Vector { _handler: PVD_PVM }, + Vector { + _handler: TAMP_STAMP, + }, + Vector { _handler: RTC_WKUP }, + Vector { _handler: FLASH }, + Vector { _handler: RCC }, + Vector { _handler: EXTI0 }, + Vector { _handler: EXTI1 }, + Vector { _handler: EXTI2 }, + Vector { _handler: EXTI3 }, + Vector { _handler: EXTI4 }, + Vector { + _handler: DMA1_Channel1, + }, + Vector { + _handler: DMA1_Channel2, + }, + Vector { + _handler: DMA1_Channel3, + }, + Vector { + _handler: DMA1_Channel4, + }, + Vector { + _handler: DMA1_Channel5, + }, + Vector { + _handler: DMA1_Channel6, + }, + Vector { + _handler: DMA1_Channel7, + }, + Vector { _handler: ADC1 }, + Vector { _handler: CAN1_TX }, + Vector { _handler: CAN1_RX0 }, + Vector { _handler: CAN1_RX1 }, + Vector { _handler: CAN1_SCE }, + Vector { _handler: EXTI9_5 }, + Vector { + _handler: TIM1_BRK_TIM15, + }, + Vector { + _handler: TIM1_UP_TIM16, + }, + Vector { + _handler: TIM1_TRG_COM_TIM17, + }, + Vector { _handler: TIM1_CC }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: I2C1_EV }, + Vector { _handler: I2C1_ER }, + Vector { _handler: I2C2_EV }, + Vector { _handler: I2C2_ER }, + Vector { _handler: SPI1 }, + Vector { _handler: SPI2 }, + Vector { _handler: USART1 }, + Vector { _handler: USART2 }, + Vector { _handler: USART3 }, + Vector { + _handler: EXTI15_10, + }, + Vector { + _handler: RTC_Alarm, + }, + Vector { + _handler: DFSDM1_FLT3, + }, + Vector { _handler: TIM8_BRK }, + Vector { _handler: TIM8_UP }, + Vector { + _handler: TIM8_TRG_COM, + }, + Vector { _handler: TIM8_CC }, + Vector { _reserved: 0 }, + Vector { _handler: FMC }, + Vector { _handler: SDMMC1 }, + Vector { _handler: TIM5 }, + Vector { _handler: SPI3 }, + Vector { _handler: UART4 }, + Vector { _handler: UART5 }, + Vector { _handler: TIM6_DAC }, + Vector { _handler: TIM7 }, + Vector { + _handler: DMA2_Channel1, + }, + Vector { + _handler: DMA2_Channel2, + }, + Vector { + _handler: DMA2_Channel3, + }, + Vector { + _handler: DMA2_Channel4, + }, + Vector { + _handler: DMA2_Channel5, + }, + Vector { + _handler: DFSDM1_FLT0, + }, + Vector { + _handler: DFSDM1_FLT1, + }, + Vector { + _handler: DFSDM1_FLT2, + }, + Vector { _handler: COMP }, + Vector { _handler: LPTIM1 }, + Vector { _handler: LPTIM2 }, + Vector { _handler: OTG_FS }, + Vector { + _handler: DMA2_Channel6, + }, + Vector { + _handler: DMA2_Channel7, + }, + Vector { _handler: LPUART1 }, + Vector { _handler: OCTOSPI1 }, + Vector { _handler: I2C3_EV }, + Vector { _handler: I2C3_ER }, + Vector { _handler: SAI1 }, + Vector { _handler: SAI2 }, + Vector { _handler: OCTOSPI2 }, + Vector { _handler: TSC }, + Vector { _handler: DSI }, + Vector { _handler: AES }, + Vector { _handler: RNG }, + Vector { _handler: FPU }, + Vector { _handler: HASH_CRS }, + Vector { _handler: I2C4_ER }, + Vector { _handler: I2C4_EV }, + Vector { _handler: DCMI }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: DMA2D }, + Vector { _handler: LTDC }, + Vector { _handler: LTDC_ER }, + Vector { _handler: GFXMMU }, + Vector { + _handler: DMAMUX1_OVR, + }, + ]; +} diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs new file mode 100644 index 00000000..d1924d13 --- /dev/null +++ b/embassy-stm32/src/rng.rs @@ -0,0 +1,161 @@ +#![macro_use] + +use core::future::Future; +use core::task::Poll; +use embassy::traits; +use embassy::util::{AtomicWaker, Unborrow}; +use embassy_extras::unborrow; +use futures::future::poll_fn; +use rand_core::{CryptoRng, RngCore}; + +use crate::fmt::*; +use crate::pac; + +pub(crate) static RNG_WAKER: AtomicWaker = AtomicWaker::new(); + +pub enum Error { + SeedError, + ClockError, +} + +pub struct Random { + _inner: T, +} + +impl Random { + pub fn new(inner: impl Unborrow) -> Self { + unborrow!(inner); + let mut random = Self { _inner: inner }; + random.reset(); + random + } + + pub fn reset(&mut self) { + unsafe { + T::regs().cr().modify(|reg| { + reg.set_rngen(true); + reg.set_ie(true); + }); + T::regs().sr().modify(|reg| { + reg.set_seis(false); + reg.set_ceis(false); + }); + } + // Reference manual says to discard the first. + let _ = self.next_u32(); + } +} + +impl RngCore for Random { + fn next_u32(&mut self) -> u32 { + loop { + let bits = unsafe { T::regs().sr().read() }; + if bits.drdy() { + return unsafe { T::regs().dr().read() }; + } + } + } + + fn next_u64(&mut self) -> u64 { + let mut rand = self.next_u32() as u64; + rand |= (self.next_u32() as u64) << 32; + rand + } + + fn fill_bytes(&mut self, dest: &mut [u8]) { + for chunk in dest.chunks_mut(4) { + let rand = self.next_u32(); + for (slot, num) in chunk.iter_mut().zip(rand.to_be_bytes().iter()) { + *slot = *num + } + } + } + + fn try_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), rand_core::Error> { + self.fill_bytes(dest); + Ok(()) + } +} + +impl CryptoRng for Random {} + +impl traits::rng::Rng for Random { + type Error = Error; + #[rustfmt::skip] + type RngFuture<'a> where Self: 'a = impl Future>; + + fn fill_bytes<'a>(&'a mut self, dest: &'a mut [u8]) -> Self::RngFuture<'a> { + unsafe { + T::regs().cr().modify(|reg| { + reg.set_rngen(true); + }); + } + async move { + for chunk in dest.chunks_mut(4) { + poll_fn(|cx| { + RNG_WAKER.register(cx.waker()); + unsafe { + T::regs().cr().modify(|reg| { + reg.set_ie(true); + }); + } + + let bits = unsafe { T::regs().sr().read() }; + + if bits.drdy() { + Poll::Ready(Ok(())) + } else if bits.seis() { + self.reset(); + Poll::Ready(Err(Error::SeedError)) + } else if bits.ceis() { + self.reset(); + Poll::Ready(Err(Error::ClockError)) + } else { + Poll::Pending + } + }) + .await?; + let random_bytes = unsafe { T::regs().dr().read() }.to_be_bytes(); + for (dest, src) in chunk.iter_mut().zip(random_bytes.iter()) { + *dest = *src + } + } + Ok(()) + } + } +} + +pub(crate) mod sealed { + use super::*; + + pub trait Instance { + fn regs() -> pac::rng::Rng; + } +} + +pub trait Instance: sealed::Instance {} + +macro_rules! impl_rng { + ($inst:ident, $irq:ident) => { + impl crate::rng::sealed::Instance for peripherals::RNG { + fn regs() -> crate::pac::chip::rng::Rng { + crate::pac::RNG + } + } + + impl crate::rng::Instance for peripherals::RNG {} + + mod rng_irq { + use crate::interrupt; + + #[interrupt] + unsafe fn $irq() { + let bits = $crate::pac::RNG.sr().read(); + if bits.drdy() || bits.seis() || bits.ceis() { + $crate::pac::RNG.cr().write(|reg| reg.set_ie(false)); + $crate::rng::RNG_WAKER.wake(); + } + } + } + }; +} diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs new file mode 100644 index 00000000..6d62eaee --- /dev/null +++ b/embassy-stm32/src/sdmmc/mod.rs @@ -0,0 +1,7 @@ +#![macro_use] + +#[cfg_attr(feature = "_sdmmc_v1", path = "v1.rs")] +#[cfg_attr(feature = "_sdmmc_v2", path = "v2.rs")] +mod _version; + +pub use _version::*; diff --git a/embassy-stm32/src/sdmmc/v2.rs b/embassy-stm32/src/sdmmc/v2.rs new file mode 100644 index 00000000..a4da4be8 --- /dev/null +++ b/embassy-stm32/src/sdmmc/v2.rs @@ -0,0 +1,1578 @@ +#![macro_use] + +use core::default::Default; +use core::future::Future; +use core::marker::PhantomData; +use core::task::Poll; + +use embassy::interrupt::InterruptExt; +use embassy::util::{AtomicWaker, OnDrop, Unborrow}; +use embassy_extras::unborrow; +use futures::future::poll_fn; +use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID, CSD, OCR, SCR}; + +use crate::fmt::*; +use crate::pac; +use crate::pac::gpio::Gpio; +use crate::pac::interrupt::Interrupt; +use crate::pac::sdmmc::Sdmmc as RegBlock; +use crate::time::Hertz; + +/// The signalling scheme used on the SDMMC bus +#[non_exhaustive] +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Signalling { + SDR12, + SDR25, + SDR50, + SDR104, + DDR50, +} + +impl Default for Signalling { + fn default() -> Self { + Signalling::SDR12 + } +} + +#[repr(align(4))] +pub struct DataBlock([u8; 512]); + +/// Errors +#[non_exhaustive] +#[derive(Debug, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + Timeout, + SoftwareTimeout, + UnsupportedCardVersion, + UnsupportedCardType, + Crc, + DataCrcFail, + RxOverFlow, + NoCard, + BadClock, + SignalingSwitchFailed, + PeripheralBusy, +} + +/// A SD command +struct Cmd { + cmd: u8, + arg: u32, + resp: Response, +} + +#[derive(Clone, Copy, Debug, Default)] +/// SD Card +pub struct Card { + /// The type of this card + pub card_type: CardCapacity, + /// Operation Conditions Register + pub ocr: OCR, + /// Relative Card Address + pub rca: u32, + /// Card ID + pub cid: CID, + /// Card Specific Data + pub csd: CSD, + /// SD CARD Configuration Register + pub scr: SCR, + /// SD Status + pub status: SDStatus, +} +impl Card { + /// Size in bytes + pub fn size(&self) -> u64 { + // SDHC / SDXC / SDUC + u64::from(self.csd.block_count()) * 512 + } +} + +/// Indicates transfer direction +enum Dir { + CardToHost, + HostToCard, +} + +#[repr(u8)] +enum PowerCtrl { + Off = 0b00, + On = 0b11, +} + +#[repr(u32)] +#[allow(dead_code)] +#[allow(non_camel_case_types)] +enum CmdAppOper { + VOLTAGE_WINDOW_SD = 0x8010_0000, + HIGH_CAPACITY = 0x4000_0000, + SDMMC_STD_CAPACITY = 0x0000_0000, + SDMMC_CHECK_PATTERN = 0x0000_01AA, + SD_SWITCH_1_8V_CAPACITY = 0x0100_0000, +} + +#[derive(Eq, PartialEq, Copy, Clone)] +enum Response { + None = 0, + Short = 1, + Long = 3, +} + +/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to +/// `sdmmc_ck` in Hertz. +/// +/// Returns `(clk_div, clk_f)`, where `clk_div` is the divisor register +/// value and `clk_f` is the resulting new clock frequency. +fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(u16, Hertz), Error> { + match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck { + 0 | 1 => Ok((0, ker_ck)), + x @ 2..=2046 => { + let clk_div = ((x + 1) / 2) as u16; + let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2)); + + Ok((clk_div, clk)) + } + _ => Err(Error::BadClock), + } +} + +/// SDMMC configuration +/// +/// You should probably change the default clock values to match your configuration +/// +/// Default values: +/// hclk = 400_000_000 Hz +/// kernel_clk: 100_000_000 Hz +/// data_transfer_timeout: 5_000_000 +#[non_exhaustive] +pub struct Config { + /// AHB clock + pub hclk: Hertz, + /// SDMMC kernel clock + pub kernel_clk: Hertz, + /// The timeout to be set for data transfers, in card bus clock periods + pub data_transfer_timeout: u32, +} + +impl Default for Config { + fn default() -> Self { + Self { + hclk: Hertz(400_000_000), + kernel_clk: Hertz(100_000_000), + data_transfer_timeout: 5_000_000, + } + } +} + +/// Sdmmc device +pub struct Sdmmc<'d, T: Instance, P: Pins> { + sdmmc: PhantomData<&'d mut T>, + pins: P, + irq: T::Interrupt, + config: Config, + /// Current clock to card + clock: Hertz, + /// Current signalling scheme to card + signalling: Signalling, + /// Card + card: Option, +} + +impl<'d, T: Instance, P: Pins> Sdmmc<'d, T, P> { + /// # Safety + /// + /// Futures that borrow this type can't be leaked + #[inline(always)] + pub unsafe fn new( + _peripheral: impl Unborrow + 'd, + pins: impl Unborrow + 'd, + irq: impl Unborrow, + config: Config, + ) -> Self { + unborrow!(irq, pins); + pins.configure(); + + let inner = T::inner(); + let clock = inner.new_inner(config.kernel_clk); + + irq.set_handler(Self::on_interrupt); + irq.unpend(); + irq.enable(); + + Self { + sdmmc: PhantomData, + pins, + irq, + config, + clock, + signalling: Default::default(), + card: None, + } + } + + #[inline(always)] + pub async fn init_card(&mut self, freq: impl Into) -> Result<(), Error> { + let inner = T::inner(); + let freq = freq.into(); + + inner + .init_card( + freq, + P::BUSWIDTH, + &mut self.card, + &mut self.signalling, + self.config.hclk, + self.config.kernel_clk, + &mut self.clock, + T::state(), + self.config.data_transfer_timeout, + ) + .await + } + + #[inline(always)] + pub async fn read_block( + &mut self, + block_idx: u32, + buffer: &mut DataBlock, + ) -> Result<(), Error> { + let card_capacity = self.card()?.card_type; + let inner = T::inner(); + let state = T::state(); + + // NOTE(unsafe) DataBlock uses align 4 + let buf = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) }; + inner + .read_block( + block_idx, + buf, + card_capacity, + state, + self.config.data_transfer_timeout, + ) + .await + } + + pub async fn write_block(&mut self, block_idx: u32, buffer: &DataBlock) -> Result<(), Error> { + let card = self.card.as_mut().ok_or(Error::NoCard)?; + let inner = T::inner(); + let state = T::state(); + + // NOTE(unsafe) DataBlock uses align 4 + let buf = unsafe { &*((&buffer.0) as *const [u8; 512] as *const [u32; 128]) }; + inner + .write_block( + block_idx, + buf, + card, + state, + self.config.data_transfer_timeout, + ) + .await + } + + /// Get a reference to the initialized card + /// + /// # Errors + /// + /// Returns Error::NoCard if [`init_card`](#method.init_card) + /// has not previously succeeded + #[inline(always)] + pub fn card(&self) -> Result<&Card, Error> { + self.card.as_ref().ok_or(Error::NoCard) + } + + #[inline(always)] + fn on_interrupt(_: *mut ()) { + let regs = T::inner(); + let state = T::state(); + + regs.data_interrupts(false); + state.wake(); + } +} + +impl<'d, T: Instance, P: Pins> Drop for Sdmmc<'d, T, P> { + fn drop(&mut self) { + self.irq.disable(); + let inner = T::inner(); + unsafe { inner.on_drop() }; + self.pins.deconfigure(); + } +} + +pub struct SdmmcInner(pub(crate) RegBlock); + +impl SdmmcInner { + /// # Safety + /// + /// Access to `regs` registers should be exclusive + unsafe fn new_inner(&self, kernel_clk: Hertz) -> Hertz { + let regs = self.0; + + // While the SD/SDIO card or eMMC is in identification mode, + // the SDMMC_CK frequency must be less than 400 kHz. + let (clkdiv, clock) = unwrap!(clk_div(kernel_clk, 400_000)); + + regs.clkcr().write(|w| { + w.set_widbus(0); + w.set_clkdiv(clkdiv); + w.set_pwrsav(false); + w.set_negedge(false); + w.set_hwfc_en(true); + }); + + // Power off, writen 00: Clock to the card is stopped; + // D[7:0], CMD, and CK are driven high. + regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::Off as u8)); + + clock + } + + /// Initializes card (if present) and sets the bus at the + /// specified frequency. + #[allow(clippy::too_many_arguments)] + async fn init_card( + &self, + freq: Hertz, + bus_width: BusWidth, + old_card: &mut Option, + signalling: &mut Signalling, + hclk: Hertz, + ker_ck: Hertz, + clock: &mut Hertz, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result<(), Error> { + let regs = self.0; + + // NOTE(unsafe) We have exclusive access to the peripheral + unsafe { + regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8)); + self.cmd(Cmd::idle(), false)?; + + // Check if cards supports CMD8 (with pattern) + self.cmd(Cmd::hs_send_ext_csd(0x1AA), false)?; + let r1 = regs.respr(0).read().cardstatus1(); + + let mut card = if r1 == 0x1AA { + // Card echoed back the pattern. Must be at least v2 + Card::default() + } else { + return Err(Error::UnsupportedCardVersion); + }; + + let ocr = loop { + // Signal that next command is a app command + self.cmd(Cmd::app_cmd(0), false)?; // CMD55 + + let arg = CmdAppOper::VOLTAGE_WINDOW_SD as u32 + | CmdAppOper::HIGH_CAPACITY as u32 + | CmdAppOper::SD_SWITCH_1_8V_CAPACITY as u32; + + // Initialize card + match self.cmd(Cmd::app_op_cmd(arg), false) { + // ACMD41 + Ok(_) => (), + Err(Error::Crc) => (), + Err(err) => return Err(err), + } + let ocr: OCR = regs.respr(0).read().cardstatus1().into(); + if !ocr.is_busy() { + // Power up done + break ocr; + } + }; + + if ocr.high_capacity() { + // Card is SDHC or SDXC or SDUC + card.card_type = CardCapacity::SDHC; + } else { + card.card_type = CardCapacity::SDSC; + } + card.ocr = ocr; + + self.cmd(Cmd::all_send_cid(), false)?; // CMD2 + let cid0 = regs.respr(0).read().cardstatus1() as u128; + let cid1 = regs.respr(1).read().cardstatus1() as u128; + let cid2 = regs.respr(2).read().cardstatus1() as u128; + let cid3 = regs.respr(3).read().cardstatus1() as u128; + let cid = (cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3); + card.cid = cid.into(); + + self.cmd(Cmd::send_rel_addr(), false)?; + card.rca = regs.respr(0).read().cardstatus1() >> 16; + + self.cmd(Cmd::send_csd(card.rca << 16), false)?; + let csd0 = regs.respr(0).read().cardstatus1() as u128; + let csd1 = regs.respr(1).read().cardstatus1() as u128; + let csd2 = regs.respr(2).read().cardstatus1() as u128; + let csd3 = regs.respr(3).read().cardstatus1() as u128; + let csd = (csd0 << 96) | (csd1 << 64) | (csd2 << 32) | (csd3); + card.csd = csd.into(); + + self.select_card(Some(&card))?; + self.get_scr(&mut card, waker_reg, data_transfer_timeout) + .await?; + + // Set bus width + let (width, acmd_arg) = match bus_width { + BusWidth::Eight => unimplemented!(), + BusWidth::Four if card.scr.bus_width_four() => (BusWidth::Four, 2), + _ => (BusWidth::One, 0), + }; + self.cmd(Cmd::app_cmd(card.rca << 16), false)?; + self.cmd(Cmd::cmd6(acmd_arg), false)?; + + // CPSMACT and DPSMACT must be 0 to set WIDBUS + self.wait_idle(); + + regs.clkcr().modify(|w| { + w.set_widbus(match width { + BusWidth::One => 0, + BusWidth::Four => 1, + BusWidth::Eight => 2, + _ => self::panic!("Invalid Bus Width"), + }) + }); + + // Set Clock + if freq.0 <= 25_000_000 { + // Final clock frequency + self.clkcr_set_clkdiv(freq.0, width, hclk, ker_ck, clock)?; + } else { + // Switch to max clock for SDR12 + self.clkcr_set_clkdiv(25_000_000, width, hclk, ker_ck, clock)?; + } + + // Read status + self.read_sd_status(&mut card, waker_reg, data_transfer_timeout) + .await?; + + if freq.0 > 25_000_000 { + // Switch to SDR25 + *signalling = self + .switch_signalling_mode(Signalling::SDR25, waker_reg, data_transfer_timeout) + .await?; + + if *signalling == Signalling::SDR25 { + // Set final clock frequency + self.clkcr_set_clkdiv(freq.0, width, hclk, ker_ck, clock)?; + + if self.read_status(&card)?.state() != CurrentState::Transfer { + return Err(Error::SignalingSwitchFailed); + } + } + } + // Read status after signalling change + self.read_sd_status(&mut card, waker_reg, data_transfer_timeout) + .await?; + old_card.replace(card); + } + + Ok(()) + } + + async fn read_block( + &self, + block_idx: u32, + buffer: &mut [u32; 128], + capacity: CardCapacity, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result<(), Error> { + // Always read 1 block of 512 bytes + // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes + let address = match capacity { + CardCapacity::SDSC => block_idx * 512, + _ => block_idx, + }; + self.cmd(Cmd::set_block_length(512), false)?; // CMD16 + + let regs = self.0; + let on_drop = OnDrop::new(|| unsafe { self.on_drop() }); + + let buf_addr = buffer as *mut [u32; 128] as u32; + unsafe { + self.prepare_datapath_transfer( + buf_addr, + 512, + 9, + Dir::CardToHost, + data_transfer_timeout, + ); + self.data_interrupts(true); + } + self.cmd(Cmd::read_single_block(address), true)?; + + let res = poll_fn(|cx| { + waker_reg.register(cx.waker()); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + self.clear_interrupt_flags(); + + if res.is_ok() { + on_drop.defuse(); + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } + } + res + } + + async fn write_block( + &self, + block_idx: u32, + buffer: &[u32; 128], + card: &mut Card, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result<(), Error> { + // Always read 1 block of 512 bytes + // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes + let address = match card.card_type { + CardCapacity::SDSC => block_idx * 512, + _ => block_idx, + }; + self.cmd(Cmd::set_block_length(512), false)?; // CMD16 + + let regs = self.0; + let on_drop = OnDrop::new(|| unsafe { self.on_drop() }); + + let buf_addr = buffer as *const [u32; 128] as u32; + unsafe { + self.prepare_datapath_transfer( + buf_addr, + 512, + 9, + Dir::HostToCard, + data_transfer_timeout, + ); + self.data_interrupts(true); + } + self.cmd(Cmd::write_single_block(address), true)?; + + let res = poll_fn(|cx| { + waker_reg.register(cx.waker()); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + self.clear_interrupt_flags(); + + match res { + Ok(_) => { + on_drop.defuse(); + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } + // TODO: Make this configurable + let mut timeout: u32 = 0x00FF_FFFF; + + // Try to read card status (ACMD13) + while timeout > 0 { + match self + .read_sd_status(card, waker_reg, data_transfer_timeout) + .await + { + Ok(_) => return Ok(()), + Err(Error::Timeout) => (), // Try again + Err(e) => return Err(e), + } + timeout -= 1; + } + Err(Error::SoftwareTimeout) + } + Err(e) => Err(e), + } + } + + /// Get the current SDMMC bus clock + //pub fn clock(&self) -> Hertz { + // self.clock + //} + + /// Wait idle on DOSNACT and CPSMACT + #[inline(always)] + fn wait_idle(&self) { + let regs = self.0; + + // NOTE(unsafe) Atomic read with no side-effects + unsafe { + while { + let status = regs.star().read(); + status.dpsmact() || status.cpsmact() + } {} + } + } + + /// # Safety + /// + /// `buffer_addr` must be valid for the whole transfer and word aligned + unsafe fn prepare_datapath_transfer( + &self, + buffer_addr: u32, + length_bytes: u32, + block_size: u8, + direction: Dir, + data_transfer_timeout: u32, + ) { + self::assert!(block_size <= 14, "Block size up to 2^14 bytes"); + let regs = self.0; + + let dtdir = match direction { + Dir::CardToHost => true, + Dir::HostToCard => false, + }; + + // Command AND Data state machines must be idle + self.wait_idle(); + self.clear_interrupt_flags(); + + // NOTE(unsafe) We have exclusive access to the regisers + + regs.dtimer() + .write(|w| w.set_datatime(data_transfer_timeout)); + regs.dlenr().write(|w| w.set_datalength(length_bytes)); + + regs.idmabase0r().write(|w| w.set_idmabase0(buffer_addr)); + regs.idmactrlr().modify(|w| w.set_idmaen(true)); + regs.dctrl().modify(|w| { + w.set_dblocksize(block_size); + w.set_dtdir(dtdir); + }); + } + + /// Sets the CLKDIV field in CLKCR. Updates clock field in self + fn clkcr_set_clkdiv( + &self, + freq: u32, + width: BusWidth, + hclk: Hertz, + ker_ck: Hertz, + clock: &mut Hertz, + ) -> Result<(), Error> { + let regs = self.0; + + let (clkdiv, new_clock) = clk_div(ker_ck, freq)?; + // Enforce AHB and SDMMC_CK clock relation. See RM0433 Rev 7 + // Section 55.5.8 + let sdmmc_bus_bandwidth = new_clock.0 * (width as u32); + self::assert!(hclk.0 > 3 * sdmmc_bus_bandwidth / 32); + *clock = new_clock; + + // NOTE(unsafe) We have exclusive access to the regblock + unsafe { + // CPSMACT and DPSMACT must be 0 to set CLKDIV + self.wait_idle(); + regs.clkcr().modify(|w| w.set_clkdiv(clkdiv)); + } + + Ok(()) + } + + /// Switch mode using CMD6. + /// + /// Attempt to set a new signalling mode. The selected + /// signalling mode is returned. Expects the current clock + /// frequency to be > 12.5MHz. + async fn switch_signalling_mode( + &self, + signalling: Signalling, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result { + // NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not + // necessary" + + let set_function = 0x8000_0000 + | match signalling { + // See PLSS v7_10 Table 4-11 + Signalling::DDR50 => 0xFF_FF04, + Signalling::SDR104 => 0xFF_1F03, + Signalling::SDR50 => 0xFF_1F02, + Signalling::SDR25 => 0xFF_FF01, + Signalling::SDR12 => 0xFF_FF00, + }; + + let mut status = [0u32; 16]; + let status_addr = &mut status as *mut [u32; 16] as u32; + + // Arm `OnDrop` after the buffer, so it will be dropped first + let regs = self.0; + let on_drop = OnDrop::new(|| unsafe { self.on_drop() }); + + unsafe { + self.prepare_datapath_transfer( + status_addr, + 64, + 6, + Dir::CardToHost, + data_transfer_timeout, + ); + self.data_interrupts(true); + } + self.cmd(Cmd::cmd6(set_function), true)?; // CMD6 + + let res = poll_fn(|cx| { + waker_reg.register(cx.waker()); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + self.clear_interrupt_flags(); + + // Host is allowed to use the new functions at least 8 + // clocks after the end of the switch command + // transaction. We know the current clock period is < 80ns, + // so a total delay of 640ns is required here + for _ in 0..300 { + cortex_m::asm::nop(); + } + + match res { + Ok(_) => { + on_drop.defuse(); + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } + // Function Selection of Function Group 1 + let selection = (u32::from_be(status[4]) >> 24) & 0xF; + + match selection { + 0 => Ok(Signalling::SDR12), + 1 => Ok(Signalling::SDR25), + 2 => Ok(Signalling::SDR50), + 3 => Ok(Signalling::SDR104), + 4 => Ok(Signalling::DDR50), + _ => Err(Error::UnsupportedCardType), + } + } + Err(e) => Err(e), + } + } + + /// Query the card status (CMD13, returns R1) + /// + fn read_status(&self, card: &Card) -> Result { + let regs = self.0; + let rca = card.rca; + + self.cmd(Cmd::card_status(rca << 16), false)?; // CMD13 + + // NOTE(unsafe) Atomic read with no side-effects + let r1 = unsafe { regs.respr(0).read().cardstatus1() }; + Ok(r1.into()) + } + + /// Reads the SD Status (ACMD13) + async fn read_sd_status( + &self, + card: &mut Card, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result<(), Error> { + let rca = card.rca; + self.cmd(Cmd::set_block_length(64), false)?; // CMD16 + self.cmd(Cmd::app_cmd(rca << 16), false)?; // APP + + let mut status = [0u32; 16]; + let status_addr = &mut status as *mut [u32; 16] as u32; + + // Arm `OnDrop` after the buffer, so it will be dropped first + let regs = self.0; + let on_drop = OnDrop::new(|| unsafe { self.on_drop() }); + + unsafe { + self.prepare_datapath_transfer( + status_addr, + 64, + 6, + Dir::CardToHost, + data_transfer_timeout, + ); + self.data_interrupts(true); + } + self.cmd(Cmd::card_status(0), true)?; + + let res = poll_fn(|cx| { + waker_reg.register(cx.waker()); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + self.clear_interrupt_flags(); + + if res.is_ok() { + on_drop.defuse(); + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } + for byte in status.iter_mut() { + *byte = u32::from_be(*byte); + } + card.status = status.into(); + } + res + } + + /// Select one card and place it into the _Tranfer State_ + /// + /// If `None` is specifed for `card`, all cards are put back into + /// _Stand-by State_ + fn select_card(&self, card: Option<&Card>) -> Result<(), Error> { + // Determine Relative Card Address (RCA) of given card + let rca = card.map(|c| c.rca << 16).unwrap_or(0); + + let r = self.cmd(Cmd::sel_desel_card(rca), false); + match (r, rca) { + (Err(Error::Timeout), 0) => Ok(()), + _ => r, + } + } + + /// Clear flags in interrupt clear register + #[inline(always)] + fn clear_interrupt_flags(&self) { + let regs = self.0; + // NOTE(unsafe) Atomic write + unsafe { + regs.icr().write(|w| { + w.set_ccrcfailc(true); + w.set_dcrcfailc(true); + w.set_ctimeoutc(true); + w.set_dtimeoutc(true); + w.set_txunderrc(true); + w.set_rxoverrc(true); + w.set_cmdrendc(true); + w.set_cmdsentc(true); + w.set_dataendc(true); + w.set_dholdc(true); + w.set_dbckendc(true); + w.set_dabortc(true); + w.set_busyd0endc(true); + w.set_sdioitc(true); + w.set_ackfailc(true); + w.set_acktimeoutc(true); + w.set_vswendc(true); + w.set_ckstopc(true); + w.set_idmatec(true); + w.set_idmabtcc(true); + }); + } + } + + /// Enables the interrupts for data transfer + #[inline(always)] + fn data_interrupts(&self, enable: bool) { + let regs = self.0; + // NOTE(unsafe) Atomic write + unsafe { + regs.maskr().write(|w| { + w.set_dcrcfailie(enable); + w.set_dtimeoutie(enable); + w.set_dataendie(enable); + w.set_dabortie(enable); + }); + } + } + + async fn get_scr( + &self, + card: &mut Card, + waker_reg: &AtomicWaker, + data_transfer_timeout: u32, + ) -> Result<(), Error> { + // Read the the 64-bit SCR register + self.cmd(Cmd::set_block_length(8), false)?; // CMD16 + self.cmd(Cmd::app_cmd(card.rca << 16), false)?; + + let mut scr = [0u32; 2]; + let scr_addr = &mut scr as *mut u32 as u32; + + // Arm `OnDrop` after the buffer, so it will be dropped first + let regs = self.0; + let on_drop = OnDrop::new(move || unsafe { self.on_drop() }); + + unsafe { + self.prepare_datapath_transfer(scr_addr, 8, 3, Dir::CardToHost, data_transfer_timeout); + self.data_interrupts(true); + } + self.cmd(Cmd::cmd51(), true)?; + + let res = poll_fn(|cx| { + waker_reg.register(cx.waker()); + let status = unsafe { regs.star().read() }; + + if status.dcrcfail() { + return Poll::Ready(Err(Error::Crc)); + } else if status.dtimeout() { + return Poll::Ready(Err(Error::Timeout)); + } else if status.dataend() { + return Poll::Ready(Ok(())); + } + Poll::Pending + }) + .await; + self.clear_interrupt_flags(); + + if res.is_ok() { + on_drop.defuse(); + + unsafe { + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + let scr_bytes = &*(&scr as *const [u32; 2] as *const [u8; 8]); + card.scr = SCR(u64::from_be_bytes(*scr_bytes)); + } + } + res + } + + /// Send command to card + fn cmd(&self, cmd: Cmd, data: bool) -> Result<(), Error> { + let regs = self.0; + + self.clear_interrupt_flags(); + // NOTE(safety) Atomic operations + unsafe { + // CP state machine must be idle + while regs.star().read().cpsmact() {} + + // Command arg + regs.argr().write(|w| w.set_cmdarg(cmd.arg)); + + // Special mode in CP State Machine + // CMD12: Stop Transmission + let cpsm_stop_transmission = cmd.cmd == 12; + + // Command index and start CP State Machine + regs.cmdr().write(|w| { + w.set_waitint(false); + w.set_waitresp(cmd.resp as u8); + w.set_cmdstop(cpsm_stop_transmission); + w.set_cmdindex(cmd.cmd); + w.set_cpsmen(true); + w.set_cmdtrans(data); + }); + + let mut status; + if cmd.resp == Response::None { + // Wait for CMDSENT or a timeout + while { + status = regs.star().read(); + !(status.ctimeout() || status.cmdsent()) + } {} + } else { + // Wait for CMDREND or CCRCFAIL or a timeout + while { + status = regs.star().read(); + !(status.ctimeout() || status.cmdrend() || status.ccrcfail()) + } {} + } + + if status.ctimeout() { + return Err(Error::Timeout); + } else if status.ccrcfail() { + return Err(Error::Crc); + } + Ok(()) + } + } + + /// # Safety + /// + /// Ensure that `regs` has exclusive access to the regblocks + unsafe fn on_drop(&self) { + let regs = self.0; + if regs.star().read().dpsmact() { + self.clear_interrupt_flags(); + // Send abort + // CP state machine must be idle + while regs.star().read().cpsmact() {} + + // Command arg + regs.argr().write(|w| w.set_cmdarg(0)); + + // Command index and start CP State Machine + regs.cmdr().write(|w| { + w.set_waitint(false); + w.set_waitresp(Response::Short as u8); + w.set_cmdstop(true); + w.set_cmdindex(12); + w.set_cpsmen(true); + w.set_cmdtrans(false); + }); + + // Wait for the abort + while regs.star().read().dpsmact() {} + } + self.data_interrupts(false); + self.clear_interrupt_flags(); + regs.idmactrlr().modify(|w| w.set_idmaen(false)); + } +} + +/// SD card Commands +impl Cmd { + const fn new(cmd: u8, arg: u32, resp: Response) -> Cmd { + Cmd { cmd, arg, resp } + } + + /// CMD0: Idle + const fn idle() -> Cmd { + Cmd::new(0, 0, Response::None) + } + + /// CMD2: Send CID + const fn all_send_cid() -> Cmd { + Cmd::new(2, 0, Response::Long) + } + + /// CMD3: Send Relative Address + const fn send_rel_addr() -> Cmd { + Cmd::new(3, 0, Response::Short) + } + + /// CMD6: Switch Function Command + /// ACMD6: Bus Width + const fn cmd6(arg: u32) -> Cmd { + Cmd::new(6, arg, Response::Short) + } + + /// CMD7: Select one card and put it into the _Tranfer State_ + const fn sel_desel_card(rca: u32) -> Cmd { + Cmd::new(7, rca, Response::Short) + } + + /// CMD8: + const fn hs_send_ext_csd(arg: u32) -> Cmd { + Cmd::new(8, arg, Response::Short) + } + + /// CMD9: + const fn send_csd(rca: u32) -> Cmd { + Cmd::new(9, rca, Response::Long) + } + + /// CMD12: + //const fn stop_transmission() -> Cmd { + // Cmd::new(12, 0, Response::Short) + //} + + /// CMD13: Ask card to send status register + /// ACMD13: SD Status + const fn card_status(rca: u32) -> Cmd { + Cmd::new(13, rca, Response::Short) + } + + /// CMD16: + const fn set_block_length(blocklen: u32) -> Cmd { + Cmd::new(16, blocklen, Response::Short) + } + + /// CMD17: Block Read + const fn read_single_block(addr: u32) -> Cmd { + Cmd::new(17, addr, Response::Short) + } + + /// CMD18: Multiple Block Read + //const fn read_multiple_blocks(addr: u32) -> Cmd { + // Cmd::new(18, addr, Response::Short) + //} + + /// CMD24: Block Write + const fn write_single_block(addr: u32) -> Cmd { + Cmd::new(24, addr, Response::Short) + } + + const fn app_op_cmd(arg: u32) -> Cmd { + Cmd::new(41, arg, Response::Short) + } + + const fn cmd51() -> Cmd { + Cmd::new(51, 0, Response::Short) + } + + /// App Command. Indicates that next command will be a app command + const fn app_cmd(rca: u32) -> Cmd { + Cmd::new(55, rca, Response::Short) + } +} + +////////////////////////////////////////////////////// + +pub(crate) mod sealed { + use super::*; + use crate::gpio::Pin as GpioPin; + + pub trait Instance { + type Interrupt: Interrupt; + + fn inner() -> SdmmcInner; + fn state() -> &'static AtomicWaker; + } + pub trait CkPin: GpioPin { + const AF_NUM: u8; + } + pub trait CmdPin: GpioPin { + const AF_NUM: u8; + } + pub trait D0Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D1Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D2Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D3Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D4Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D5Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D6Pin: GpioPin { + const AF_NUM: u8; + } + pub trait D7Pin: GpioPin { + const AF_NUM: u8; + } + + pub trait Pins {} +} + +pub trait Instance: sealed::Instance + 'static {} +pub trait CkPin: sealed::CkPin + 'static {} +pub trait CmdPin: sealed::CmdPin + 'static {} +pub trait D0Pin: sealed::D0Pin + 'static {} +pub trait D1Pin: sealed::D1Pin + 'static {} +pub trait D2Pin: sealed::D2Pin + 'static {} +pub trait D3Pin: sealed::D3Pin + 'static {} +pub trait D4Pin: sealed::D4Pin + 'static {} +pub trait D5Pin: sealed::D5Pin + 'static {} +pub trait D6Pin: sealed::D6Pin + 'static {} +pub trait D7Pin: sealed::D7Pin + 'static {} + +pub trait Pins: sealed::Pins + 'static { + const BUSWIDTH: BusWidth; + + fn configure(&mut self); + fn deconfigure(&mut self); +} + +impl sealed::Pins for (CLK, CMD, D0, D1, D2, D3) +where + T: Instance, + CLK: CkPin, + CMD: CmdPin, + D0: D0Pin, + D1: D1Pin, + D2: D2Pin, + D3: D3Pin, +{ +} + +impl sealed::Pins for (CLK, CMD, D0) +where + T: Instance, + CLK: CkPin, + CMD: CmdPin, + D0: D0Pin, +{ +} + +/// # Safety +/// +/// Access to `block` registers should be exclusive +unsafe fn configure_pin(block: Gpio, n: usize, afr_num: u8, pup: bool) { + use pac::gpio::vals::{Afr, Moder, Ospeedr, Pupdr}; + + let (afr, n_af) = if n < 8 { (0, n) } else { (1, n - 8) }; + block.afr(afr).modify(|w| w.set_afr(n_af, Afr(afr_num))); + block.moder().modify(|w| w.set_moder(n, Moder::ALTERNATE)); + if pup { + block.pupdr().modify(|w| w.set_pupdr(n, Pupdr::PULLUP)); + } + block + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::VERYHIGHSPEED)); +} + +impl Pins for (CLK, CMD, D0, D1, D2, D3) +where + T: Instance, + CLK: CkPin, + CMD: CmdPin, + D0: D0Pin, + D1: D1Pin, + D2: D2Pin, + D3: D3Pin, +{ + const BUSWIDTH: BusWidth = BusWidth::Four; + + fn configure(&mut self) { + let (clk_pin, cmd_pin, d0_pin, d1_pin, d2_pin, d3_pin) = self; + + cortex_m::interrupt::free(|_| unsafe { + // clk + let block = clk_pin.block(); + let n = clk_pin.pin() as usize; + let afr_num = CLK::AF_NUM; + configure_pin(block, n, afr_num, false); + + // cmd + let block = cmd_pin.block(); + let n = cmd_pin.pin() as usize; + let afr_num = CMD::AF_NUM; + configure_pin(block, n, afr_num, true); + + // d0 + let block = d0_pin.block(); + let n = d0_pin.pin() as usize; + let afr_num = D0::AF_NUM; + configure_pin(block, n, afr_num, true); + + // d1 + let block = d1_pin.block(); + let n = d1_pin.pin() as usize; + let afr_num = D1::AF_NUM; + configure_pin(block, n, afr_num, true); + + // d2 + let block = d2_pin.block(); + let n = d2_pin.pin() as usize; + let afr_num = D2::AF_NUM; + configure_pin(block, n, afr_num, true); + + // d3 + let block = d3_pin.block(); + let n = d3_pin.pin() as usize; + let afr_num = D3::AF_NUM; + configure_pin(block, n, afr_num, true); + }); + } + + fn deconfigure(&mut self) { + use pac::gpio::vals::{Moder, Ospeedr, Pupdr}; + + let (clk_pin, cmd_pin, d0_pin, d1_pin, d2_pin, d3_pin) = self; + + cortex_m::interrupt::free(|_| unsafe { + // clk + let n = clk_pin.pin().into(); + clk_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + clk_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + + // cmd + let n = cmd_pin.pin().into(); + cmd_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + cmd_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + cmd_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + + // d0 + let n = d0_pin.pin().into(); + d0_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + d0_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + d0_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + + // d1 + let n = d1_pin.pin().into(); + d1_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + d1_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + d1_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + + // d2 + let n = d2_pin.pin().into(); + d2_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + d2_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + d2_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + + // d3 + let n = d3_pin.pin().into(); + d3_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + d3_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + d3_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + }); + } +} + +impl Pins for (CLK, CMD, D0) +where + T: Instance, + CLK: CkPin, + CMD: CmdPin, + D0: D0Pin, +{ + const BUSWIDTH: BusWidth = BusWidth::One; + + fn configure(&mut self) { + let (clk_pin, cmd_pin, d0_pin) = self; + + cortex_m::interrupt::free(|_| unsafe { + // clk + let block = clk_pin.block(); + let n = clk_pin.pin() as usize; + let afr_num = CLK::AF_NUM; + configure_pin(block, n, afr_num, false); + + // cmd + let block = cmd_pin.block(); + let n = cmd_pin.pin() as usize; + let afr_num = CMD::AF_NUM; + configure_pin(block, n, afr_num, true); + + // d0 + let block = d0_pin.block(); + let n = d0_pin.pin() as usize; + let afr_num = D0::AF_NUM; + configure_pin(block, n, afr_num, true); + }); + } + + fn deconfigure(&mut self) { + use pac::gpio::vals::{Moder, Ospeedr, Pupdr}; + + let (clk_pin, cmd_pin, d0_pin) = self; + + cortex_m::interrupt::free(|_| unsafe { + // clk + let n = clk_pin.pin().into(); + clk_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + clk_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + + // cmd + let n = cmd_pin.pin().into(); + cmd_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + cmd_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + cmd_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + + // d0 + let n = d0_pin.pin().into(); + d0_pin + .block() + .moder() + .modify(|w| w.set_moder(n, Moder::ANALOG)); + d0_pin + .block() + .ospeedr() + .modify(|w| w.set_ospeedr(n, Ospeedr::LOWSPEED)); + d0_pin + .block() + .pupdr() + .modify(|w| w.set_pupdr(n, Pupdr::FLOATING)); + }); + } +} + +macro_rules! impl_sdmmc { + ($inst:ident) => { + impl crate::sdmmc::sealed::Instance for peripherals::$inst { + type Interrupt = interrupt::$inst; + + fn inner() -> crate::sdmmc::SdmmcInner { + const INNER: crate::sdmmc::SdmmcInner = crate::sdmmc::SdmmcInner($inst); + INNER + } + + fn state() -> &'static ::embassy::util::AtomicWaker { + static WAKER: ::embassy::util::AtomicWaker = ::embassy::util::AtomicWaker::new(); + &WAKER + } + } + + impl crate::sdmmc::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_sdmmc_pin { + ($inst:ident, $func:ident, $pin:ident, $num:expr) => { + impl crate::sdmmc::sealed::$func for peripherals::$pin { + const AF_NUM: u8 = $num; + } + + impl crate::sdmmc::$func for peripherals::$pin {} + }; +} + +#[cfg(feature = "sdmmc-rs")] +mod sdmmc_rs { + use super::*; + use embedded_sdmmc::{Block, BlockCount, BlockDevice, BlockIdx}; + + impl<'d, T: Instance, P: Pins> BlockDevice for Sdmmc<'d, T, P> { + type Error = Error; + #[rustfmt::skip] + type ReadFuture<'a> where Self: 'a = impl Future> + 'a; + #[rustfmt::skip] + type WriteFuture<'a> where Self: 'a = impl Future> + 'a; + + fn read<'a>( + &'a mut self, + blocks: &'a mut [Block], + start_block_idx: BlockIdx, + _reason: &str, + ) -> Self::ReadFuture<'a> { + async move { + let card_capacity = self.card()?.card_type; + let inner = T::inner(); + let state = T::state(); + let mut address = start_block_idx.0; + + for block in blocks.iter_mut() { + let block: &mut [u8; 512] = &mut block.contents; + + // NOTE(unsafe) Block uses align(4) + let buf = unsafe { &mut *(block as *mut [u8; 512] as *mut [u32; 128]) }; + inner + .read_block( + address, + buf, + card_capacity, + state, + self.config.data_transfer_timeout, + ) + .await?; + address += 1; + } + Ok(()) + } + } + + fn write<'a>( + &'a mut self, + blocks: &'a [Block], + start_block_idx: BlockIdx, + ) -> Self::WriteFuture<'a> { + async move { + let card = self.card.as_mut().ok_or(Error::NoCard)?; + let inner = T::inner(); + let state = T::state(); + let mut address = start_block_idx.0; + + for block in blocks.iter() { + let block: &[u8; 512] = &block.contents; + + // NOTE(unsafe) DataBlock uses align 4 + let buf = unsafe { &*(block as *const [u8; 512] as *const [u32; 128]) }; + inner + .write_block(address, buf, card, state, self.config.data_transfer_timeout) + .await?; + address += 1; + } + Ok(()) + } + } + + fn num_blocks(&self) -> Result { + let card = self.card()?; + let count = card.csd.block_count(); + Ok(BlockCount(count)) + } + } +} diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs new file mode 100644 index 00000000..9f62a5ec --- /dev/null +++ b/embassy-stm32/src/spi/mod.rs @@ -0,0 +1,93 @@ +#![macro_use] + +#[cfg_attr(feature = "_spi_v1", path = "v1.rs")] +#[cfg_attr(feature = "_spi_v2", path = "v2.rs")] +mod _version; +pub use _version::*; + +use crate::gpio::Pin; + +pub enum Error { + Framing, + Crc, + Overrun, +} + +// TODO move upwards in the tree +pub enum ByteOrder { + LsbFirst, + MsbFirst, +} + +#[derive(Copy, Clone, PartialOrd, PartialEq)] +enum WordSize { + EightBit, + SixteenBit, +} + +#[non_exhaustive] +pub struct Config { + pub mode: Mode, + pub byte_order: ByteOrder, +} + +impl Default for Config { + fn default() -> Self { + Self { + mode: MODE_0, + byte_order: ByteOrder::MsbFirst, + } + } +} + +pub(crate) mod sealed { + use super::*; + + pub trait Instance { + fn regs() -> &'static crate::pac::spi::Spi; + } + + pub trait SckPin: Pin { + fn af_num(&self) -> u8; + } + + pub trait MosiPin: Pin { + fn af_num(&self) -> u8; + } + + pub trait MisoPin: Pin { + fn af_num(&self) -> u8; + } +} + +pub trait Instance: sealed::Instance + 'static {} + +pub trait SckPin: sealed::SckPin + 'static {} + +pub trait MosiPin: sealed::MosiPin + 'static {} + +pub trait MisoPin: sealed::MisoPin + 'static {} + +macro_rules! impl_spi { + ($inst:ident, $clk:ident) => { + impl crate::spi::sealed::Instance for peripherals::$inst { + fn regs() -> &'static crate::pac::spi::Spi { + &crate::pac::$inst + } + } + + impl crate::spi::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_spi_pin { + ($inst:ident, $pin_func:ident, $pin:ident, $af:expr) => { + impl crate::spi::$pin_func for peripherals::$pin {} + + impl crate::spi::sealed::$pin_func for peripherals::$pin { + fn af_num(&self) -> u8 { + $af + } + } + }; +} diff --git a/embassy-stm32/src/spi/v1.rs b/embassy-stm32/src/spi/v1.rs new file mode 100644 index 00000000..a464c427 --- /dev/null +++ b/embassy-stm32/src/spi/v1.rs @@ -0,0 +1,278 @@ +#![macro_use] + +use crate::gpio::{sealed::Pin, AnyPin}; +use crate::pac::spi; +use crate::spi::{ByteOrder, Config, Error, Instance, MisoPin, MosiPin, SckPin, WordSize}; +use crate::time::Hertz; +use core::marker::PhantomData; +use embassy::util::Unborrow; +use embassy_extras::unborrow; +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; + +impl WordSize { + fn dff(&self) -> spi::vals::Dff { + match self { + WordSize::EightBit => spi::vals::Dff::EIGHTBIT, + WordSize::SixteenBit => spi::vals::Dff::SIXTEENBIT, + } + } +} + +pub struct Spi<'d, T: Instance> { + //peri: T, + sck: AnyPin, + mosi: AnyPin, + miso: AnyPin, + current_word_size: WordSize, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Instance> Spi<'d, T> { + pub fn new( + pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + freq: F, + config: Config, + ) -> Self + where + F: Into, + { + unborrow!(peri, sck, mosi, miso); + + unsafe { + sck.set_as_af(sck.af_num()); + mosi.set_as_af(mosi.af_num()); + miso.set_as_af(miso.af_num()); + } + + let sck = sck.degrade(); + let mosi = mosi.degrade(); + let miso = miso.degrade(); + + unsafe { + T::regs().cr2().write(|w| { + w.set_ssoe(false); + }); + } + + let br = Self::compute_baud_rate(pclk, freq.into()); + + unsafe { + T::regs().cr1().write(|w| { + w.set_cpha( + match config.mode.phase == Phase::CaptureOnSecondTransition { + true => spi::vals::Cpha::SECONDEDGE, + false => spi::vals::Cpha::FIRSTEDGE, + }, + ); + w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { + true => spi::vals::Cpol::IDLEHIGH, + false => spi::vals::Cpol::IDLELOW, + }); + + w.set_mstr(spi::vals::Mstr::MASTER); + w.set_br(spi::vals::Br(br)); + w.set_spe(true); + w.set_lsbfirst(match config.byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + }); + w.set_ssi(true); + w.set_ssm(true); + w.set_crcen(false); + w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); + w.set_dff(WordSize::EightBit.dff()) + }); + } + + Self { + //peri, + sck, + mosi, + miso, + current_word_size: WordSize::EightBit, + phantom: PhantomData, + } + } + + fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { + match clocks.0 / freq.0 { + 0 => unreachable!(), + 1..=2 => 0b000, + 3..=5 => 0b001, + 6..=11 => 0b010, + 12..=23 => 0b011, + 24..=39 => 0b100, + 40..=95 => 0b101, + 96..=191 => 0b110, + _ => 0b111, + } + } + + fn set_word_size(&mut self, word_size: WordSize) { + if self.current_word_size == word_size { + return; + } + unsafe { + T::regs().cr1().modify(|reg| { + reg.set_spe(false); + reg.set_dff(word_size.dff()) + }); + T::regs().cr1().modify(|reg| { + reg.set_spe(true); + }); + self.current_word_size = word_size; + } + } +} + +impl<'d, T: Instance> Drop for Spi<'d, T> { + fn drop(&mut self) { + unsafe { + self.sck.set_as_analog(); + self.mosi.set_as_analog(); + self.miso.set_as_analog(); + } + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { + self.set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { + self.set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u8 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { + self.set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { + self.set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u16 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} diff --git a/embassy-stm32/src/spi/v2.rs b/embassy-stm32/src/spi/v2.rs new file mode 100644 index 00000000..b6ae8b27 --- /dev/null +++ b/embassy-stm32/src/spi/v2.rs @@ -0,0 +1,294 @@ +#![macro_use] + +use crate::gpio::{AnyPin, Pin}; +use crate::pac::gpio::vals::{Afr, Moder}; +use crate::pac::gpio::Gpio; +use crate::pac::spi; +use crate::spi::{ByteOrder, Config, Instance, MisoPin, MosiPin, SckPin, WordSize}; +use crate::time::Hertz; +use core::marker::PhantomData; +use embassy::util::Unborrow; +use embassy_extras::unborrow; +pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; + +impl WordSize { + fn ds(&self) -> spi::vals::Ds { + match self { + WordSize::EightBit => spi::vals::Ds::EIGHTBIT, + WordSize::SixteenBit => spi::vals::Ds::SIXTEENBIT, + } + } + + fn frxth(&self) -> spi::vals::Frxth { + match self { + WordSize::EightBit => spi::vals::Frxth::QUARTER, + WordSize::SixteenBit => spi::vals::Frxth::HALF, + } + } +} + +pub struct Spi<'d, T: Instance> { + //peri: T, + sck: AnyPin, + mosi: AnyPin, + miso: AnyPin, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Instance> Spi<'d, T> { + pub fn new( + pclk: Hertz, + peri: impl Unborrow + 'd, + sck: impl Unborrow>, + mosi: impl Unborrow>, + miso: impl Unborrow>, + freq: F, + config: Config, + ) -> Self + where + F: Into, + { + unborrow!(peri); + unborrow!(sck, mosi, miso); + + unsafe { + Self::configure_pin(sck.block(), sck.pin() as _, sck.af()); + Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af()); + Self::configure_pin(miso.block(), miso.pin() as _, miso.af()); + } + + let sck = sck.degrade(); + let mosi = mosi.degrade(); + let miso = miso.degrade(); + + unsafe { + T::regs().cr2().write(|w| { + w.set_ssoe(false); + }); + } + + let br = Self::compute_baud_rate(pclk, freq.into()); + + unsafe { + T::regs().cr1().write(|w| { + w.set_cpha( + match config.mode.phase == Phase::CaptureOnSecondTransition { + true => spi::vals::Cpha::SECONDEDGE, + false => spi::vals::Cpha::FIRSTEDGE, + }, + ); + w.set_cpol(match config.mode.polarity == Polarity::IdleHigh { + true => spi::vals::Cpol::IDLEHIGH, + false => spi::vals::Cpol::IDLELOW, + }); + + w.set_mstr(spi::vals::Mstr::MASTER); + w.set_br(spi::vals::Br(br)); + w.set_spe(true); + w.set_lsbfirst(match config.byte_order { + ByteOrder::LsbFirst => spi::vals::Lsbfirst::LSBFIRST, + ByteOrder::MsbFirst => spi::vals::Lsbfirst::MSBFIRST, + }); + w.set_ssi(true); + w.set_ssm(true); + w.set_crcen(false); + w.set_bidimode(spi::vals::Bidimode::UNIDIRECTIONAL); + }); + } + + Self { + //peri, + sck, + mosi, + miso, + phantom: PhantomData, + } + } + + unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) { + let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) }; + block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE)); + block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num))); + } + + unsafe fn unconfigure_pin(block: Gpio, pin: usize) { + block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG)); + } + + fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 { + match clocks.0 / freq.0 { + 0 => unreachable!(), + 1..=2 => 0b000, + 3..=5 => 0b001, + 6..=11 => 0b010, + 12..=23 => 0b011, + 24..=39 => 0b100, + 40..=95 => 0b101, + 96..=191 => 0b110, + _ => 0b111, + } + } + + fn set_word_size(word_size: WordSize) { + unsafe { + T::regs().cr2().write(|w| { + w.set_ds(word_size.ds()); + w.set_frxth(word_size.frxth()); + }); + } + } +} + +impl<'d, T: Instance> Drop for Spi<'d, T> { + fn drop(&mut self) { + unsafe { + Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _); + Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _); + Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _); + } + } +} + +pub enum Error { + Framing, + Crc, + Overrun, +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> { + Self::set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> { + Self::set_word_size(WordSize::EightBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u8 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Write for Spi<'d, T> { + type Error = Error; + + fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> { + Self::set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + loop { + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + if !sr.txe() { + // loop waiting for TXE + } + } + } + + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer for Spi<'d, T> { + type Error = Error; + + fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> { + Self::set_word_size(WordSize::SixteenBit); + let regs = T::regs(); + + for word in words.iter_mut() { + while unsafe { !regs.sr().read().txe() } { + // spin + } + unsafe { + regs.dr().write(|reg| reg.0 = *word as u32); + } + while unsafe { !regs.sr().read().rxne() } { + // spin waiting for inbound to shift in. + } + *word = unsafe { regs.dr().read().0 as u16 }; + let sr = unsafe { regs.sr().read() }; + if sr.fre() { + return Err(Error::Framing); + } + if sr.ovr() { + return Err(Error::Overrun); + } + if sr.crcerr() { + return Err(Error::Crc); + } + } + + Ok(words) + } +} diff --git a/embassy-stm32/src/time.rs b/embassy-stm32/src/time.rs new file mode 100644 index 00000000..c131415c --- /dev/null +++ b/embassy-stm32/src/time.rs @@ -0,0 +1,126 @@ +//! Time units + +/// Bits per second +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct Bps(pub u32); + +/// Hertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct Hertz(pub u32); + +/// KiloHertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct KiloHertz(pub u32); + +/// MegaHertz +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MegaHertz(pub u32); + +/// MilliSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MilliSeconds(pub u32); + +/// MicroSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct MicroSeconds(pub u32); + +/// NanoSeconds +#[derive(PartialEq, PartialOrd, Clone, Copy, Debug)] +pub struct NanoSeconds(pub u32); + +/// Extension trait that adds convenience methods to the `u32` type +pub trait U32Ext { + /// Wrap in `Bps` + fn bps(self) -> Bps; + + /// Wrap in `Hertz` + fn hz(self) -> Hertz; + + /// Wrap in `KiloHertz` + fn khz(self) -> KiloHertz; + + /// Wrap in `MegaHertz` + fn mhz(self) -> MegaHertz; + + /// Wrap in "MilliSeconds" + fn ms(self) -> MilliSeconds; + + /// Wrap in "MicroSeconds" + fn us(self) -> MicroSeconds; + + /// Wrap in "NanoSeconds" + fn ns(self) -> NanoSeconds; +} + +impl U32Ext for u32 { + fn bps(self) -> Bps { + Bps(self) + } + + fn hz(self) -> Hertz { + Hertz(self) + } + + fn khz(self) -> KiloHertz { + KiloHertz(self) + } + + fn mhz(self) -> MegaHertz { + MegaHertz(self) + } + + fn ms(self) -> MilliSeconds { + MilliSeconds(self) + } + + fn us(self) -> MicroSeconds { + MicroSeconds(self) + } + + fn ns(self) -> NanoSeconds { + NanoSeconds(self) + } +} + +// Unit conversions +impl Into for Bps { + fn into(self) -> Hertz { + Hertz(self.0) + } +} + +impl Into for KiloHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> Hertz { + Hertz(self.0 * 1_000_000) + } +} + +impl Into for MegaHertz { + fn into(self) -> KiloHertz { + KiloHertz(self.0 * 1_000) + } +} + +impl Into for MicroSeconds { + fn into(self) -> NanoSeconds { + NanoSeconds(self.0 * 1_000) + } +} + +impl Into for MilliSeconds { + fn into(self) -> NanoSeconds { + NanoSeconds(self.0 * 1_000_000) + } +} + +impl Into for MilliSeconds { + fn into(self) -> MicroSeconds { + MicroSeconds(self.0 * 1_000) + } +} diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs new file mode 100644 index 00000000..02ef9c4b --- /dev/null +++ b/embassy-stm32/src/usart/mod.rs @@ -0,0 +1,74 @@ +#![macro_use] + +#[cfg_attr(feature = "_usart_v1", path = "v1.rs")] +#[cfg_attr(feature = "_usart_v2", path = "v2.rs")] +mod _version; +pub use _version::*; + +use crate::gpio::Pin; +use crate::pac::usart::Usart; + +/// Serial error +#[derive(Debug, Eq, PartialEq, Copy, Clone)] +#[non_exhaustive] +pub enum Error { + /// Framing error + Framing, + /// Noise error + Noise, + /// RX buffer overrun + Overrun, + /// Parity check error + Parity, +} + +pub(crate) mod sealed { + use super::*; + + pub trait Instance { + fn regs(&self) -> Usart; + } + pub trait RxPin: Pin { + fn af_num(&self) -> u8; + } + pub trait TxPin: Pin { + fn af_num(&self) -> u8; + } + pub trait CtsPin: Pin { + fn af_num(&self) -> u8; + } + pub trait RtsPin: Pin { + fn af_num(&self) -> u8; + } + pub trait CkPin: Pin { + fn af_num(&self) -> u8; + } +} +pub trait Instance: sealed::Instance {} +pub trait RxPin: sealed::RxPin {} +pub trait TxPin: sealed::TxPin {} +pub trait CtsPin: sealed::CtsPin {} +pub trait RtsPin: sealed::RtsPin {} +pub trait CkPin: sealed::CkPin {} + +macro_rules! impl_usart { + ($inst:ident) => { + impl crate::usart::sealed::Instance for peripherals::$inst { + fn regs(&self) -> crate::pac::usart::Usart { + crate::pac::$inst + } + } + impl crate::usart::Instance for peripherals::$inst {} + }; +} + +macro_rules! impl_usart_pin { + ($inst:ident, $func:ident, $pin:ident, $af:expr) => { + impl crate::usart::sealed::$func for peripherals::$pin { + fn af_num(&self) -> u8 { + $af + } + } + impl crate::usart::$func for peripherals::$pin {} + }; +} diff --git a/embassy-stm32/src/usart/v1.rs b/embassy-stm32/src/usart/v1.rs new file mode 100644 index 00000000..78a53b53 --- /dev/null +++ b/embassy-stm32/src/usart/v1.rs @@ -0,0 +1,171 @@ +use core::marker::PhantomData; + +use embassy::util::Unborrow; +use embassy_extras::unborrow; + +use crate::gpio::{NoPin, Pin}; +use crate::pac::usart::{regs, vals, Usart}; + +use super::*; + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub enum DataBits { + DataBits8, + DataBits9, +} + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub enum Parity { + ParityNone, + ParityEven, + ParityOdd, +} + +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub enum StopBits { + #[doc = "1 stop bit"] + STOP1, + #[doc = "0.5 stop bits"] + STOP0P5, + #[doc = "2 stop bits"] + STOP2, + #[doc = "1.5 stop bits"] + STOP1P5, +} + +#[non_exhaustive] +#[derive(Clone, Copy, PartialEq, Eq, Debug)] +pub struct Config { + pub baudrate: u32, + pub data_bits: DataBits, + pub stop_bits: StopBits, + pub parity: Parity, +} + +impl Default for Config { + fn default() -> Self { + Self { + baudrate: 115200, + data_bits: DataBits::DataBits8, + stop_bits: StopBits::STOP1, + parity: Parity::ParityNone, + } + } +} + +pub struct Uart<'d, T: Instance> { + inner: T, + phantom: PhantomData<&'d mut T>, +} + +impl<'d, T: Instance> Uart<'d, T> { + pub fn new( + inner: impl Unborrow, + rx: impl Unborrow>, + tx: impl Unborrow>, + config: Config, + pclk_freq: u32, + ) -> Self { + unborrow!(inner, rx, tx); + + // TODO: enable in RCC + + // TODO: better calculation, including error checking and OVER8 if possible. + let div = (pclk_freq + (config.baudrate / 2)) / config.baudrate; + + let r = inner.regs(); + + unsafe { + rx.set_as_af(rx.af_num()); + tx.set_as_af(tx.af_num()); + + r.brr().write_value(regs::Brr(div)); + r.cr1().write(|w| { + w.set_ue(true); + w.set_te(true); + w.set_re(true); + w.set_m(vals::M::M8); + w.set_pce(config.parity != Parity::ParityNone); + w.set_ps(match config.parity { + Parity::ParityOdd => vals::Ps::ODD, + Parity::ParityEven => vals::Ps::EVEN, + _ => vals::Ps::EVEN, + }); + }); + r.cr2().write(|_w| {}); + r.cr3().write(|_w| {}); + } + + Self { + inner, + phantom: PhantomData, + } + } + + #[cfg(feature = "_dma_v2")] + pub async fn write_dma(&mut self, ch: &mut impl crate::dma::Channel, buffer: &[u8]) -> Result<(), Error> { + let ch_func = 4; // USART3_TX + let r = self.inner.regs(); + + unsafe { + r.cr3().write(|w| { + w.set_dmat(true); + }); + + let dst = r.dr().ptr() as *mut u8; + + crate::dma::transfer_m2p(ch, ch_func, buffer, dst).await; + } + + Ok(()) + } + + pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { + unsafe { + let r = self.inner.regs(); + for b in buffer { + loop { + let sr = r.sr().read(); + if sr.pe() { + r.dr().read(); + return Err(Error::Parity); + } else if sr.fe() { + r.dr().read(); + return Err(Error::Framing); + } else if sr.ne() { + r.dr().read(); + return Err(Error::Noise); + } else if sr.ore() { + r.dr().read(); + return Err(Error::Overrun); + } else if sr.rxne() { + break; + } + } + *b = r.dr().read().0 as u8; + } + } + Ok(()) + } +} + +impl<'d, T: Instance> embedded_hal::blocking::serial::Write for Uart<'d, T> { + type Error = Error; + fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> { + unsafe { + let r = self.inner.regs(); + for &b in buffer { + while !r.sr().read().txe() {} + r.dr().write_value(regs::Dr(b as u32)) + } + } + Ok(()) + } + fn bflush(&mut self) -> Result<(), Self::Error> { + unsafe { + let r = self.inner.regs(); + while !r.sr().read().tc() {} + } + Ok(()) + } +} diff --git a/embassy-stm32/src/usart/v2.rs b/embassy-stm32/src/usart/v2.rs new file mode 100644 index 00000000..e69de29b diff --git a/embassy-stm32/stm32-data b/embassy-stm32/stm32-data new file mode 160000 index 00000000..67db3905 --- /dev/null +++ b/embassy-stm32/stm32-data @@ -0,0 +1 @@ +Subproject commit 67db3905b34f062c55ceff09b1beac8444b78cab diff --git a/embassy-traits/src/flash.rs b/embassy-traits/src/flash.rs index c9b14a39..5e0a4e39 100644 --- a/embassy-traits/src/flash.rs +++ b/embassy-traits/src/flash.rs @@ -1,5 +1,4 @@ use core::future::Future; -use core::pin::Pin; #[derive(Copy, Clone, Debug, Eq, PartialEq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/embassy-traits/src/gpio.rs b/embassy-traits/src/gpio.rs index c4ae206c..9fdb41f5 100644 --- a/embassy-traits/src/gpio.rs +++ b/embassy-traits/src/gpio.rs @@ -1,5 +1,4 @@ use core::future::Future; -use core::pin::Pin; /// Wait for a pin to become high. pub trait WaitForHigh { diff --git a/embassy-traits/src/lib.rs b/embassy-traits/src/lib.rs index ceef0d2e..04741787 100644 --- a/embassy-traits/src/lib.rs +++ b/embassy-traits/src/lib.rs @@ -13,3 +13,4 @@ pub mod gpio; pub mod i2c; pub mod spi; pub mod uart; +pub mod rng; diff --git a/embassy-traits/src/rng.rs b/embassy-traits/src/rng.rs new file mode 100644 index 00000000..ddc4c20e --- /dev/null +++ b/embassy-traits/src/rng.rs @@ -0,0 +1,17 @@ +use core::future::Future; + +/// Random-number Generator +pub trait Rng { + type Error; + + type RngFuture<'a>: Future> + 'a + where + Self: 'a; + + /// Completely fill the provided buffer with random bytes. + /// + /// May result in delays if entropy is exhausted prior to completely + /// filling the buffer. Upon completion, the buffer will be completely + /// filled or an error will have been reported. + fn fill_bytes<'a>(&'a mut self, dest: &'a mut [u8]) -> Self::RngFuture<'a>; +} diff --git a/embassy-traits/src/spi.rs b/embassy-traits/src/spi.rs index 771ebf2f..227b8bfe 100644 --- a/embassy-traits/src/spi.rs +++ b/embassy-traits/src/spi.rs @@ -1,7 +1,6 @@ //! Async SPI API use core::future::Future; -use core::pin::Pin; /// Full duplex (master mode) /// diff --git a/embassy-traits/src/uart.rs b/embassy-traits/src/uart.rs index 9e76306b..755aee6d 100644 --- a/embassy-traits/src/uart.rs +++ b/embassy-traits/src/uart.rs @@ -1,5 +1,4 @@ use core::future::Future; -use core::pin::Pin; #[derive(Copy, Clone, Debug, Eq, PartialEq)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/embassy/src/util/mod.rs b/embassy/src/util/mod.rs index 6aa3a733..7de15d4a 100644 --- a/embassy/src/util/mod.rs +++ b/embassy/src/util/mod.rs @@ -25,3 +25,44 @@ pub trait Unborrow { pub trait Steal { unsafe fn steal() -> Self; } + +macro_rules! impl_unborrow_tuples { + ($($t:ident),+) => { + impl<$($t),+> Unborrow for ($($t),+) + where + $( + $t: Unborrow + ),+ + { + type Target = ($($t),+); + unsafe fn unborrow(self) -> Self::Target { + self + } + } + + impl<'a, $($t),+> Unborrow for &'a mut($($t),+) + where + $( + $t: Unborrow + ),+ + { + type Target = ($($t),+); + unsafe fn unborrow(self) -> Self::Target { + ::core::ptr::read(self) + } + } + + }; +} + +impl_unborrow_tuples!(A, B); +impl_unborrow_tuples!(A, B, C); +impl_unborrow_tuples!(A, B, C, D); +impl_unborrow_tuples!(A, B, C, D, E); +impl_unborrow_tuples!(A, B, C, D, E, F); +impl_unborrow_tuples!(A, B, C, D, E, F, G); +impl_unborrow_tuples!(A, B, C, D, E, F, G, H); +impl_unborrow_tuples!(A, B, C, D, E, F, G, H, I); +impl_unborrow_tuples!(A, B, C, D, E, F, G, H, I, J); +impl_unborrow_tuples!(A, B, C, D, E, F, G, H, I, J, K); +impl_unborrow_tuples!(A, B, C, D, E, F, G, H, I, J, K, L);