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Update rp-pac.

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This commit is contained in:
Dario Nieuwenhuis 2023-06-29 02:08:55 +02:00
parent 8cbe5b8e20
commit ce889900d6
4 changed files with 51 additions and 51 deletions
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2
embassy-rp/Cargo.toml
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@ -76,7 +76,7 @@ embedded-storage = { version = "0.3" }
rand_core = "0.6.4" rand_core = "0.6.4"
fixed = "1.23.1" fixed = "1.23.1"
rp-pac = { version = "5" } rp-pac = { version = "6" }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] } embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true} embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}

92
embassy-rp/src/clocks.rs
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@ -46,13 +46,13 @@ static CLOCKS: Clocks = Clocks {
#[non_exhaustive] #[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)] #[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum PeriClkSrc { pub enum PeriClkSrc {
Sys = ClkPeriCtrlAuxsrc::CLK_SYS.0, Sys = ClkPeriCtrlAuxsrc::CLK_SYS as _,
PllSys = ClkPeriCtrlAuxsrc::CLKSRC_PLL_SYS.0, PllSys = ClkPeriCtrlAuxsrc::CLKSRC_PLL_SYS as _,
PllUsb = ClkPeriCtrlAuxsrc::CLKSRC_PLL_USB.0, PllUsb = ClkPeriCtrlAuxsrc::CLKSRC_PLL_USB as _,
Rosc = ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH.0, Rosc = ClkPeriCtrlAuxsrc::ROSC_CLKSRC_PH as _,
Xosc = ClkPeriCtrlAuxsrc::XOSC_CLKSRC.0, Xosc = ClkPeriCtrlAuxsrc::XOSC_CLKSRC as _,
// Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0.0, // Gpin0 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
// Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1.0, // Gpin1 = ClkPeriCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
} }
#[non_exhaustive] #[non_exhaustive]
@ -251,12 +251,12 @@ pub struct SysClkConfig {
#[non_exhaustive] #[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)] #[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UsbClkSrc { pub enum UsbClkSrc {
PllUsb = ClkUsbCtrlAuxsrc::CLKSRC_PLL_USB.0, PllUsb = ClkUsbCtrlAuxsrc::CLKSRC_PLL_USB as _,
PllSys = ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS.0, PllSys = ClkUsbCtrlAuxsrc::CLKSRC_PLL_SYS as _,
Rosc = ClkUsbCtrlAuxsrc::ROSC_CLKSRC_PH.0, Rosc = ClkUsbCtrlAuxsrc::ROSC_CLKSRC_PH as _,
Xosc = ClkUsbCtrlAuxsrc::XOSC_CLKSRC.0, Xosc = ClkUsbCtrlAuxsrc::XOSC_CLKSRC as _,
// Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0.0, // Gpin0 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
// Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1.0, // Gpin1 = ClkUsbCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
} }
pub struct UsbClkConfig { pub struct UsbClkConfig {
@ -269,12 +269,12 @@ pub struct UsbClkConfig {
#[non_exhaustive] #[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)] #[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum AdcClkSrc { pub enum AdcClkSrc {
PllUsb = ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB.0, PllUsb = ClkAdcCtrlAuxsrc::CLKSRC_PLL_USB as _,
PllSys = ClkAdcCtrlAuxsrc::CLKSRC_PLL_SYS.0, PllSys = ClkAdcCtrlAuxsrc::CLKSRC_PLL_SYS as _,
Rosc = ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH.0, Rosc = ClkAdcCtrlAuxsrc::ROSC_CLKSRC_PH as _,
Xosc = ClkAdcCtrlAuxsrc::XOSC_CLKSRC.0, Xosc = ClkAdcCtrlAuxsrc::XOSC_CLKSRC as _,
// Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0.0, // Gpin0 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
// Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1.0, // Gpin1 = ClkAdcCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
} }
pub struct AdcClkConfig { pub struct AdcClkConfig {
@ -287,12 +287,12 @@ pub struct AdcClkConfig {
#[non_exhaustive] #[non_exhaustive]
#[derive(Clone, Copy, Debug, PartialEq, Eq)] #[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum RtcClkSrc { pub enum RtcClkSrc {
PllUsb = ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB.0, PllUsb = ClkRtcCtrlAuxsrc::CLKSRC_PLL_USB as _,
PllSys = ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS.0, PllSys = ClkRtcCtrlAuxsrc::CLKSRC_PLL_SYS as _,
Rosc = ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH.0, Rosc = ClkRtcCtrlAuxsrc::ROSC_CLKSRC_PH as _,
Xosc = ClkRtcCtrlAuxsrc::XOSC_CLKSRC.0, Xosc = ClkRtcCtrlAuxsrc::XOSC_CLKSRC as _,
// Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0.0, // Gpin0 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
// Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1.0, // Gpin1 = ClkRtcCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
} }
pub struct RtcClkConfig { pub struct RtcClkConfig {
@ -396,7 +396,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
w.set_src(ref_src); w.set_src(ref_src);
w.set_auxsrc(ref_aux); w.set_auxsrc(ref_aux);
}); });
while c.clk_ref_selected().read() != 1 << ref_src.0 {} while c.clk_ref_selected().read() != 1 << ref_src as u32 {}
c.clk_ref_div().write(|w| { c.clk_ref_div().write(|w| {
w.set_int(config.ref_clk.div); w.set_int(config.ref_clk.div);
}); });
@ -425,13 +425,13 @@ pub(crate) unsafe fn init(config: ClockConfig) {
CLOCKS.sys.store(clk_sys_freq, Ordering::Relaxed); CLOCKS.sys.store(clk_sys_freq, Ordering::Relaxed);
if sys_src != ClkSysCtrlSrc::CLK_REF { if sys_src != ClkSysCtrlSrc::CLK_REF {
c.clk_sys_ctrl().write(|w| w.set_src(ClkSysCtrlSrc::CLK_REF)); c.clk_sys_ctrl().write(|w| w.set_src(ClkSysCtrlSrc::CLK_REF));
while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF.0 {} while c.clk_sys_selected().read() != 1 << ClkSysCtrlSrc::CLK_REF as u32 {}
} }
c.clk_sys_ctrl().write(|w| { c.clk_sys_ctrl().write(|w| {
w.set_auxsrc(sys_aux); w.set_auxsrc(sys_aux);
w.set_src(sys_src); w.set_src(sys_src);
}); });
while c.clk_sys_selected().read() != 1 << sys_src.0 {} while c.clk_sys_selected().read() != 1 << sys_src as u32 {}
c.clk_sys_div().write(|w| { c.clk_sys_div().write(|w| {
w.set_int(config.sys_clk.div_int); w.set_int(config.sys_clk.div_int);
w.set_frac(config.sys_clk.div_frac); w.set_frac(config.sys_clk.div_frac);
@ -442,7 +442,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
if let Some(src) = config.peri_clk_src { if let Some(src) = config.peri_clk_src {
c.clk_peri_ctrl().write(|w| { c.clk_peri_ctrl().write(|w| {
w.set_enable(true); w.set_enable(true);
w.set_auxsrc(ClkPeriCtrlAuxsrc(src as _)); w.set_auxsrc(ClkPeriCtrlAuxsrc::from_bits(src as _));
}); });
let peri_freq = match src { let peri_freq = match src {
PeriClkSrc::Sys => clk_sys_freq, PeriClkSrc::Sys => clk_sys_freq,
@ -468,7 +468,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_usb_ctrl().write(|w| { c.clk_usb_ctrl().write(|w| {
w.set_phase(conf.phase); w.set_phase(conf.phase);
w.set_enable(true); w.set_enable(true);
w.set_auxsrc(ClkUsbCtrlAuxsrc(conf.src as _)); w.set_auxsrc(ClkUsbCtrlAuxsrc::from_bits(conf.src as _));
}); });
let usb_freq = match conf.src { let usb_freq = match conf.src {
UsbClkSrc::PllUsb => pll_usb_freq, UsbClkSrc::PllUsb => pll_usb_freq,
@ -491,7 +491,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_adc_ctrl().write(|w| { c.clk_adc_ctrl().write(|w| {
w.set_phase(conf.phase); w.set_phase(conf.phase);
w.set_enable(true); w.set_enable(true);
w.set_auxsrc(ClkAdcCtrlAuxsrc(conf.src as _)); w.set_auxsrc(ClkAdcCtrlAuxsrc::from_bits(conf.src as _));
}); });
let adc_in_freq = match conf.src { let adc_in_freq = match conf.src {
AdcClkSrc::PllUsb => pll_usb_freq, AdcClkSrc::PllUsb => pll_usb_freq,
@ -517,7 +517,7 @@ pub(crate) unsafe fn init(config: ClockConfig) {
c.clk_rtc_ctrl().write(|w| { c.clk_rtc_ctrl().write(|w| {
w.set_phase(conf.phase); w.set_phase(conf.phase);
w.set_enable(true); w.set_enable(true);
w.set_auxsrc(ClkRtcCtrlAuxsrc(conf.src as _)); w.set_auxsrc(ClkRtcCtrlAuxsrc::from_bits(conf.src as _));
}); });
let rtc_in_freq = match conf.src { let rtc_in_freq = match conf.src {
RtcClkSrc::PllUsb => pll_usb_freq, RtcClkSrc::PllUsb => pll_usb_freq,
@ -718,7 +718,7 @@ impl<'d, T: Pin> Drop for Gpin<'d, T> {
self.gpin self.gpin
.io() .io()
.ctrl() .ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0)); .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
} }
} }
@ -743,17 +743,17 @@ impl_gpoutpin!(PIN_25, 3);
#[repr(u8)] #[repr(u8)]
pub enum GpoutSrc { pub enum GpoutSrc {
PllSys = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS.0, PllSys = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_SYS as _,
// Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0.0, // Gpin0 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN0 as _ ,
// Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1.0, // Gpin1 = ClkGpoutCtrlAuxsrc::CLKSRC_GPIN1 as _ ,
PllUsb = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB.0, PllUsb = ClkGpoutCtrlAuxsrc::CLKSRC_PLL_USB as _,
Rosc = ClkGpoutCtrlAuxsrc::ROSC_CLKSRC.0, Rosc = ClkGpoutCtrlAuxsrc::ROSC_CLKSRC as _,
Xosc = ClkGpoutCtrlAuxsrc::XOSC_CLKSRC.0, Xosc = ClkGpoutCtrlAuxsrc::XOSC_CLKSRC as _,
Sys = ClkGpoutCtrlAuxsrc::CLK_SYS.0, Sys = ClkGpoutCtrlAuxsrc::CLK_SYS as _,
Usb = ClkGpoutCtrlAuxsrc::CLK_USB.0, Usb = ClkGpoutCtrlAuxsrc::CLK_USB as _,
Adc = ClkGpoutCtrlAuxsrc::CLK_ADC.0, Adc = ClkGpoutCtrlAuxsrc::CLK_ADC as _,
Rtc = ClkGpoutCtrlAuxsrc::CLK_RTC.0, Rtc = ClkGpoutCtrlAuxsrc::CLK_RTC as _,
Ref = ClkGpoutCtrlAuxsrc::CLK_REF.0, Ref = ClkGpoutCtrlAuxsrc::CLK_REF as _,
} }
pub struct Gpout<'d, T: GpoutPin> { pub struct Gpout<'d, T: GpoutPin> {
@ -780,7 +780,7 @@ impl<'d, T: GpoutPin> Gpout<'d, T> {
pub fn set_src(&self, src: GpoutSrc) { pub fn set_src(&self, src: GpoutSrc) {
let c = pac::CLOCKS; let c = pac::CLOCKS;
c.clk_gpout_ctrl(self.gpout.number()).modify(|w| { c.clk_gpout_ctrl(self.gpout.number()).modify(|w| {
w.set_auxsrc(ClkGpoutCtrlAuxsrc(src as _)); w.set_auxsrc(ClkGpoutCtrlAuxsrc::from_bits(src as _));
}); });
} }
@ -831,7 +831,7 @@ impl<'d, T: GpoutPin> Drop for Gpout<'d, T> {
self.gpout self.gpout
.io() .io()
.ctrl() .ctrl()
.write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0)); .write(|w| w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _));
} }
} }

4
embassy-rp/src/gpio.rs
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@ -452,7 +452,7 @@ impl<'d, T: Pin> Flex<'d, T> {
}); });
pin.io().ctrl().write(|w| { pin.io().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0.0); w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::SIO_0 as _);
}); });
Self { pin } Self { pin }
@ -618,7 +618,7 @@ impl<'d, T: Pin> Drop for Flex<'d, T> {
fn drop(&mut self) { fn drop(&mut self) {
self.pin.pad_ctrl().write(|_| {}); self.pin.pad_ctrl().write(|_| {});
self.pin.io().ctrl().write(|w| { self.pin.io().ctrl().write(|w| {
w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL.0); w.set_funcsel(pac::io::vals::Gpio0ctrlFuncsel::NULL as _);
}); });
} }
} }

4
embassy-rp/src/pio.rs
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@ -834,7 +834,7 @@ impl<'d, PIO: Instance> Common<'d, PIO> {
/// of [`Pio`] do not keep pin registrations alive.** /// of [`Pio`] do not keep pin registrations alive.**
pub fn make_pio_pin(&mut self, pin: impl Peripheral<P = impl PioPin + 'd> + 'd) -> Pin<'d, PIO> { pub fn make_pio_pin(&mut self, pin: impl Peripheral<P = impl PioPin + 'd> + 'd) -> Pin<'d, PIO> {
into_ref!(pin); into_ref!(pin);
pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL.0)); pin.io().ctrl().write(|w| w.set_funcsel(PIO::FUNCSEL as _));
// we can be relaxed about this because we're &mut here and nothing is cached // we can be relaxed about this because we're &mut here and nothing is cached
PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed); PIO::state().used_pins.fetch_or(1 << pin.pin_bank(), Ordering::Relaxed);
Pin { Pin {
@ -998,7 +998,7 @@ fn on_pio_drop<PIO: Instance>() {
let state = PIO::state(); let state = PIO::state();
if state.users.fetch_sub(1, Ordering::AcqRel) == 1 { if state.users.fetch_sub(1, Ordering::AcqRel) == 1 {
let used_pins = state.used_pins.load(Ordering::Relaxed); let used_pins = state.used_pins.load(Ordering::Relaxed);
let null = Gpio0ctrlFuncsel::NULL.0; let null = Gpio0ctrlFuncsel::NULL as _;
// we only have 30 pins. don't test the other two since gpio() asserts. // we only have 30 pins. don't test the other two since gpio() asserts.
for i in 0..30 { for i in 0..30 {
if used_pins & (1 << i) != 0 { if used_pins & (1 << i) != 0 {