Rename write to respond_to_read
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633ffe46ae
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cf900a8a3f
@ -507,7 +507,7 @@ impl<'d, T: Instance> Twis<'d, T> {
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})
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})
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}
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}
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fn setup_write_from_ram(&mut self, buffer: &[u8], inten: bool) -> Result<(), Error> {
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fn setup_respond_from_ram(&mut self, buffer: &[u8], inten: bool) -> Result<(), Error> {
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let r = T::regs();
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let r = T::regs();
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compiler_fence(SeqCst);
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compiler_fence(SeqCst);
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@ -532,14 +532,14 @@ impl<'d, T: Instance> Twis<'d, T> {
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Ok(())
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Ok(())
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}
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}
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fn setup_write(&mut self, wr_buffer: &[u8], inten: bool) -> Result<(), Error> {
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fn setup_respond(&mut self, wr_buffer: &[u8], inten: bool) -> Result<(), Error> {
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match self.setup_write_from_ram(wr_buffer, inten) {
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match self.setup_respond_from_ram(wr_buffer, inten) {
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Ok(_) => Ok(()),
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Ok(_) => Ok(()),
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Err(Error::DMABufferNotInDataMemory) => {
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Err(Error::DMABufferNotInDataMemory) => {
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trace!("Copying TWIS tx buffer into RAM for DMA");
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trace!("Copying TWIS tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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tx_ram_buf.copy_from_slice(wr_buffer);
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tx_ram_buf.copy_from_slice(wr_buffer);
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self.setup_write_from_ram(&tx_ram_buf, inten)
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self.setup_respond_from_ram(&tx_ram_buf, inten)
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}
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}
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Err(error) => Err(error),
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Err(error) => Err(error),
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}
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}
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@ -609,18 +609,19 @@ impl<'d, T: Instance> Twis<'d, T> {
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Ok(Command::Read)
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Ok(Command::Read)
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}
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}
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/// Write to an I2C master.
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/// Respond to an I2C master READ command.
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/// Returns the number of bytes written.
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/// Returns the number of bytes written.
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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/// and at most 65535 bytes on the nRF52840.
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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pub fn blocking_respond_to_read(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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self.setup_write(buffer, false)?;
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self.setup_respond(buffer, false)?;
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self.blocking_wait()
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self.blocking_wait()
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}
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}
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/// Same as [`blocking_write`](Twis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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/// Same as [`blocking_respond_to_read`](Twis::blocking_respond_to_read) but will fail instead of copying data into RAM.
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pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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/// Consult the module level documentation to learn more.
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self.setup_write_from_ram(buffer, false)?;
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pub fn blocking_respond_to_read_from_ram(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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self.setup_respond_from_ram(buffer, false)?;
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self.blocking_wait()
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self.blocking_wait()
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}
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}
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@ -643,19 +644,24 @@ impl<'d, T: Instance> Twis<'d, T> {
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Ok(Command::Read)
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Ok(Command::Read)
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}
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}
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/// Write to an I2C master with timeout.
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/// Respond to an I2C master READ command with timeout.
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/// Returns the number of bytes written.
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/// Returns the number of bytes written.
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/// See [`blocking_write`].
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/// See [`blocking_respond_to_read`].
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#[cfg(feature = "time")]
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#[cfg(feature = "time")]
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pub fn blocking_write_timeout(&mut self, buffer: &[u8], timeout: Duration) -> Result<usize, Error> {
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pub fn blocking_respond_to_read_timeout(&mut self, buffer: &[u8], timeout: Duration) -> Result<usize, Error> {
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self.setup_write(buffer, false)?;
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self.setup_respond(buffer, false)?;
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self.blocking_wait_timeout(timeout)
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self.blocking_wait_timeout(timeout)
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}
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}
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/// Same as [`blocking_write`](Twis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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/// Same as [`blocking_respond_to_read_timeout`](Twis::blocking_respond_to_read_timeout) but will fail instead of copying data into RAM.
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/// Consult the module level documentation to learn more.
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#[cfg(feature = "time")]
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#[cfg(feature = "time")]
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pub fn blocking_write_from_ram_timeout(&mut self, buffer: &[u8], timeout: Duration) -> Result<usize, Error> {
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pub fn blocking_respond_to_read_from_ram_timeout(
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self.setup_write_from_ram(buffer, false)?;
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&mut self,
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buffer: &[u8],
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timeout: Duration,
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) -> Result<usize, Error> {
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self.setup_respond_from_ram(buffer, false)?;
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self.blocking_wait_timeout(timeout)
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self.blocking_wait_timeout(timeout)
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}
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}
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@ -677,18 +683,18 @@ impl<'d, T: Instance> Twis<'d, T> {
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Ok(Command::Read)
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Ok(Command::Read)
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}
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}
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/// Async write to an I2C master.
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/// Respond to an I2C master READ command, asynchronously.
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/// Returns the number of bytes written.
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/// Returns the number of bytes written.
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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/// and at most 65535 bytes on the nRF52840.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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pub async fn respond_to_read(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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self.setup_write(buffer, true)?;
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self.setup_respond(buffer, true)?;
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self.async_wait().await
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self.async_wait().await
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}
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}
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/// Same as [`write`](Twis::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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/// Same as [`respond_to_read`](Twis::respond_to_read) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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pub async fn respond_to_read_from_ram(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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self.setup_write_from_ram(buffer, true)?;
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self.setup_respond_from_ram(buffer, true)?;
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self.async_wait().await
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self.async_wait().await
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}
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}
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}
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}
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@ -22,20 +22,21 @@ async fn main(_spawner: Spawner) {
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info!("Listening...");
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info!("Listening...");
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loop {
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loop {
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let response = [1, 2, 3, 4, 5, 6, 7, 8];
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// This buffer is used if the i2c master performs a Write or WriteRead
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let mut buf = [0u8; 16];
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let mut buf = [0u8; 16];
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let tx_buf = [1, 2, 3, 4, 5, 6, 7, 8];
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match i2c.listen(&mut buf).await {
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match i2c.listen(&mut buf).await {
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Ok(Command::Read) => {
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Ok(Command::Read) => {
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info!("Got READ command. Writing back data:\n{:?}\n", tx_buf);
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info!("Got READ command. Respond with data:\n{:?}\n", response);
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if let Err(e) = i2c.write(&tx_buf).await {
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if let Err(e) = i2c.respond_to_read(&response).await {
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error!("{:?}", e);
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error!("{:?}", e);
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}
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}
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}
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}
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Ok(Command::Write(n)) => info!("Got WRITE command with data:\n{:?}\n", buf[..n]),
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Ok(Command::Write(n)) => info!("Got WRITE command with data:\n{:?}\n", buf[..n]),
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Ok(Command::WriteRead(n)) => {
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Ok(Command::WriteRead(n)) => {
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info!("Got WRITE/READ command with data:\n{:?}", buf[..n]);
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info!("Got WRITE/READ command with data:\n{:?}", buf[..n]);
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info!("Writing back data:\n{:?}\n", tx_buf);
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info!("Respond with data:\n{:?}\n", response);
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if let Err(e) = i2c.write(&tx_buf).await {
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if let Err(e) = i2c.respond_to_read(&response).await {
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error!("{:?}", e);
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error!("{:?}", e);
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}
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}
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}
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}
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