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Fix STM32 timer interrupt bug

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This commit is contained in:
chemicstry 2022-03-30 00:27:33 +03:00
parent 1a31cda3c3
commit d052631118
1 changed files with 6 additions and 2 deletions
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8
embassy-stm32/src/time_driver.rs
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@ -172,8 +172,11 @@ impl RtcDriver {
// Mid-way point // Mid-way point
r.ccr(0).write(|w| w.set_ccr(0x8000)); r.ccr(0).write(|w| w.set_ccr(0x8000));
// Enable CC0, disable others // Enable overflow and half-overflow interrupts
r.dier().write(|w| w.set_ccie(0, true)); r.dier().write(|w| {
w.set_uie(true);
w.set_ccie(0, true);
});
let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(()); let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(());
irq.unpend(); irq.unpend();
@ -197,6 +200,7 @@ impl RtcDriver {
// miss interrupts. // miss interrupts.
r.sr().write_value(regs::SrGp(!sr.0)); r.sr().write_value(regs::SrGp(!sr.0));
// Overflow
if sr.uif() { if sr.uif() {
self.next_period(); self.next_period();
} }