From d0d8585e4cdb73373ead13289a28b7d155377963 Mon Sep 17 00:00:00 2001
From: shakencodes <shakencodes@gmail.com>
Date: Wed, 1 Nov 2023 11:46:17 -0700
Subject: [PATCH] Reinstate rcc::Config adc_clock_source field

---
 embassy-stm32/src/rcc/l4l5.rs | 34 +++++++++++++++++++++++++++++++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/embassy-stm32/src/rcc/l4l5.rs b/embassy-stm32/src/rcc/l4l5.rs
index 2f89f682..a7c136a3 100644
--- a/embassy-stm32/src/rcc/l4l5.rs
+++ b/embassy-stm32/src/rcc/l4l5.rs
@@ -4,8 +4,8 @@ pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
 #[cfg(any(stm32wb, stm32wl))]
 pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
 pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
-    Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
+    Adcsel, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv,
+    Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
 };
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
@@ -52,7 +52,30 @@ pub struct Pll {
     pub divr: Option<PllRDiv>,
 }
 
-/// Clocks configutation
+#[derive(Clone, Copy)]
+pub enum AdcClockSource {
+    HSI16,
+    PLLPCLK,
+    SYSCLK,
+}
+
+impl AdcClockSource {
+    pub fn adcsel(&self) -> Adcsel {
+        match self {
+            AdcClockSource::HSI16 => Adcsel::HSI,
+            AdcClockSource::PLLPCLK => Adcsel::PLL1_P,
+            AdcClockSource::SYSCLK => Adcsel::SYS,
+        }
+    }
+}
+
+impl Default for AdcClockSource {
+    fn default() -> Self {
+        Self::HSI16
+    }
+}
+
+/// Clocks configuration
 pub struct Config {
     // base clock sources
     pub msi: Option<MSIRange>,
@@ -84,6 +107,8 @@ pub struct Config {
 
     // low speed LSI/LSE/RTC
     pub ls: super::LsConfig,
+
+    pub adc_clock_source: AdcClockSource,
 }
 
 impl Default for Config {
@@ -111,6 +136,7 @@ impl Default for Config {
             #[cfg(any(stm32l4, stm32l5, stm32wb))]
             clk48_src: Clk48Src::HSI48,
             ls: Default::default(),
+            adc_clock_source: AdcClockSource::default(),
         }
     }
 }
@@ -344,6 +370,8 @@ pub(crate) unsafe fn init(config: Config) {
     });
     while RCC.cfgr().read().sws() != config.mux {}
 
+    RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source.adcsel()));
+
     #[cfg(any(stm32wl, stm32wb))]
     {
         RCC.extcfgr().modify(|w| {