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Merge pull request #1524 from embassy-rs/remove-irqs

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Remove owned interrupts, PeripheralMutex.
This commit is contained in:
Dario Nieuwenhuis 2023-06-01 01:31:05 +00:00 committed by GitHub
commit d36feb6405
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GPG Key ID: 4AEE18F83AFDEB23
56 changed files with 239 additions and 584 deletions
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180
embassy-cortex-m/src/interrupt.rs
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@ -1,10 +1,8 @@
//! Interrupt handling for cortex-m devices. //! Interrupt handling for cortex-m devices.
use core::{mem, ptr}; use core::mem;
use core::sync::atomic::{compiler_fence, Ordering};
use atomic_polyfill::{compiler_fence, AtomicPtr, Ordering};
use cortex_m::peripheral::NVIC; use cortex_m::peripheral::NVIC;
use embassy_hal_common::Peripheral;
pub use embassy_macros::cortex_m_interrupt_take as take;
/// Do not use. Used for macros and HALs only. Not covered by semver guarantees. /// Do not use. Used for macros and HALs only. Not covered by semver guarantees.
#[doc(hidden)] #[doc(hidden)]
@ -43,22 +41,6 @@ pub trait Handler<I: Interrupt> {
/// This allows drivers to check bindings at compile-time. /// This allows drivers to check bindings at compile-time.
pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {} pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {}
/// Implementation detail, do not use outside embassy crates.
#[doc(hidden)]
pub struct DynHandler {
pub func: AtomicPtr<()>,
pub ctx: AtomicPtr<()>,
}
impl DynHandler {
pub const fn new() -> Self {
Self {
func: AtomicPtr::new(ptr::null_mut()),
ctx: AtomicPtr::new(ptr::null_mut()),
}
}
}
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
pub(crate) struct NrWrap(pub(crate) u16); pub(crate) struct NrWrap(pub(crate) u16);
unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap { unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
@ -69,144 +51,68 @@ unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
/// Represents an interrupt type that can be configured by embassy to handle /// Represents an interrupt type that can be configured by embassy to handle
/// interrupts. /// interrupts.
pub unsafe trait Interrupt: Peripheral<P = Self> { pub unsafe trait Interrupt {
/// Return the NVIC interrupt number for this interrupt. /// Return the NVIC interrupt number for this interrupt.
fn number(&self) -> u16; fn number() -> u16;
/// Steal an instance of this interrupt
///
/// # Safety
///
/// This may panic if the interrupt has already been stolen and configured.
unsafe fn steal() -> Self;
/// Implementation detail, do not use outside embassy crates. /// Enable the interrupt.
#[doc(hidden)] #[inline]
unsafe fn __handler(&self) -> &'static DynHandler; unsafe fn enable() {
} compiler_fence(Ordering::SeqCst);
NVIC::unmask(NrWrap(Self::number()))
/// Represents additional behavior for all interrupts. }
pub trait InterruptExt: Interrupt {
/// Configure the interrupt handler for this interrupt.
///
/// # Safety
///
/// It is the responsibility of the caller to ensure the handler
/// points to a valid handler as long as interrupts are enabled.
fn set_handler(&self, func: unsafe fn(*mut ()));
/// Remove the interrupt handler for this interrupt.
fn remove_handler(&self);
/// Set point to a context that is passed to the interrupt handler when
/// an interrupt is pending.
///
/// # Safety
///
/// It is the responsibility of the caller to ensure the context
/// points to a valid handler as long as interrupts are enabled.
fn set_handler_context(&self, ctx: *mut ());
/// Enable the interrupt. Once enabled, the interrupt handler may
/// be called "any time".
fn enable(&self);
/// Disable the interrupt. /// Disable the interrupt.
fn disable(&self); #[inline]
fn disable() {
NVIC::mask(NrWrap(Self::number()));
compiler_fence(Ordering::SeqCst);
}
/// Check if interrupt is being handled. /// Check if interrupt is being handled.
#[inline]
#[cfg(not(armv6m))] #[cfg(not(armv6m))]
fn is_active(&self) -> bool; fn is_active() -> bool {
NVIC::is_active(NrWrap(Self::number()))
}
/// Check if interrupt is enabled. /// Check if interrupt is enabled.
fn is_enabled(&self) -> bool; #[inline]
fn is_enabled() -> bool {
NVIC::is_enabled(NrWrap(Self::number()))
}
/// Check if interrupt is pending. /// Check if interrupt is pending.
fn is_pending(&self) -> bool; #[inline]
fn is_pending() -> bool {
NVIC::is_pending(NrWrap(Self::number()))
}
/// Set interrupt pending. /// Set interrupt pending.
fn pend(&self); #[inline]
fn pend() {
NVIC::pend(NrWrap(Self::number()))
}
/// Unset interrupt pending. /// Unset interrupt pending.
fn unpend(&self); #[inline]
fn unpend() {
NVIC::unpend(NrWrap(Self::number()))
}
/// Get the priority of the interrupt. /// Get the priority of the interrupt.
fn get_priority(&self) -> Priority; #[inline]
fn get_priority() -> Priority {
Priority::from(NVIC::get_priority(NrWrap(Self::number())))
}
/// Set the interrupt priority. /// Set the interrupt priority.
fn set_priority(&self, prio: Priority);
}
impl<T: Interrupt + ?Sized> InterruptExt for T {
fn set_handler(&self, func: unsafe fn(*mut ())) {
compiler_fence(Ordering::SeqCst);
let handler = unsafe { self.__handler() };
handler.func.store(func as *mut (), Ordering::Relaxed);
compiler_fence(Ordering::SeqCst);
}
fn remove_handler(&self) {
compiler_fence(Ordering::SeqCst);
let handler = unsafe { self.__handler() };
handler.func.store(ptr::null_mut(), Ordering::Relaxed);
compiler_fence(Ordering::SeqCst);
}
fn set_handler_context(&self, ctx: *mut ()) {
let handler = unsafe { self.__handler() };
handler.ctx.store(ctx, Ordering::Relaxed);
}
#[inline] #[inline]
fn enable(&self) { fn set_priority(prio: Priority) {
compiler_fence(Ordering::SeqCst); critical_section::with(|_| unsafe {
unsafe {
NVIC::unmask(NrWrap(self.number()));
}
}
#[inline]
fn disable(&self) {
NVIC::mask(NrWrap(self.number()));
compiler_fence(Ordering::SeqCst);
}
#[inline]
#[cfg(not(armv6m))]
fn is_active(&self) -> bool {
NVIC::is_active(NrWrap(self.number()))
}
#[inline]
fn is_enabled(&self) -> bool {
NVIC::is_enabled(NrWrap(self.number()))
}
#[inline]
fn is_pending(&self) -> bool {
NVIC::is_pending(NrWrap(self.number()))
}
#[inline]
fn pend(&self) {
NVIC::pend(NrWrap(self.number()))
}
#[inline]
fn unpend(&self) {
NVIC::unpend(NrWrap(self.number()))
}
#[inline]
fn get_priority(&self) -> Priority {
Priority::from(NVIC::get_priority(NrWrap(self.number())))
}
#[inline]
fn set_priority(&self, prio: Priority) {
unsafe {
let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(()); let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(());
nvic.set_priority(NrWrap(self.number()), prio.into()) nvic.set_priority(NrWrap(Self::number()), prio.into())
} })
} }
} }

1
embassy-cortex-m/src/lib.rs
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@ -7,4 +7,3 @@ pub(crate) mod fmt;
pub use embassy_executor as executor; pub use embassy_executor as executor;
pub mod interrupt; pub mod interrupt;
pub mod peripheral;

144
embassy-cortex-m/src/peripheral.rs
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@ -1,144 +0,0 @@
//! Peripheral interrupt handling specific to cortex-m devices.
use core::mem::MaybeUninit;
use cortex_m::peripheral::scb::VectActive;
use cortex_m::peripheral::{NVIC, SCB};
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use crate::interrupt::{Interrupt, InterruptExt, Priority};
/// A type which can be used as state with `PeripheralMutex`.
///
/// It needs to be `Send` because `&mut` references are sent back and forth between the 'thread' which owns the `PeripheralMutex` and the interrupt,
/// and `&mut T` is only `Send` where `T: Send`.
pub trait PeripheralState: Send {
/// The interrupt that is used for this peripheral.
type Interrupt: Interrupt;
/// The interrupt handler that should be invoked for the peripheral. Implementations need to clear the appropriate interrupt flags to ensure the handle will not be called again.
fn on_interrupt(&mut self);
}
/// A type for storing the state of a peripheral that can be stored in a static.
pub struct StateStorage<S>(MaybeUninit<S>);
impl<S> StateStorage<S> {
/// Create a new instance for storing peripheral state.
pub const fn new() -> Self {
Self(MaybeUninit::uninit())
}
}
/// A type for a peripheral that keeps the state of a peripheral that can be accessed from thread mode and an interrupt handler in
/// a safe way.
pub struct PeripheralMutex<'a, S: PeripheralState> {
state: *mut S,
irq: PeripheralRef<'a, S::Interrupt>,
}
/// Whether `irq` can be preempted by the current interrupt.
pub(crate) fn can_be_preempted(irq: &impl Interrupt) -> bool {
match SCB::vect_active() {
// Thread mode can't preempt anything.
VectActive::ThreadMode => false,
// Exceptions don't always preempt interrupts,
// but there isn't much of a good reason to be keeping a `PeripheralMutex` in an exception anyway.
VectActive::Exception(_) => true,
VectActive::Interrupt { irqn } => {
#[derive(Clone, Copy)]
struct NrWrap(u16);
unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
fn number(self) -> u16 {
self.0
}
}
NVIC::get_priority(NrWrap(irqn.into())) < irq.get_priority().into()
}
}
}
impl<'a, S: PeripheralState> PeripheralMutex<'a, S> {
/// Create a new `PeripheralMutex` wrapping `irq`, with `init` initializing the initial state.
///
/// Registers `on_interrupt` as the `irq`'s handler, and enables it.
pub fn new(
irq: impl Peripheral<P = S::Interrupt> + 'a,
storage: &'a mut StateStorage<S>,
init: impl FnOnce() -> S,
) -> Self {
into_ref!(irq);
if can_be_preempted(&*irq) {
panic!(
"`PeripheralMutex` cannot be created in an interrupt with higher priority than the interrupt it wraps"
);
}
let state_ptr = storage.0.as_mut_ptr();
// Safety: The pointer is valid and not used by anyone else
// because we have the `&mut StateStorage`.
unsafe { state_ptr.write(init()) };
irq.disable();
irq.set_handler(|p| unsafe {
// Safety: it's OK to get a &mut to the state, since
// - We checked that the thread owning the `PeripheralMutex` can't preempt us in `new`.
// Interrupts' priorities can only be changed with raw embassy `Interrupts`,
// which can't safely store a `PeripheralMutex` across invocations.
// - We can't have preempted a with() call because the irq is disabled during it.
let state = &mut *(p as *mut S);
state.on_interrupt();
});
irq.set_handler_context(state_ptr as *mut ());
irq.enable();
Self { irq, state: state_ptr }
}
/// Access the peripheral state ensuring interrupts are disabled so that the state can be
/// safely accessed.
pub fn with<R>(&mut self, f: impl FnOnce(&mut S) -> R) -> R {
self.irq.disable();
// Safety: it's OK to get a &mut to the state, since the irq is disabled.
let state = unsafe { &mut *self.state };
let r = f(state);
self.irq.enable();
r
}
/// Returns whether the wrapped interrupt is currently in a pending state.
pub fn is_pending(&self) -> bool {
self.irq.is_pending()
}
/// Forces the wrapped interrupt into a pending state.
pub fn pend(&self) {
self.irq.pend()
}
/// Forces the wrapped interrupt out of a pending state.
pub fn unpend(&self) {
self.irq.unpend()
}
/// Gets the priority of the wrapped interrupt.
pub fn priority(&self) -> Priority {
self.irq.get_priority()
}
}
impl<'a, S: PeripheralState> Drop for PeripheralMutex<'a, S> {
fn drop(&mut self) {
self.irq.disable();
self.irq.remove_handler();
// safety:
// - we initialized the state in `new`, so we know it's initialized.
// - the irq is disabled, so it won't preempt us while dropping.
unsafe { self.state.drop_in_place() }
}
}

6
embassy-lora/src/iv.rs
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@ -22,7 +22,7 @@ pub struct InterruptHandler {}
#[cfg(feature = "stm32wl")] #[cfg(feature = "stm32wl")]
impl interrupt::Handler<interrupt::SUBGHZ_RADIO> for InterruptHandler { impl interrupt::Handler<interrupt::SUBGHZ_RADIO> for InterruptHandler {
unsafe fn on_interrupt() { unsafe fn on_interrupt() {
unsafe { SUBGHZ_RADIO::steal() }.disable(); interrupt::SUBGHZ_RADIO::disable();
IRQ_SIGNAL.signal(()); IRQ_SIGNAL.signal(());
} }
} }
@ -49,7 +49,7 @@ where
rf_switch_rx: Option<CTRL>, rf_switch_rx: Option<CTRL>,
rf_switch_tx: Option<CTRL>, rf_switch_tx: Option<CTRL>,
) -> Result<Self, RadioError> { ) -> Result<Self, RadioError> {
unsafe { interrupt::SUBGHZ_RADIO::steal() }.disable(); interrupt::SUBGHZ_RADIO::disable();
Ok(Self { Ok(Self {
board_type: BoardType::Stm32wlSx1262, // updated when associated with a specific LoRa board board_type: BoardType::Stm32wlSx1262, // updated when associated with a specific LoRa board
rf_switch_rx, rf_switch_rx,
@ -95,7 +95,7 @@ where
} }
async fn await_irq(&mut self) -> Result<(), RadioError> { async fn await_irq(&mut self) -> Result<(), RadioError> {
unsafe { interrupt::SUBGHZ_RADIO::steal() }.enable(); unsafe { interrupt::SUBGHZ_RADIO::enable() };
IRQ_SIGNAL.wait().await; IRQ_SIGNAL.wait().await;
Ok(()) Ok(())
} }

11
embassy-macros/src/lib.rs
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@ -169,14 +169,3 @@ pub fn cortex_m_interrupt_declare(item: TokenStream) -> TokenStream {
let name = syn::parse_macro_input!(item as syn::Ident); let name = syn::parse_macro_input!(item as syn::Ident);
cortex_m_interrupt_declare::run(name).unwrap_or_else(|x| x).into() cortex_m_interrupt_declare::run(name).unwrap_or_else(|x| x).into()
} }
/// # interrupt_take procedural macro
///
/// core::panic! is used as a default way to panic in this macro as there is no sensible way of enabling/disabling defmt for macro generation.
/// We are aware that this brings bloat in the form of core::fmt, but the bloat is already included with e.g. array indexing panics.
/// To get rid of this bloat, use the compiler flags `-Zbuild-std=core -Zbuild-std-features=panic_immediate_abort`.
#[proc_macro]
pub fn cortex_m_interrupt_take(item: TokenStream) -> TokenStream {
let name = syn::parse_macro_input!(item as syn::Ident);
cortex_m_interrupt_take::run(name).unwrap_or_else(|x| x).into()
}

21
embassy-macros/src/macros/cortex_m_interrupt_declare.rs
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@ -3,32 +3,19 @@ use quote::{format_ident, quote};
pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> { pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> {
let name = format_ident!("{}", name); let name = format_ident!("{}", name);
let name_interrupt = format_ident!("{}", name); let doc = format!("{} interrupt.", name);
let name_handler = format!("__EMBASSY_{}_HANDLER", name);
let doc = format!("{} interrupt singleton.", name);
let result = quote! { let result = quote! {
#[doc = #doc] #[doc = #doc]
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]
pub struct #name_interrupt(()); pub enum #name{}
unsafe impl ::embassy_cortex_m::interrupt::Interrupt for #name_interrupt { unsafe impl ::embassy_cortex_m::interrupt::Interrupt for #name {
fn number(&self) -> u16 { fn number() -> u16 {
use cortex_m::interrupt::InterruptNumber; use cortex_m::interrupt::InterruptNumber;
let irq = InterruptEnum::#name; let irq = InterruptEnum::#name;
irq.number() as u16 irq.number() as u16
} }
unsafe fn steal() -> Self {
Self(())
} }
unsafe fn __handler(&self) -> &'static ::embassy_cortex_m::interrupt::DynHandler {
#[export_name = #name_handler]
static HANDLER: ::embassy_cortex_m::interrupt::DynHandler = ::embassy_cortex_m::interrupt::DynHandler::new();
&HANDLER
}
}
::embassy_hal_common::impl_peripheral!(#name_interrupt);
}; };
Ok(result) Ok(result)
} }

57
embassy-macros/src/macros/cortex_m_interrupt_take.rs
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@ -1,57 +0,0 @@
use proc_macro2::TokenStream;
use quote::{format_ident, quote};
pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> {
let name = format!("{}", name);
let name_interrupt = format_ident!("{}", name);
let name_handler = format!("__EMBASSY_{}_HANDLER", name);
#[cfg(feature = "rtos-trace-interrupt")]
let (isr_enter, isr_exit) = (
quote! {
::embassy_executor::rtos_trace_interrupt! {
::embassy_executor::_export::trace::isr_enter();
}
},
quote! {
::embassy_executor::rtos_trace_interrupt! {
::embassy_executor::_export::trace::isr_exit();
}
},
);
#[cfg(not(feature = "rtos-trace-interrupt"))]
let (isr_enter, isr_exit) = (quote! {}, quote! {});
let result = quote! {
{
#[allow(non_snake_case)]
#[export_name = #name]
pub unsafe extern "C" fn trampoline() {
extern "C" {
#[link_name = #name_handler]
static HANDLER: interrupt::DynHandler;
}
let func = HANDLER.func.load(interrupt::_export::atomic::Ordering::Relaxed);
let ctx = HANDLER.ctx.load(interrupt::_export::atomic::Ordering::Relaxed);
let func: fn(*mut ()) = ::core::mem::transmute(func);
#isr_enter
func(ctx);
#isr_exit
}
static TAKEN: interrupt::_export::atomic::AtomicBool = interrupt::_export::atomic::AtomicBool::new(false);
if TAKEN.compare_exchange(false, true, interrupt::_export::atomic::Ordering::AcqRel, interrupt::_export::atomic::Ordering::Acquire).is_err() {
core::panic!("IRQ Already taken");
}
let irq: interrupt::#name_interrupt = unsafe { ::core::mem::transmute(()) };
irq
}
};
Ok(result)
}

1
embassy-macros/src/macros/mod.rs
View File

@ -1,5 +1,4 @@
pub mod cortex_m_interrupt; pub mod cortex_m_interrupt;
pub mod cortex_m_interrupt_declare; pub mod cortex_m_interrupt_declare;
pub mod cortex_m_interrupt_take;
pub mod main; pub mod main;
pub mod task; pub mod task;

8
embassy-nrf/src/buffered_uarte.rs
View File

@ -24,7 +24,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
use crate::gpio::sealed::Pin; use crate::gpio::sealed::Pin;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self, InterruptExt}; use crate::interrupt::{self};
use crate::ppi::{ use crate::ppi::{
self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task, self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
}; };
@ -362,8 +362,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
ppi_ch2.disable(); ppi_ch2.disable();
ppi_group.add_channel(&ppi_ch2); ppi_group.add_channel(&ppi_ch2);
unsafe { U::Interrupt::steal() }.pend(); U::Interrupt::pend();
unsafe { U::Interrupt::steal() }.enable(); unsafe { U::Interrupt::enable() };
Self { Self {
_peri: peri, _peri: peri,
@ -375,7 +375,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
} }
fn pend_irq() { fn pend_irq() {
unsafe { <U::Interrupt as Interrupt>::steal() }.pend() U::Interrupt::pend()
} }
/// Adjust the baud rate to the provided value. /// Adjust the baud rate to the provided value.

50
embassy-nrf/src/gpiote.rs
View File

@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use crate::gpio::sealed::Pin as _; use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin}; use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin};
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::ppi::{Event, Task}; use crate::ppi::{Event, Task};
use crate::{interrupt, pac, peripherals}; use crate::{interrupt, pac, peripherals};
@ -74,42 +74,38 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
} }
// Enable interrupts // Enable interrupts
cfg_if::cfg_if! { #[cfg(any(feature = "nrf5340-app-s", feature = "nrf9160-s"))]
if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] { type Irq = interrupt::GPIOTE0;
let irq = unsafe { interrupt::GPIOTE0::steal() }; #[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
} else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] { type Irq = interrupt::GPIOTE1;
let irq = unsafe { interrupt::GPIOTE1::steal() }; #[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
} else { type Irq = interrupt::GPIOTE;
let irq = unsafe { interrupt::GPIOTE::steal() };
}
}
irq.unpend(); Irq::unpend();
irq.set_priority(irq_prio); Irq::set_priority(irq_prio);
irq.enable(); unsafe { Irq::enable() };
let g = regs(); let g = regs();
g.events_port.write(|w| w); g.events_port.write(|w| w);
g.intenset.write(|w| w.port().set()); g.intenset.write(|w| w.port().set());
} }
cfg_if::cfg_if! { #[cfg(any(feature = "nrf5340-app-s", feature = "nrf9160-s"))]
if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] { #[interrupt]
#[interrupt] fn GPIOTE0() {
fn GPIOTE0() {
unsafe { handle_gpiote_interrupt() }; unsafe { handle_gpiote_interrupt() };
} }
} else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
#[interrupt] #[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
fn GPIOTE1() { #[interrupt]
fn GPIOTE1() {
unsafe { handle_gpiote_interrupt() }; unsafe { handle_gpiote_interrupt() };
} }
} else {
#[interrupt] #[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
fn GPIOTE() { #[interrupt]
fn GPIOTE() {
unsafe { handle_gpiote_interrupt() }; unsafe { handle_gpiote_interrupt() };
}
}
} }
unsafe fn handle_gpiote_interrupt() { unsafe fn handle_gpiote_interrupt() {

5
embassy-nrf/src/i2s.rs
View File

@ -9,7 +9,6 @@ use core::ops::{Deref, DerefMut};
use core::sync::atomic::{compiler_fence, Ordering}; use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::InterruptExt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
@ -564,8 +563,8 @@ impl<'d, T: Instance> I2S<'d, T> {
} }
fn setup_interrupt(&self) { fn setup_interrupt(&self) {
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let device = Device::<T>::new(); let device = Device::<T>::new();
device.disable_tx_ptr_interrupt(); device.disable_tx_ptr_interrupt();

2
embassy-nrf/src/lib.rs
View File

@ -96,7 +96,7 @@ mod chip;
pub mod interrupt { pub mod interrupt {
//! Interrupt definitions and macros to bind them. //! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex}; pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
pub use crate::chip::irqs::*; pub use crate::chip::irqs::*;

6
embassy-nrf/src/pdm.rs
View File

@ -14,7 +14,7 @@ use futures::future::poll_fn;
use crate::chip::EASY_DMA_SIZE; use crate::chip::EASY_DMA_SIZE;
use crate::gpio::sealed::Pin; use crate::gpio::sealed::Pin;
use crate::gpio::{AnyPin, Pin as GpioPin}; use crate::gpio::{AnyPin, Pin as GpioPin};
use crate::interrupt::{self, InterruptExt}; use crate::interrupt::{self};
use crate::Peripheral; use crate::Peripheral;
/// Interrupt handler. /// Interrupt handler.
@ -94,8 +94,8 @@ impl<'d, T: Instance> Pdm<'d, T> {
r.gainr.write(|w| w.gainr().default_gain()); r.gainr.write(|w| w.gainr().default_gain());
// IRQ // IRQ
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
r.enable.write(|w| w.enable().set_bit()); r.enable.write(|w| w.enable().set_bit());

7
embassy-nrf/src/qdec.rs
View File

@ -6,12 +6,11 @@ use core::future::poll_fn;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use crate::gpio::sealed::Pin as _; use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Pin as GpioPin}; use crate::gpio::{AnyPin, Pin as GpioPin};
use crate::interrupt::InterruptExt; use crate::interrupt::Interrupt;
use crate::{interrupt, Peripheral}; use crate::{interrupt, Peripheral};
/// Quadrature decoder driver. /// Quadrature decoder driver.
@ -134,8 +133,8 @@ impl<'d, T: Instance> Qdec<'d, T> {
SamplePeriod::_131ms => w.sampleper()._131ms(), SamplePeriod::_131ms => w.sampleper()._131ms(),
}); });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
// Enable peripheral // Enable peripheral
r.enable.write(|w| w.enable().set_bit()); r.enable.write(|w| w.enable().set_bit());

6
embassy-nrf/src/qspi.rs
View File

@ -12,7 +12,7 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash}; use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
use crate::gpio::{self, Pin as GpioPin}; use crate::gpio::{self, Pin as GpioPin};
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
pub use crate::pac::qspi::ifconfig0::{ pub use crate::pac::qspi::ifconfig0::{
ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode, ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode,
}; };
@ -207,8 +207,8 @@ impl<'d, T: Instance> Qspi<'d, T> {
w w
}); });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
// Enable it // Enable it
r.enable.write(|w| w.enable().enabled()); r.enable.write(|w| w.enable().enabled());

7
embassy-nrf/src/rng.rs
View File

@ -8,12 +8,11 @@ use core::ptr;
use core::sync::atomic::{AtomicPtr, Ordering}; use core::sync::atomic::{AtomicPtr, Ordering};
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use crate::interrupt::InterruptExt; use crate::interrupt::Interrupt;
use crate::{interrupt, Peripheral}; use crate::{interrupt, Peripheral};
/// Interrupt handler. /// Interrupt handler.
@ -99,8 +98,8 @@ impl<'d, T: Instance> Rng<'d, T> {
this.stop(); this.stop();
this.disable_irq(); this.disable_irq();
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
this this
} }

6
embassy-nrf/src/saadc.rs
View File

@ -6,7 +6,7 @@ use core::future::poll_fn;
use core::sync::atomic::{compiler_fence, Ordering}; use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef}; use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
@ -189,8 +189,8 @@ impl<'d, const N: usize> Saadc<'d, N> {
// Disable all events interrupts // Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) }); r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) });
unsafe { interrupt::SAADC::steal() }.unpend(); interrupt::SAADC::unpend();
unsafe { interrupt::SAADC::steal() }.enable(); unsafe { interrupt::SAADC::enable() };
Self { _p: saadc } Self { _p: saadc }
} }

6
embassy-nrf/src/spim.rs
View File

@ -15,7 +15,7 @@ pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
use crate::chip::FORCE_COPY_BUFFER_SIZE; use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _; use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut}; use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{pac, Peripheral}; use crate::{pac, Peripheral};
@ -207,8 +207,8 @@ impl<'d, T: Instance> Spim<'d, T> {
// Disable all events interrupts // Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { _p: spim } Self { _p: spim }
} }

6
embassy-nrf/src/spis.rs
View File

@ -13,7 +13,7 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
use crate::chip::FORCE_COPY_BUFFER_SIZE; use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _; use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin}; use crate::gpio::{self, AnyPin, Pin as GpioPin};
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut}; use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{pac, Peripheral}; use crate::{pac, Peripheral};
@ -214,8 +214,8 @@ impl<'d, T: Instance> Spis<'d, T> {
// Disable all events interrupts. // Disable all events interrupts.
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { _p: spis } Self { _p: spis }
} }

7
embassy-nrf/src/temp.rs
View File

@ -3,13 +3,12 @@
use core::future::poll_fn; use core::future::poll_fn;
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use fixed::types::I30F2; use fixed::types::I30F2;
use crate::interrupt::InterruptExt; use crate::interrupt::Interrupt;
use crate::peripherals::TEMP; use crate::peripherals::TEMP;
use crate::{interrupt, pac, Peripheral}; use crate::{interrupt, pac, Peripheral};
@ -42,8 +41,8 @@ impl<'d> Temp<'d> {
into_ref!(_peri); into_ref!(_peri);
// Enable interrupt that signals temperature values // Enable interrupt that signals temperature values
unsafe { interrupt::TEMP::steal() }.unpend(); interrupt::TEMP::unpend();
unsafe { interrupt::TEMP::steal() }.enable(); unsafe { interrupt::TEMP::enable() };
Self { _peri } Self { _peri }
} }

7
embassy-nrf/src/time_driver.rs
View File

@ -7,7 +7,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex; use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
use embassy_time::driver::{AlarmHandle, Driver}; use embassy_time::driver::{AlarmHandle, Driver};
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::{interrupt, pac}; use crate::{interrupt, pac};
fn rtc() -> &'static pac::rtc0::RegisterBlock { fn rtc() -> &'static pac::rtc0::RegisterBlock {
@ -142,9 +142,8 @@ impl RtcDriver {
// Wait for clear // Wait for clear
while r.counter.read().bits() != 0 {} while r.counter.read().bits() != 0 {}
let irq = unsafe { interrupt::RTC1::steal() }; interrupt::RTC1::set_priority(irq_prio);
irq.set_priority(irq_prio); unsafe { interrupt::RTC1::enable() };
irq.enable();
} }
fn on_interrupt(&self) { fn on_interrupt(&self) {

6
embassy-nrf/src/twim.rs
View File

@ -16,7 +16,7 @@ use embassy_time::{Duration, Instant};
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::Pin as GpioPin; use crate::gpio::Pin as GpioPin;
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::util::{slice_in_ram, slice_in_ram_or}; use crate::util::{slice_in_ram, slice_in_ram_or};
use crate::{gpio, pac, Peripheral}; use crate::{gpio, pac, Peripheral};
@ -174,8 +174,8 @@ impl<'d, T: Instance> Twim<'d, T> {
// Disable all events interrupts // Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) }); r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { _p: twim } Self { _p: twim }
} }

6
embassy-nrf/src/twis.rs
View File

@ -15,7 +15,7 @@ use embassy_time::{Duration, Instant};
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::Pin as GpioPin; use crate::gpio::Pin as GpioPin;
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::util::slice_in_ram_or; use crate::util::slice_in_ram_or;
use crate::{gpio, pac, Peripheral}; use crate::{gpio, pac, Peripheral};
@ -204,8 +204,8 @@ impl<'d, T: Instance> Twis<'d, T> {
// Generate suspend on read event // Generate suspend on read event
r.shorts.write(|w| w.read_suspend().enabled()); r.shorts.write(|w| w.read_suspend().enabled());
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { _p: twis } Self { _p: twis }
} }

14
embassy-nrf/src/uarte.rs
View File

@ -27,7 +27,7 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE}; use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _; use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits}; use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task}; use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
use crate::timer::{Frequency, Instance as TimerInstance, Timer}; use crate::timer::{Frequency, Instance as TimerInstance, Timer};
use crate::util::slice_in_ram_or; use crate::util::slice_in_ram_or;
@ -168,8 +168,8 @@ impl<'d, T: Instance> Uarte<'d, T> {
} }
r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) }); r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let hardware_flow_control = match (rts.is_some(), cts.is_some()) { let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
(false, false) => false, (false, false) => false,
@ -358,8 +358,8 @@ impl<'d, T: Instance> UarteTx<'d, T> {
let hardware_flow_control = cts.is_some(); let hardware_flow_control = cts.is_some();
configure(r, config, hardware_flow_control); configure(r, config, hardware_flow_control);
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let s = T::state(); let s = T::state();
s.tx_rx_refcount.store(1, Ordering::Relaxed); s.tx_rx_refcount.store(1, Ordering::Relaxed);
@ -551,8 +551,8 @@ impl<'d, T: Instance> UarteRx<'d, T> {
r.psel.txd.write(|w| w.connect().disconnected()); r.psel.txd.write(|w| w.connect().disconnected());
r.psel.cts.write(|w| w.connect().disconnected()); r.psel.cts.write(|w| w.connect().disconnected());
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let hardware_flow_control = rts.is_some(); let hardware_flow_control = rts.is_some();
configure(r, config, hardware_flow_control); configure(r, config, hardware_flow_control);

6
embassy-nrf/src/usb/mod.rs
View File

@ -18,7 +18,7 @@ use embassy_usb_driver::{Direction, EndpointAddress, EndpointError, EndpointInfo
use pac::usbd::RegisterBlock; use pac::usbd::RegisterBlock;
use self::vbus_detect::VbusDetect; use self::vbus_detect::VbusDetect;
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::util::slice_in_ram; use crate::util::slice_in_ram;
use crate::{pac, Peripheral}; use crate::{pac, Peripheral};
@ -103,8 +103,8 @@ impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
) -> Self { ) -> Self {
into_ref!(usb); into_ref!(usb);
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { Self {
_p: usb, _p: usb,

6
embassy-nrf/src/usb/vbus_detect.rs
View File

@ -7,7 +7,7 @@ use core::task::Poll;
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use super::BUS_WAKER; use super::BUS_WAKER;
use crate::interrupt::{self, Interrupt, InterruptExt}; use crate::interrupt::{self, Interrupt};
use crate::pac; use crate::pac;
/// Trait for detecting USB VBUS power. /// Trait for detecting USB VBUS power.
@ -80,8 +80,8 @@ impl HardwareVbusDetect {
pub fn new(_irq: impl interrupt::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self { pub fn new(_irq: impl interrupt::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self {
let regs = unsafe { &*UsbRegPeri::ptr() }; let regs = unsafe { &*UsbRegPeri::ptr() };
unsafe { UsbRegIrq::steal() }.unpend(); UsbRegIrq::unpend();
unsafe { UsbRegIrq::steal() }.enable(); unsafe { UsbRegIrq::enable() };
regs.intenset regs.intenset
.write(|w| w.usbdetected().set().usbremoved().set().usbpwrrdy().set()); .write(|w| w.usbdetected().set().usbremoved().set().usbpwrrdy().set());

6
embassy-rp/src/adc.rs
View File

@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use embedded_hal_02::adc::{Channel, OneShot}; use embedded_hal_02::adc::{Channel, OneShot};
use crate::gpio::Pin; use crate::gpio::Pin;
use crate::interrupt::{self, InterruptExt, ADC_IRQ_FIFO}; use crate::interrupt::{self, ADC_IRQ_FIFO};
use crate::peripherals::ADC; use crate::peripherals::ADC;
use crate::{pac, peripherals, Peripheral}; use crate::{pac, peripherals, Peripheral};
static WAKER: AtomicWaker = AtomicWaker::new(); static WAKER: AtomicWaker = AtomicWaker::new();
@ -63,8 +63,8 @@ impl<'d> Adc<'d> {
// Setup IRQ // Setup IRQ
unsafe { unsafe {
ADC_IRQ_FIFO::steal().unpend(); ADC_IRQ_FIFO::unpend();
ADC_IRQ_FIFO::steal().enable(); ADC_IRQ_FIFO::enable();
}; };
Self { phantom: PhantomData } Self { phantom: PhantomData }

9
embassy-rp/src/dma.rs
View File

@ -4,7 +4,7 @@ use core::pin::Pin;
use core::sync::atomic::{compiler_fence, Ordering}; use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll}; use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef}; use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use pac::dma::vals::DataSize; use pac::dma::vals::DataSize;
@ -29,13 +29,12 @@ unsafe fn DMA_IRQ_0() {
} }
pub(crate) unsafe fn init() { pub(crate) unsafe fn init() {
let irq = interrupt::DMA_IRQ_0::steal(); interrupt::DMA_IRQ_0::disable();
irq.disable(); interrupt::DMA_IRQ_0::set_priority(interrupt::Priority::P3);
irq.set_priority(interrupt::Priority::P3);
pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF)); pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
irq.enable(); interrupt::DMA_IRQ_0::enable();
} }
pub unsafe fn read<'a, C: Channel, W: Word>( pub unsafe fn read<'a, C: Channel, W: Word>(

9
embassy-rp/src/gpio.rs
View File

@ -3,7 +3,7 @@ use core::future::Future;
use core::pin::Pin as FuturePin; use core::pin::Pin as FuturePin;
use core::task::{Context, Poll}; use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef}; use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
@ -137,10 +137,9 @@ pub enum InterruptTrigger {
} }
pub(crate) unsafe fn init() { pub(crate) unsafe fn init() {
let irq = interrupt::IO_IRQ_BANK0::steal(); interrupt::IO_IRQ_BANK0::disable();
irq.disable(); interrupt::IO_IRQ_BANK0::set_priority(interrupt::Priority::P3);
irq.set_priority(interrupt::Priority::P3); interrupt::IO_IRQ_BANK0::enable();
irq.enable();
} }
#[interrupt] #[interrupt]

12
embassy-rp/src/i2c.rs
View File

@ -2,7 +2,7 @@ use core::future;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use pac::i2c; use pac::i2c;
@ -82,14 +82,12 @@ impl<'d, T: Instance> I2c<'d, T, Async> {
let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config); let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config);
unsafe { let r = T::regs();
let i2c = T::regs();
// mask everything initially // mask everything initially
i2c.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0)); unsafe { r.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0)) }
T::Interrupt::steal().unpend(); T::Interrupt::unpend();
T::Interrupt::steal().enable(); unsafe { T::Interrupt::enable() };
}
i2c i2c
} }

2
embassy-rp/src/interrupt.rs
View File

@ -1,7 +1,7 @@
//! Interrupt definitions and macros to bind them. //! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex}; pub use cortex_m::interrupt::{CriticalSection, Mutex};
use embassy_cortex_m::interrupt::_export::declare; use embassy_cortex_m::interrupt::_export::declare;
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
use crate::pac::Interrupt as InterruptEnum; use crate::pac::Interrupt as InterruptEnum;
declare!(TIMER_IRQ_0); declare!(TIMER_IRQ_0);

5
embassy-rp/src/multicore.rs
View File

@ -50,7 +50,7 @@
use core::mem::ManuallyDrop; use core::mem::ManuallyDrop;
use core::sync::atomic::{compiler_fence, AtomicBool, Ordering}; use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::peripherals::CORE1; use crate::peripherals::CORE1;
use crate::{gpio, interrupt, pac}; use crate::{gpio, interrupt, pac};
@ -156,8 +156,7 @@ where
IS_CORE1_INIT.store(true, Ordering::Release); IS_CORE1_INIT.store(true, Ordering::Release);
// Enable fifo interrupt on CORE1 for `pause` functionality. // Enable fifo interrupt on CORE1 for `pause` functionality.
let irq = unsafe { interrupt::SIO_IRQ_PROC1::steal() }; unsafe { interrupt::SIO_IRQ_PROC1::enable() };
irq.enable();
entry() entry()
} }

16
embassy-rp/src/pio.rs
View File

@ -5,7 +5,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll}; use core::task::{Context, Poll};
use atomic_polyfill::{AtomicU32, AtomicU8}; use atomic_polyfill::{AtomicU32, AtomicU8};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef}; use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use fixed::types::extra::U8; use fixed::types::extra::U8;
@ -110,17 +110,15 @@ unsafe fn PIO1_IRQ_0() {
} }
pub(crate) unsafe fn init() { pub(crate) unsafe fn init() {
let irq = interrupt::PIO0_IRQ_0::steal(); interrupt::PIO0_IRQ_0::disable();
irq.disable(); interrupt::PIO0_IRQ_0::set_priority(interrupt::Priority::P3);
irq.set_priority(interrupt::Priority::P3);
pac::PIO0.irqs(0).inte().write(|m| m.0 = 0); pac::PIO0.irqs(0).inte().write(|m| m.0 = 0);
irq.enable(); interrupt::PIO0_IRQ_0::enable();
let irq = interrupt::PIO1_IRQ_0::steal(); interrupt::PIO1_IRQ_0::disable();
irq.disable(); interrupt::PIO1_IRQ_0::set_priority(interrupt::Priority::P3);
irq.set_priority(interrupt::Priority::P3);
pac::PIO1.irqs(0).inte().write(|m| m.0 = 0); pac::PIO1.irqs(0).inte().write(|m| m.0 = 0);
irq.enable(); interrupt::PIO1_IRQ_0::enable();
} }
/// Future that waits for TX-FIFO to become writable /// Future that waits for TX-FIFO to become writable

10
embassy-rp/src/timer.rs
View File

@ -6,7 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex; use embassy_sync::blocking_mutex::Mutex;
use embassy_time::driver::{AlarmHandle, Driver}; use embassy_time::driver::{AlarmHandle, Driver};
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::{interrupt, pac}; use crate::{interrupt, pac};
struct AlarmState { struct AlarmState {
@ -145,10 +145,10 @@ pub unsafe fn init() {
w.set_alarm(2, true); w.set_alarm(2, true);
w.set_alarm(3, true); w.set_alarm(3, true);
}); });
interrupt::TIMER_IRQ_0::steal().enable(); interrupt::TIMER_IRQ_0::enable();
interrupt::TIMER_IRQ_1::steal().enable(); interrupt::TIMER_IRQ_1::enable();
interrupt::TIMER_IRQ_2::steal().enable(); interrupt::TIMER_IRQ_2::enable();
interrupt::TIMER_IRQ_3::steal().enable(); interrupt::TIMER_IRQ_3::enable();
} }
#[interrupt] #[interrupt]

14
embassy-rp/src/uart/buffered.rs
View File

@ -3,7 +3,7 @@ use core::slice;
use core::task::Poll; use core::task::Poll;
use atomic_polyfill::{AtomicU8, Ordering}; use atomic_polyfill::{AtomicU8, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::atomic_ring_buffer::RingBuffer; use embassy_hal_common::atomic_ring_buffer::RingBuffer;
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use embassy_time::{Duration, Timer}; use embassy_time::{Duration, Timer};
@ -80,8 +80,8 @@ pub(crate) fn init_buffers<'d, T: Instance + 'd>(
w.set_txim(true); w.set_txim(true);
}); });
T::Interrupt::steal().unpend(); T::Interrupt::unpend();
T::Interrupt::steal().enable(); T::Interrupt::enable();
}; };
} }
@ -362,7 +362,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
// FIFO and the number of bytes drops below a threshold. When the // FIFO and the number of bytes drops below a threshold. When the
// FIFO was empty we have to manually pend the interrupt to shovel // FIFO was empty we have to manually pend the interrupt to shovel
// TX data from the buffer into the FIFO. // TX data from the buffer into the FIFO.
unsafe { T::Interrupt::steal() }.pend(); T::Interrupt::pend();
Poll::Ready(Ok(n)) Poll::Ready(Ok(n))
}) })
} }
@ -398,7 +398,7 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
// FIFO and the number of bytes drops below a threshold. When the // FIFO and the number of bytes drops below a threshold. When the
// FIFO was empty we have to manually pend the interrupt to shovel // FIFO was empty we have to manually pend the interrupt to shovel
// TX data from the buffer into the FIFO. // TX data from the buffer into the FIFO.
unsafe { T::Interrupt::steal() }.pend(); T::Interrupt::pend();
return Ok(n); return Ok(n);
} }
} }
@ -460,7 +460,7 @@ impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
// TX is inactive if the the buffer is not available. // TX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler // We can now unregister the interrupt handler
if state.tx_buf.len() == 0 { if state.tx_buf.len() == 0 {
T::Interrupt::steal().disable(); T::Interrupt::disable();
} }
} }
} }
@ -475,7 +475,7 @@ impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
// RX is inactive if the the buffer is not available. // RX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler // We can now unregister the interrupt handler
if state.rx_buf.len() == 0 { if state.rx_buf.len() == 0 {
T::Interrupt::steal().disable(); T::Interrupt::disable();
} }
} }
} }

12
embassy-rp/src/uart/mod.rs
View File

@ -3,7 +3,7 @@ use core::marker::PhantomData;
use core::task::Poll; use core::task::Poll;
use atomic_polyfill::{AtomicU16, Ordering}; use atomic_polyfill::{AtomicU16, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_futures::select::{select, Either}; use embassy_futures::select::{select, Either};
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
@ -245,12 +245,10 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
fn new_inner(has_irq: bool, rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self { fn new_inner(has_irq: bool, rx_dma: Option<PeripheralRef<'d, AnyChannel>>) -> Self {
debug_assert_eq!(has_irq, rx_dma.is_some()); debug_assert_eq!(has_irq, rx_dma.is_some());
if has_irq { if has_irq {
unsafe {
// disable all error interrupts initially // disable all error interrupts initially
T::regs().uartimsc().write(|w| w.0 = 0); unsafe { T::regs().uartimsc().write(|w| w.0 = 0) }
T::Interrupt::steal().unpend(); T::Interrupt::unpend();
T::Interrupt::steal().enable(); unsafe { T::Interrupt::enable() };
}
} }
Self { Self {
rx_dma, rx_dma,
@ -295,7 +293,7 @@ impl<'d, T: Instance, M: Mode> Drop for UartRx<'d, T, M> {
fn drop(&mut self) { fn drop(&mut self) {
if let Some(_) = self.rx_dma { if let Some(_) = self.rx_dma {
unsafe { unsafe {
T::Interrupt::steal().disable(); T::Interrupt::disable();
// clear dma flags. irq handlers use these to disambiguate among themselves. // clear dma flags. irq handlers use these to disambiguate among themselves.
T::regs().uartdmacr().write_clear(|reg| { T::regs().uartdmacr().write_clear(|reg| {
reg.set_rxdmae(true); reg.set_rxdmae(true);

8
embassy-rp/src/usb.rs
View File

@ -11,7 +11,7 @@ use embassy_usb_driver::{
Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
}; };
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::{pac, peripherals, Peripheral, RegExt}; use crate::{pac, peripherals, Peripheral, RegExt};
pub(crate) mod sealed { pub(crate) mod sealed {
@ -106,10 +106,8 @@ pub struct Driver<'d, T: Instance> {
impl<'d, T: Instance> Driver<'d, T> { impl<'d, T: Instance> Driver<'d, T> {
pub fn new(_usb: impl Peripheral<P = T> + 'd, _irq: impl Binding<T::Interrupt, InterruptHandler<T>>) -> Self { pub fn new(_usb: impl Peripheral<P = T> + 'd, _irq: impl Binding<T::Interrupt, InterruptHandler<T>>) -> Self {
unsafe { T::Interrupt::unpend();
T::Interrupt::steal().unpend(); unsafe { T::Interrupt::enable() };
T::Interrupt::steal().enable();
}
let regs = T::regs(); let regs = T::regs();
unsafe { unsafe {

6
embassy-stm32/src/dcmi.rs
View File

@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use crate::dma::Transfer; use crate::dma::Transfer;
use crate::gpio::sealed::AFType; use crate::gpio::sealed::AFType;
use crate::gpio::Speed; use crate::gpio::Speed;
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::{interrupt, Peripheral}; use crate::{interrupt, Peripheral};
/// Interrupt handler. /// Interrupt handler.
@ -346,8 +346,8 @@ where
}); });
} }
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { inner: peri, dma } Self { inner: peri, dma }
} }

7
embassy-stm32/src/dma/bdma.rs
View File

@ -14,7 +14,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
use super::word::{Word, WordSize}; use super::word::{Word, WordSize};
use super::Dir; use super::Dir;
use crate::_generated::BDMA_CHANNEL_COUNT; use crate::_generated::BDMA_CHANNEL_COUNT;
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::pac; use crate::pac;
use crate::pac::bdma::{regs, vals}; use crate::pac::bdma::{regs, vals};
@ -70,9 +70,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) { pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! { foreach_interrupt! {
($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => { ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
let irq = crate::interrupt::$irq::steal(); crate::interrupt::$irq::set_priority(irq_priority);
irq.set_priority(irq_priority); crate::interrupt::$irq::enable();
irq.enable();
}; };
} }
crate::_generated::init_bdma(); crate::_generated::init_bdma();

7
embassy-stm32/src/dma/dma.rs
View File

@ -13,7 +13,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
use super::word::{Word, WordSize}; use super::word::{Word, WordSize};
use super::Dir; use super::Dir;
use crate::_generated::DMA_CHANNEL_COUNT; use crate::_generated::DMA_CHANNEL_COUNT;
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::pac::dma::{regs, vals}; use crate::pac::dma::{regs, vals};
use crate::{interrupt, pac}; use crate::{interrupt, pac};
@ -149,9 +149,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) { pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! { foreach_interrupt! {
($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => { ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
let irq = interrupt::$irq::steal(); interrupt::$irq::set_priority(irq_priority);
irq.set_priority(irq_priority); interrupt::$irq::enable();
irq.enable();
}; };
} }
crate::_generated::init_dma(); crate::_generated::init_dma();

7
embassy-stm32/src/dma/gpdma.rs
View File

@ -12,7 +12,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use super::word::{Word, WordSize}; use super::word::{Word, WordSize};
use super::Dir; use super::Dir;
use crate::_generated::GPDMA_CHANNEL_COUNT; use crate::_generated::GPDMA_CHANNEL_COUNT;
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::pac; use crate::pac;
use crate::pac::gpdma::vals; use crate::pac::gpdma::vals;
@ -56,9 +56,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) { pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! { foreach_interrupt! {
($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => { ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
let irq = crate::interrupt::$irq::steal(); crate::interrupt::$irq::set_priority(irq_priority);
irq.set_priority(irq_priority); crate::interrupt::$irq::enable();
irq.enable();
}; };
} }
crate::_generated::init_gpdma(); crate::_generated::init_gpdma();

6
embassy-stm32/src/eth/v1/mod.rs
View File

@ -5,7 +5,7 @@ mod tx_desc;
use core::sync::atomic::{fence, Ordering}; use core::sync::atomic::{fence, Ordering};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf}; use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
@ -267,8 +267,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
P::phy_reset(&mut this); P::phy_reset(&mut this);
P::phy_init(&mut this); P::phy_init(&mut this);
interrupt::ETH::steal().unpend(); interrupt::ETH::unpend();
interrupt::ETH::steal().enable(); interrupt::ETH::enable();
this this
} }

6
embassy-stm32/src/eth/v2/mod.rs
View File

@ -2,7 +2,7 @@ mod descriptors;
use core::sync::atomic::{fence, Ordering}; use core::sync::atomic::{fence, Ordering};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing}; pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
@ -238,8 +238,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
P::phy_reset(&mut this); P::phy_reset(&mut this);
P::phy_init(&mut this); P::phy_init(&mut this);
interrupt::ETH::steal().unpend(); interrupt::ETH::unpend();
interrupt::ETH::steal().enable(); interrupt::ETH::enable();
this this
} }

4
embassy-stm32/src/exti.rs
View File

@ -354,13 +354,13 @@ impl_exti!(EXTI15, 15);
macro_rules! enable_irq { macro_rules! enable_irq {
($e:ident) => { ($e:ident) => {
crate::interrupt::$e::steal().enable(); crate::interrupt::$e::enable();
}; };
} }
/// safety: must be called only once /// safety: must be called only once
pub(crate) unsafe fn init() { pub(crate) unsafe fn init() {
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
foreach_exti_irq!(enable_irq); foreach_exti_irq!(enable_irq);

7
embassy-stm32/src/flash/asynch.rs
View File

@ -1,7 +1,7 @@
use core::marker::PhantomData; use core::marker::PhantomData;
use atomic_polyfill::{fence, Ordering}; use atomic_polyfill::{fence, Ordering};
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::into_ref; use embassy_hal_common::into_ref;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
@ -23,9 +23,8 @@ impl<'d> Flash<'d, Async> {
) -> Self { ) -> Self {
into_ref!(p); into_ref!(p);
let flash_irq = unsafe { crate::interrupt::FLASH::steal() }; crate::interrupt::FLASH::unpend();
flash_irq.unpend(); unsafe { crate::interrupt::FLASH::enable() };
flash_irq.enable();
Self { Self {
inner: p, inner: p,

6
embassy-stm32/src/i2c/v2.rs
View File

@ -3,7 +3,7 @@ use core::future::poll_fn;
use core::marker::PhantomData; use core::marker::PhantomData;
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_embedded_hal::SetConfig; use embassy_embedded_hal::SetConfig;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
@ -133,8 +133,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}); });
} }
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { Self {
_peri: peri, _peri: peri,

2
embassy-stm32/src/lib.rs
View File

@ -75,7 +75,7 @@ pub(crate) mod _generated {
pub mod interrupt { pub mod interrupt {
//! Interrupt definitions and macros to bind them. //! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex}; pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, InterruptExt, Priority}; pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
pub use crate::_generated::interrupt::*; pub use crate::_generated::interrupt::*;

8
embassy-stm32/src/sdmmc/mod.rs
View File

@ -14,7 +14,7 @@ use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID,
use crate::dma::NoDma; use crate::dma::NoDma;
use crate::gpio::sealed::{AFType, Pin}; use crate::gpio::sealed::{AFType, Pin};
use crate::gpio::{AnyPin, Pull, Speed}; use crate::gpio::{AnyPin, Pull, Speed};
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::pac::sdmmc::Sdmmc as RegBlock; use crate::pac::sdmmc::Sdmmc as RegBlock;
use crate::rcc::RccPeripheral; use crate::rcc::RccPeripheral;
use crate::time::Hertz; use crate::time::Hertz;
@ -447,8 +447,8 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
T::enable(); T::enable();
T::reset(); T::reset();
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let regs = T::regs(); let regs = T::regs();
unsafe { unsafe {
@ -1288,7 +1288,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> { impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> {
fn drop(&mut self) { fn drop(&mut self) {
unsafe { T::Interrupt::steal() }.disable(); T::Interrupt::disable();
unsafe { Self::on_drop() }; unsafe { Self::on_drop() };
critical_section::with(|_| unsafe { critical_section::with(|_| unsafe {

7
embassy-stm32/src/time_driver.rs
View File

@ -11,7 +11,7 @@ use embassy_time::driver::{AlarmHandle, Driver};
use embassy_time::TICK_HZ; use embassy_time::TICK_HZ;
use stm32_metapac::timer::regs; use stm32_metapac::timer::regs;
use crate::interrupt::InterruptExt; use crate::interrupt::Interrupt;
use crate::pac::timer::vals; use crate::pac::timer::vals;
use crate::rcc::sealed::RccPeripheral; use crate::rcc::sealed::RccPeripheral;
use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance}; use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};
@ -177,9 +177,8 @@ impl RtcDriver {
w.set_ccie(0, true); w.set_ccie(0, true);
}); });
let irq: <T as BasicInstance>::Interrupt = core::mem::transmute(()); <T as BasicInstance>::Interrupt::unpend();
irq.unpend(); <T as BasicInstance>::Interrupt::enable();
irq.enable();
r.cr1().modify(|w| w.set_cen(true)); r.cr1().modify(|w| w.set_cen(true));
}) })

10
embassy-stm32/src/tl_mbox/mod.rs
View File

@ -2,7 +2,7 @@ use core::mem::MaybeUninit;
use atomic_polyfill::{compiler_fence, Ordering}; use atomic_polyfill::{compiler_fence, Ordering};
use bit_field::BitField; use bit_field::BitField;
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef}; use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex; use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::channel::Channel; use embassy_sync::channel::Channel;
@ -379,11 +379,11 @@ impl<'d> TlMbox<'d> {
MemoryManager::enable(); MemoryManager::enable();
// enable interrupts // enable interrupts
unsafe { crate::interrupt::IPCC_C1_RX::steal() }.unpend(); crate::interrupt::IPCC_C1_RX::unpend();
unsafe { crate::interrupt::IPCC_C1_TX::steal() }.unpend(); crate::interrupt::IPCC_C1_TX::unpend();
unsafe { crate::interrupt::IPCC_C1_RX::steal() }.enable(); unsafe { crate::interrupt::IPCC_C1_RX::enable() };
unsafe { crate::interrupt::IPCC_C1_TX::steal() }.enable(); unsafe { crate::interrupt::IPCC_C1_TX::enable() };
Self { _ipcc: ipcc } Self { _ipcc: ipcc }
} }

18
embassy-stm32/src/usart/buffered.rs
View File

@ -216,8 +216,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
}); });
} }
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
Self { Self {
rx: BufferedUartRx { phantom: PhantomData }, rx: BufferedUartRx { phantom: PhantomData },
@ -245,7 +245,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
rx_reader.pop_done(len); rx_reader.pop_done(len);
if do_pend { if do_pend {
unsafe { T::Interrupt::steal().pend() }; T::Interrupt::pend();
} }
return Poll::Ready(Ok(len)); return Poll::Ready(Ok(len));
@ -271,7 +271,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
rx_reader.pop_done(len); rx_reader.pop_done(len);
if do_pend { if do_pend {
unsafe { T::Interrupt::steal().pend() }; T::Interrupt::pend();
} }
return Ok(len); return Ok(len);
@ -301,7 +301,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
let full = state.rx_buf.is_full(); let full = state.rx_buf.is_full();
rx_reader.pop_done(amt); rx_reader.pop_done(amt);
if full { if full {
unsafe { T::Interrupt::steal().pend() }; T::Interrupt::pend();
} }
} }
} }
@ -324,7 +324,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
tx_writer.push_done(n); tx_writer.push_done(n);
if empty { if empty {
unsafe { T::Interrupt::steal() }.pend(); T::Interrupt::pend();
} }
Poll::Ready(Ok(n)) Poll::Ready(Ok(n))
@ -358,7 +358,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
tx_writer.push_done(n); tx_writer.push_done(n);
if empty { if empty {
unsafe { T::Interrupt::steal() }.pend(); T::Interrupt::pend();
} }
return Ok(n); return Ok(n);
@ -385,7 +385,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartRx<'d, T> {
// TX is inactive if the the buffer is not available. // TX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler // We can now unregister the interrupt handler
if state.tx_buf.len() == 0 { if state.tx_buf.len() == 0 {
T::Interrupt::steal().disable(); T::Interrupt::disable();
} }
} }
} }
@ -400,7 +400,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartTx<'d, T> {
// RX is inactive if the the buffer is not available. // RX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler // We can now unregister the interrupt handler
if state.rx_buf.len() == 0 { if state.rx_buf.len() == 0 {
T::Interrupt::steal().disable(); T::Interrupt::disable();
} }
} }
} }

10
embassy-stm32/src/usart/mod.rs
View File

@ -5,7 +5,7 @@ use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering}; use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll; use core::task::Poll;
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt}; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop; use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef}; use embassy_hal_common::{into_ref, PeripheralRef};
use futures::future::{select, Either}; use futures::future::{select, Either};
@ -331,8 +331,8 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
configure(r, &config, T::frequency(), T::KIND, true, false); configure(r, &config, T::frequency(), T::KIND, true, false);
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
// create state once! // create state once!
let _s = T::state(); let _s = T::state();
@ -732,8 +732,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
configure(r, &config, T::frequency(), T::KIND, true, true); configure(r, &config, T::frequency(), T::KIND, true, true);
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
// create state once! // create state once!
let _s = T::state(); let _s = T::state();

6
embassy-stm32/src/usb/usb.rs
View File

@ -14,7 +14,7 @@ use embassy_usb_driver::{
use super::{DmPin, DpPin, Instance}; use super::{DmPin, DpPin, Instance};
use crate::gpio::sealed::AFType; use crate::gpio::sealed::AFType;
use crate::interrupt::{Interrupt, InterruptExt}; use crate::interrupt::Interrupt;
use crate::pac::usb::regs; use crate::pac::usb::regs;
use crate::pac::usb::vals::{EpType, Stat}; use crate::pac::usb::vals::{EpType, Stat};
use crate::pac::USBRAM; use crate::pac::USBRAM;
@ -260,8 +260,8 @@ impl<'d, T: Instance> Driver<'d, T> {
dm: impl Peripheral<P = impl DmPin<T>> + 'd, dm: impl Peripheral<P = impl DmPin<T>> + 'd,
) -> Self { ) -> Self {
into_ref!(dp, dm); into_ref!(dp, dm);
unsafe { T::Interrupt::steal() }.unpend(); T::Interrupt::unpend();
unsafe { T::Interrupt::steal() }.enable(); unsafe { T::Interrupt::enable() };
let regs = T::regs(); let regs = T::regs();

8
embassy-stm32/src/usb_otg/usb.rs
View File

@ -3,7 +3,7 @@ use core::marker::PhantomData;
use core::task::Poll; use core::task::Poll;
use atomic_polyfill::{AtomicBool, AtomicU16, Ordering}; use atomic_polyfill::{AtomicBool, AtomicU16, Ordering};
use embassy_cortex_m::interrupt::InterruptExt; use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral}; use embassy_hal_common::{into_ref, Peripheral};
use embassy_sync::waitqueue::AtomicWaker; use embassy_sync::waitqueue::AtomicWaker;
use embassy_usb_driver::{ use embassy_usb_driver::{
@ -629,7 +629,7 @@ impl<'d, T: Instance> Bus<'d, T> {
} }
fn disable(&mut self) { fn disable(&mut self) {
unsafe { T::Interrupt::steal() }.disable(); T::Interrupt::disable();
<T as RccPeripheral>::disable(); <T as RccPeripheral>::disable();
@ -902,8 +902,8 @@ impl<'d, T: Instance> embassy_usb_driver::Bus for Bus<'d, T> {
<T as RccPeripheral>::enable(); <T as RccPeripheral>::enable();
<T as RccPeripheral>::reset(); <T as RccPeripheral>::reset();
T::Interrupt::steal().unpend(); T::Interrupt::unpend();
T::Interrupt::steal().enable(); T::Interrupt::enable();
let r = T::regs(); let r = T::regs();
let core_id = r.cid().read().0; let core_id = r.cid().read().0;

1
examples/boot/bootloader/rp/Cargo.toml
View File

@ -30,3 +30,4 @@ debug = ["defmt-rtt", "defmt"]
[profile.release] [profile.release]
debug = true debug = true
opt-level = 's'

2
examples/std/src/bin/tcp_accept.rs
View File

@ -108,7 +108,7 @@ async fn main_task(spawner: Spawner) {
info!("Closing the connection"); info!("Closing the connection");
socket.abort(); socket.abort();
info!("Flushing the RST out..."); info!("Flushing the RST out...");
socket.flush().await; _ = socket.flush().await;
info!("Finished with the socket"); info!("Finished with the socket");
} }
} }