Merge branch 'main' of https://github.com/embassy-rs/embassy into hrtim

embassy-stm32/src/rcc/h5.rs

@@ -473,11 +473,11 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
             w.set_divm(0);
         });
 
-        return PllOutput{
+        return PllOutput {
             p: None,
             q: None,
             r: None,
-        }
+        };
     };
 
     assert!(1 <= config.prediv && config.prediv <= 63);

embassy-stm32/src/rcc/h7.rs

@@ -740,7 +740,7 @@ mod pll {
             }
         };
 
-        let vco_ck = output + pll_x_p;
+        let vco_ck = output * pll_x_p;
 
         assert!(pll_x_p < 128);
         assert!(vco_ck >= VCO_MIN);

embassy-stm32/src/rcc/l4.rs

@@ -1,6 +1,7 @@
 use core::marker::PhantomData;
 
 use embassy_hal_common::into_ref;
+use stm32_metapac::rcc::regs::Cfgr;
 use stm32_metapac::rcc::vals::{Lsedrv, Mcopre, Mcosel};
 
 use crate::gpio::sealed::AFType;
@@ -439,6 +440,26 @@ impl<'d, T: McoInstance> Mco<'d, T> {
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    // Switch to MSI to prevent problems with PLL configuration.
+    if !RCC.cr().read().msion() {
+        // Turn on MSI and configure it to 4MHz.
+        RCC.cr().modify(|w| {
+            w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
+            w.set_msirange(MSIRange::default().into());
+            w.set_msipllen(false);
+            w.set_msion(true)
+        });
+
+        // Wait until MSI is running
+        while !RCC.cr().read().msirdy() {}
+    }
+    if RCC.cfgr().read().sws() != Sw::MSI {
+        // Set MSI as a clock source, reset prescalers.
+        RCC.cfgr().write_value(Cfgr::default());
+        // Wait for clock switch status bits to change.
+        while RCC.cfgr().read().sws() != Sw::MSI {}
+    }
+
     match config.rtc_mux {
         RtcClockSource::LSE32 => {
             // 1. Unlock the backup domain
@@ -660,6 +681,8 @@ pub(crate) unsafe fn init(config: Config) {
         }
     };
 
+    RCC.apb1enr1().modify(|w| w.set_pwren(true));
+
     set_freqs(Clocks {
         sys: Hertz(sys_clk),
         ahb1: Hertz(ahb_freq),

embassy-stm32/src/rcc/mod.rs

@@ -83,12 +83,12 @@ static mut CLOCK_FREQS: MaybeUninit<Clocks> = MaybeUninit::uninit();
 /// Safety: Sets a mutable global.
 pub(crate) unsafe fn set_freqs(freqs: Clocks) {
     debug!("rcc: {:?}", freqs);
-    CLOCK_FREQS.as_mut_ptr().write(freqs);
+    CLOCK_FREQS = MaybeUninit::new(freqs);
 }
 
 /// Safety: Reads a mutable global.
 pub(crate) unsafe fn get_freqs() -> &'static Clocks {
-    &*CLOCK_FREQS.as_ptr()
+    CLOCK_FREQS.assume_init_ref()
 }
 
 #[cfg(feature = "unstable-pac")]

embassy-stm32/src/rcc/wl.rs

@@ -1,4 +1,5 @@
-use crate::pac::{FLASH, RCC};
+use crate::pac::pwr::vals::Dbp;
+use crate::pac::{FLASH, PWR, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
@@ -184,6 +185,8 @@ pub struct Config {
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
     pub enable_lsi: bool,
+    pub enable_rtc_apb: bool,
+    pub rtc_mux: RtcClockSource,
 }
 
 impl Default for Config {
@@ -196,10 +199,25 @@ impl Default for Config {
             apb1_pre: APBPrescaler::NotDivided,
             apb2_pre: APBPrescaler::NotDivided,
             enable_lsi: false,
+            enable_rtc_apb: false,
+            rtc_mux: RtcClockSource::LSI32,
         }
     }
 }
 
+pub enum RtcClockSource {
+    LSE32,
+    LSI32,
+}
+
+#[repr(u8)]
+pub enum Lsedrv {
+    Low = 0,
+    MediumLow = 1,
+    MediumHigh = 2,
+    High = 3,
+}
+
 pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw, vos) = match config.mux {
         ClockSrc::HSI16 => (HSI_FREQ.0, 0x01, VoltageScale::Range2),
@@ -266,6 +284,32 @@ pub(crate) unsafe fn init(config: Config) {
 
     while FLASH.acr().read().latency() != ws {}
 
+    match config.rtc_mux {
+        RtcClockSource::LSE32 => {
+            // 1. Unlock the backup domain
+            PWR.cr1().modify(|w| w.set_dbp(Dbp::ENABLED));
+
+            // 2. Setup the LSE
+            RCC.bdcr().modify(|w| {
+                // Enable LSE
+                w.set_lseon(true);
+                // Max drive strength
+                // TODO: should probably be settable
+                w.set_lsedrv(Lsedrv::High as u8); //---// PAM - should not be commented
+            });
+
+            // Wait until LSE is running
+            while !RCC.bdcr().read().lserdy() {}
+        }
+        RtcClockSource::LSI32 => {
+            // Turn on the internal 32 kHz LSI oscillator
+            RCC.csr().modify(|w| w.set_lsion(true));
+
+            // Wait until LSI is running
+            while !RCC.csr().read().lsirdy() {}
+        }
+    }
+
     match config.mux {
         ClockSrc::HSI16 => {
             // Enable HSI16
@@ -287,11 +331,26 @@ pub(crate) unsafe fn init(config: Config) {
                 w.set_msirgsel(true);
                 w.set_msirange(range.into());
                 w.set_msion(true);
+
+                if let RtcClockSource::LSE32 = config.rtc_mux {
+                    // If LSE is enabled, enable calibration of MSI
+                    w.set_msipllen(true);
+                } else {
+                    w.set_msipllen(false);
+                }
             });
             while !RCC.cr().read().msirdy() {}
         }
     }
 
+    if config.enable_rtc_apb {
+        // enable peripheral clock for communication
+        crate::pac::RCC.apb1enr1().modify(|w| w.set_rtcapben(true));
+
+        // read to allow the pwr clock to enable
+        crate::pac::PWR.cr1().read();
+    }
+
     RCC.extcfgr().modify(|w| {
         if config.shd_ahb_pre == AHBPrescaler::NotDivided {
             w.set_shdhpre(0);