Move USB to embassy-extras
This commit is contained in:
Thales Fragoso
@ -32,7 +32,6 @@ stm32f479 = ["stm32f4xx-hal/stm32f469", "embassy-stm32/stm32f479"]
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[dependencies]
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embassy = { version = "0.1.0", path = "../embassy" }
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embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32" }
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embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
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defmt = { version = "0.2.0", optional = true }
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log = { version = "0.4.11", optional = true }
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@ -43,4 +42,3 @@ embedded-dma = { version = "0.1.2" }
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stm32f4xx-hal = { version = "0.8.3", features = ["rt", "can"], git = "https://github.com/stm32-rs/stm32f4xx-hal.git"}
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bxcan = "0.5.0"
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nb = "*"
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usb-device = "0.2.7"
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@ -1,338 +0,0 @@
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// Copied from https://github.com/mvirkkunen/usbd-serial
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#![allow(dead_code)]
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use core::convert::TryInto;
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use core::mem;
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use usb_device::class_prelude::*;
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use usb_device::Result;
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/// This should be used as `device_class` when building the `UsbDevice`.
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pub const USB_CLASS_CDC: u8 = 0x02;
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const USB_CLASS_CDC_DATA: u8 = 0x0a;
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const CDC_SUBCLASS_ACM: u8 = 0x02;
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const CDC_PROTOCOL_NONE: u8 = 0x00;
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const CS_INTERFACE: u8 = 0x24;
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const CDC_TYPE_HEADER: u8 = 0x00;
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const CDC_TYPE_CALL_MANAGEMENT: u8 = 0x01;
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const CDC_TYPE_ACM: u8 = 0x02;
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const CDC_TYPE_UNION: u8 = 0x06;
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const REQ_SEND_ENCAPSULATED_COMMAND: u8 = 0x00;
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#[allow(unused)]
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const REQ_GET_ENCAPSULATED_COMMAND: u8 = 0x01;
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const REQ_SET_LINE_CODING: u8 = 0x20;
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const REQ_GET_LINE_CODING: u8 = 0x21;
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const REQ_SET_CONTROL_LINE_STATE: u8 = 0x22;
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/// Packet level implementation of a CDC-ACM serial port.
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///
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/// This class can be used directly and it has the least overhead due to directly reading and
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/// writing USB packets with no intermediate buffers, but it will not act like a stream-like serial
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/// port. The following constraints must be followed if you use this class directly:
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///
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/// - `read_packet` must be called with a buffer large enough to hold max_packet_size bytes, and the
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/// method will return a `WouldBlock` error if there is no packet to be read.
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/// - `write_packet` must not be called with a buffer larger than max_packet_size bytes, and the
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/// method will return a `WouldBlock` error if the previous packet has not been sent yet.
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/// - If you write a packet that is exactly max_packet_size bytes long, it won't be processed by the
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/// host operating system until a subsequent shorter packet is sent. A zero-length packet (ZLP)
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/// can be sent if there is no other data to send. This is because USB bulk transactions must be
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/// terminated with a short packet, even if the bulk endpoint is used for stream-like data.
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pub struct CdcAcmClass<'a, B: UsbBus> {
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comm_if: InterfaceNumber,
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comm_ep: EndpointIn<'a, B>,
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data_if: InterfaceNumber,
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read_ep: EndpointOut<'a, B>,
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write_ep: EndpointIn<'a, B>,
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line_coding: LineCoding,
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dtr: bool,
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rts: bool,
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}
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impl<B: UsbBus> CdcAcmClass<'_, B> {
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/// Creates a new CdcAcmClass with the provided UsbBus and max_packet_size in bytes. For
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/// full-speed devices, max_packet_size has to be one of 8, 16, 32 or 64.
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pub fn new(alloc: &UsbBusAllocator<B>, max_packet_size: u16) -> CdcAcmClass<'_, B> {
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CdcAcmClass {
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comm_if: alloc.interface(),
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comm_ep: alloc.interrupt(8, 255),
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data_if: alloc.interface(),
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read_ep: alloc.bulk(max_packet_size),
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write_ep: alloc.bulk(max_packet_size),
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line_coding: LineCoding {
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stop_bits: StopBits::One,
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data_bits: 8,
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parity_type: ParityType::None,
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data_rate: 8_000,
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},
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dtr: false,
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rts: false,
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}
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}
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/// Gets the maximum packet size in bytes.
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pub fn max_packet_size(&self) -> u16 {
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// The size is the same for both endpoints.
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self.read_ep.max_packet_size()
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}
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/// Gets the current line coding. The line coding contains information that's mainly relevant
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/// for USB to UART serial port emulators, and can be ignored if not relevant.
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pub fn line_coding(&self) -> &LineCoding {
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&self.line_coding
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}
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/// Gets the DTR (data terminal ready) state
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pub fn dtr(&self) -> bool {
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self.dtr
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}
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/// Gets the RTS (request to send) state
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pub fn rts(&self) -> bool {
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self.rts
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}
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/// Writes a single packet into the IN endpoint.
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pub fn write_packet(&mut self, data: &[u8]) -> Result<usize> {
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self.write_ep.write(data)
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}
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/// Reads a single packet from the OUT endpoint.
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pub fn read_packet(&mut self, data: &mut [u8]) -> Result<usize> {
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self.read_ep.read(data)
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}
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/// Gets the address of the IN endpoint.
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pub fn write_ep_address(&self) -> EndpointAddress {
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self.write_ep.address()
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}
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/// Gets the address of the OUT endpoint.
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pub fn read_ep_address(&self) -> EndpointAddress {
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self.read_ep.address()
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}
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}
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impl<B: UsbBus> UsbClass<B> for CdcAcmClass<'_, B> {
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fn get_configuration_descriptors(&self, writer: &mut DescriptorWriter) -> Result<()> {
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writer.iad(
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self.comm_if,
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2,
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USB_CLASS_CDC,
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CDC_SUBCLASS_ACM,
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CDC_PROTOCOL_NONE,
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)?;
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writer.interface(
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self.comm_if,
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USB_CLASS_CDC,
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CDC_SUBCLASS_ACM,
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CDC_PROTOCOL_NONE,
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)?;
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writer.write(
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CS_INTERFACE,
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&[
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CDC_TYPE_HEADER, // bDescriptorSubtype
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0x10,
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0x01, // bcdCDC (1.10)
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],
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)?;
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writer.write(
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CS_INTERFACE,
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&[
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CDC_TYPE_ACM, // bDescriptorSubtype
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0x00, // bmCapabilities
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],
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)?;
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writer.write(
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CS_INTERFACE,
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&[
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CDC_TYPE_UNION, // bDescriptorSubtype
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self.comm_if.into(), // bControlInterface
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self.data_if.into(), // bSubordinateInterface
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],
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)?;
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writer.write(
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CS_INTERFACE,
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&[
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CDC_TYPE_CALL_MANAGEMENT, // bDescriptorSubtype
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0x00, // bmCapabilities
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self.data_if.into(), // bDataInterface
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],
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)?;
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writer.endpoint(&self.comm_ep)?;
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writer.interface(self.data_if, USB_CLASS_CDC_DATA, 0x00, 0x00)?;
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writer.endpoint(&self.write_ep)?;
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writer.endpoint(&self.read_ep)?;
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Ok(())
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}
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fn reset(&mut self) {
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self.line_coding = LineCoding::default();
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self.dtr = false;
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self.rts = false;
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}
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fn control_in(&mut self, xfer: ControlIn<B>) {
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let req = xfer.request();
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if !(req.request_type == control::RequestType::Class
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&& req.recipient == control::Recipient::Interface
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&& req.index == u8::from(self.comm_if) as u16)
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{
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return;
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}
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match req.request {
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// REQ_GET_ENCAPSULATED_COMMAND is not really supported - it will be rejected below.
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REQ_GET_LINE_CODING if req.length == 7 => {
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xfer.accept(|data| {
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data[0..4].copy_from_slice(&self.line_coding.data_rate.to_le_bytes());
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data[4] = self.line_coding.stop_bits as u8;
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data[5] = self.line_coding.parity_type as u8;
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data[6] = self.line_coding.data_bits;
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Ok(7)
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})
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.ok();
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}
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_ => {
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xfer.reject().ok();
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}
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}
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}
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fn control_out(&mut self, xfer: ControlOut<B>) {
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let req = xfer.request();
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if !(req.request_type == control::RequestType::Class
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&& req.recipient == control::Recipient::Interface
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&& req.index == u8::from(self.comm_if) as u16)
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{
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return;
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}
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match req.request {
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REQ_SEND_ENCAPSULATED_COMMAND => {
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// We don't actually support encapsulated commands but pretend we do for standards
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// compatibility.
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xfer.accept().ok();
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}
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REQ_SET_LINE_CODING if xfer.data().len() >= 7 => {
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self.line_coding.data_rate =
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u32::from_le_bytes(xfer.data()[0..4].try_into().unwrap());
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self.line_coding.stop_bits = xfer.data()[4].into();
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self.line_coding.parity_type = xfer.data()[5].into();
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self.line_coding.data_bits = xfer.data()[6];
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xfer.accept().ok();
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}
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REQ_SET_CONTROL_LINE_STATE => {
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self.dtr = (req.value & 0x0001) != 0;
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self.rts = (req.value & 0x0002) != 0;
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xfer.accept().ok();
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}
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_ => {
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xfer.reject().ok();
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}
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};
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}
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}
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/// Number of stop bits for LineCoding
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#[derive(Copy, Clone, PartialEq, Eq)]
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pub enum StopBits {
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/// 1 stop bit
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One = 0,
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/// 1.5 stop bits
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OnePointFive = 1,
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/// 2 stop bits
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Two = 2,
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}
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impl From<u8> for StopBits {
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fn from(value: u8) -> Self {
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if value <= 2 {
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unsafe { mem::transmute(value) }
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} else {
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StopBits::One
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}
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}
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}
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/// Parity for LineCoding
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#[derive(Copy, Clone, PartialEq, Eq)]
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pub enum ParityType {
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None = 0,
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Odd = 1,
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Event = 2,
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Mark = 3,
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Space = 4,
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}
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impl From<u8> for ParityType {
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fn from(value: u8) -> Self {
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if value <= 4 {
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unsafe { mem::transmute(value) }
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} else {
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ParityType::None
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}
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}
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}
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/// Line coding parameters
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///
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/// This is provided by the host for specifying the standard UART parameters such as baud rate. Can
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/// be ignored if you don't plan to interface with a physical UART.
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pub struct LineCoding {
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stop_bits: StopBits,
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data_bits: u8,
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parity_type: ParityType,
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data_rate: u32,
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}
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impl LineCoding {
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/// Gets the number of stop bits for UART communication.
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pub fn stop_bits(&self) -> StopBits {
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self.stop_bits
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}
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/// Gets the number of data bits for UART communication.
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pub fn data_bits(&self) -> u8 {
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self.data_bits
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}
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/// Gets the parity type for UART communication.
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pub fn parity_type(&self) -> ParityType {
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self.parity_type
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}
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/// Gets the data rate in bits per second for UART communication.
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pub fn data_rate(&self) -> u32 {
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self.data_rate
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}
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}
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impl Default for LineCoding {
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fn default() -> Self {
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LineCoding {
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stop_bits: StopBits::One,
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data_bits: 8,
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parity_type: ParityType::None,
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data_rate: 8_000,
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}
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}
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}
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@ -316,9 +316,3 @@ pub mod exti;
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pub mod qei;
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pub mod rtc;
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pub mod serial;
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pub mod usb;
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pub mod usb_serial;
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pub(crate) mod cdc_acm;
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pub use cortex_m_rt::interrupt;
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@ -1,238 +0,0 @@
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use core::cell::RefCell;
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use core::marker::PhantomData;
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use core::pin::Pin;
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use usb_device::bus::UsbBus;
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use usb_device::class::UsbClass;
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use usb_device::device::UsbDevice;
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use crate::interrupt;
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use crate::usb_serial::{ReadInterface, UsbSerial, WriteInterface};
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use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
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pub struct State<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B>,
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{
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device: UsbDevice<'bus, B>,
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pub(crate) classes: T,
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}
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pub struct Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B>,
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{
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// Don't you dare moving out `PeripheralMutex`
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inner: RefCell<PeripheralMutex<State<'bus, B, T>>>,
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}
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impl<'bus, B, T> Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B>,
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{
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pub fn new<S: IntoClassSet<B, T>>(
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device: UsbDevice<'bus, B>,
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class_set: S,
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irq: interrupt::OTG_FS,
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) -> Self {
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let state = State {
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device,
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classes: class_set.into_class_set(),
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};
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let mutex = PeripheralMutex::new(state, irq);
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Self {
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inner: RefCell::new(mutex),
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}
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}
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pub fn start(self: Pin<&mut Self>) {
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let this = unsafe { self.get_unchecked_mut() };
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let mut mutex = this.inner.borrow_mut();
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let mutex = unsafe { Pin::new_unchecked(&mut *mutex) };
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// Use inner to register the irq
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mutex.register_interrupt();
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}
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}
|
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impl<'bus, 'c, B, T> Usb<'bus, B, T>
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where
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B: UsbBus,
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T: ClassSet<B> + SerialState<'bus, 'c, B, Index0>,
|
||||
{
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pub fn take_serial_0<'a>(
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self: Pin<&'a Self>,
|
||||
) -> (
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ReadInterface<'a, 'bus, 'c, Index0, B, T>,
|
||||
WriteInterface<'a, 'bus, 'c, Index0, B, T>,
|
||||
) {
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let this = self.get_ref();
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|
||||
let r = ReadInterface {
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||||
inner: &this.inner,
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||||
_buf_lifetime: PhantomData,
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||||
_index: PhantomData,
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||||
};
|
||||
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let w = WriteInterface {
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||||
inner: &this.inner,
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||||
_buf_lifetime: PhantomData,
|
||||
_index: PhantomData,
|
||||
};
|
||||
(r, w)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'bus, 'c, B, T> Usb<'bus, B, T>
|
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where
|
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B: UsbBus,
|
||||
T: ClassSet<B> + SerialState<'bus, 'c, B, Index1>,
|
||||
{
|
||||
pub fn take_serial_1<'a>(
|
||||
self: Pin<&'a Self>,
|
||||
) -> (
|
||||
ReadInterface<'a, 'bus, 'c, Index1, B, T>,
|
||||
WriteInterface<'a, 'bus, 'c, Index1, B, T>,
|
||||
) {
|
||||
let this = self.get_ref();
|
||||
|
||||
let r = ReadInterface {
|
||||
inner: &this.inner,
|
||||
_buf_lifetime: PhantomData,
|
||||
_index: PhantomData,
|
||||
};
|
||||
|
||||
let w = WriteInterface {
|
||||
inner: &this.inner,
|
||||
_buf_lifetime: PhantomData,
|
||||
_index: PhantomData,
|
||||
};
|
||||
(r, w)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'bus, B, T> PeripheralState for State<'bus, B, T>
|
||||
where
|
||||
B: UsbBus,
|
||||
T: ClassSet<B>,
|
||||
{
|
||||
type Interrupt = interrupt::OTG_FS;
|
||||
fn on_interrupt(&mut self) {
|
||||
self.classes.poll_all(&mut self.device);
|
||||
}
|
||||
}
|
||||
|
||||
pub trait ClassSet<B: UsbBus> {
|
||||
fn poll_all(&mut self, device: &mut UsbDevice<'_, B>) -> bool;
|
||||
}
|
||||
|
||||
pub trait IntoClassSet<B: UsbBus, C: ClassSet<B>> {
|
||||
fn into_class_set(self) -> C;
|
||||
}
|
||||
|
||||
pub struct ClassSet1<B, C1>
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
{
|
||||
class: C1,
|
||||
_bus: PhantomData<B>,
|
||||
}
|
||||
|
||||
pub struct ClassSet2<B, C1, C2>
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
C2: UsbClass<B>,
|
||||
{
|
||||
class1: C1,
|
||||
class2: C2,
|
||||
_bus: PhantomData<B>,
|
||||
}
|
||||
|
||||
pub struct Index0;
|
||||
pub struct Index1;
|
||||
|
||||
impl<B, C1> ClassSet<B> for ClassSet1<B, C1>
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
{
|
||||
fn poll_all(&mut self, device: &mut UsbDevice<'_, B>) -> bool {
|
||||
device.poll(&mut [&mut self.class])
|
||||
}
|
||||
}
|
||||
|
||||
impl<B, C1, C2> ClassSet<B> for ClassSet2<B, C1, C2>
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
C2: UsbClass<B>,
|
||||
{
|
||||
fn poll_all(&mut self, device: &mut UsbDevice<'_, B>) -> bool {
|
||||
device.poll(&mut [&mut self.class1, &mut self.class2])
|
||||
}
|
||||
}
|
||||
|
||||
impl<B, C1> IntoClassSet<B, ClassSet1<B, C1>> for C1
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
{
|
||||
fn into_class_set(self) -> ClassSet1<B, C1> {
|
||||
ClassSet1 {
|
||||
class: self,
|
||||
_bus: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<B, C1, C2> IntoClassSet<B, ClassSet2<B, C1, C2>> for (C1, C2)
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
C2: UsbClass<B>,
|
||||
{
|
||||
fn into_class_set(self) -> ClassSet2<B, C1, C2> {
|
||||
ClassSet2 {
|
||||
class1: self.0,
|
||||
class2: self.1,
|
||||
_bus: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait SerialState<'bus, 'a, B: UsbBus, I> {
|
||||
fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B>;
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B: UsbBus> SerialState<'bus, 'a, B, Index0>
|
||||
for ClassSet1<B, UsbSerial<'bus, 'a, B>>
|
||||
{
|
||||
fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
|
||||
&mut self.class
|
||||
}
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B, C2> SerialState<'bus, 'a, B, Index0> for ClassSet2<B, UsbSerial<'bus, 'a, B>, C2>
|
||||
where
|
||||
B: UsbBus,
|
||||
C2: UsbClass<B>,
|
||||
{
|
||||
fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
|
||||
&mut self.class1
|
||||
}
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B, C1> SerialState<'bus, 'a, B, Index1> for ClassSet2<B, C1, UsbSerial<'bus, 'a, B>>
|
||||
where
|
||||
B: UsbBus,
|
||||
C1: UsbClass<B>,
|
||||
{
|
||||
fn get_serial(&mut self) -> &mut UsbSerial<'bus, 'a, B> {
|
||||
&mut self.class2
|
||||
}
|
||||
}
|
||||
@ -1,304 +0,0 @@
|
||||
use core::cell::RefCell;
|
||||
use core::marker::{PhantomData, Unpin};
|
||||
use core::pin::Pin;
|
||||
use core::task::{Context, Poll};
|
||||
|
||||
use embassy::io::{self, AsyncBufRead, AsyncWrite};
|
||||
use embassy::util::WakerRegistration;
|
||||
use usb_device::bus::UsbBus;
|
||||
use usb_device::class_prelude::*;
|
||||
use usb_device::UsbError;
|
||||
|
||||
use crate::cdc_acm::CdcAcmClass;
|
||||
use crate::usb::{ClassSet, SerialState, State};
|
||||
use embassy_extras::peripheral::PeripheralMutex;
|
||||
use embassy_extras::ring_buffer::RingBuffer;
|
||||
|
||||
pub struct ReadInterface<'a, 'bus, 'c, I, B, T>
|
||||
where
|
||||
I: Unpin,
|
||||
B: UsbBus,
|
||||
T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
|
||||
{
|
||||
// Don't you dare moving out `PeripheralMutex`
|
||||
pub(crate) inner: &'a RefCell<PeripheralMutex<State<'bus, B, T>>>,
|
||||
pub(crate) _buf_lifetime: PhantomData<&'c T>,
|
||||
pub(crate) _index: PhantomData<I>,
|
||||
}
|
||||
|
||||
/// Write interface for USB CDC_ACM
|
||||
///
|
||||
/// This interface is buffered, meaning that after the write returns the bytes might not be fully
|
||||
/// on the wire just yet
|
||||
pub struct WriteInterface<'a, 'bus, 'c, I, B, T>
|
||||
where
|
||||
I: Unpin,
|
||||
B: UsbBus,
|
||||
T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
|
||||
{
|
||||
// Don't you dare moving out `PeripheralMutex`
|
||||
pub(crate) inner: &'a RefCell<PeripheralMutex<State<'bus, B, T>>>,
|
||||
pub(crate) _buf_lifetime: PhantomData<&'c T>,
|
||||
pub(crate) _index: PhantomData<I>,
|
||||
}
|
||||
|
||||
impl<'a, 'bus, 'c, I, B, T> AsyncBufRead for ReadInterface<'a, 'bus, 'c, I, B, T>
|
||||
where
|
||||
I: Unpin,
|
||||
B: UsbBus,
|
||||
T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
|
||||
{
|
||||
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<io::Result<&[u8]>> {
|
||||
let this = self.get_mut();
|
||||
let mut mutex = this.inner.borrow_mut();
|
||||
let mutex = unsafe { Pin::new_unchecked(&mut *mutex) };
|
||||
mutex.with(|state, _irq| {
|
||||
let serial = state.classes.get_serial();
|
||||
let serial = Pin::new(serial);
|
||||
|
||||
match serial.poll_fill_buf(cx) {
|
||||
Poll::Ready(Ok(buf)) => {
|
||||
let buf: &[u8] = buf;
|
||||
let buf: &[u8] = unsafe { core::mem::transmute(buf) };
|
||||
Poll::Ready(Ok(buf))
|
||||
}
|
||||
Poll::Ready(Err(_)) => Poll::Ready(Err(io::Error::Other)),
|
||||
Poll::Pending => Poll::Pending,
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
fn consume(self: Pin<&mut Self>, amt: usize) {
|
||||
let this = self.get_mut();
|
||||
let mut mutex = this.inner.borrow_mut();
|
||||
let mutex = unsafe { Pin::new_unchecked(&mut *mutex) };
|
||||
mutex.with(|state, _irq| {
|
||||
let serial = state.classes.get_serial();
|
||||
let serial = Pin::new(serial);
|
||||
|
||||
serial.consume(amt);
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, 'bus, 'c, I, B, T> AsyncWrite for WriteInterface<'a, 'bus, 'c, I, B, T>
|
||||
where
|
||||
I: Unpin,
|
||||
B: UsbBus,
|
||||
T: SerialState<'bus, 'c, B, I> + ClassSet<B>,
|
||||
{
|
||||
fn poll_write(
|
||||
self: Pin<&mut Self>,
|
||||
cx: &mut Context<'_>,
|
||||
buf: &[u8],
|
||||
) -> Poll<io::Result<usize>> {
|
||||
let this = self.get_mut();
|
||||
let mut mutex = this.inner.borrow_mut();
|
||||
let mutex = unsafe { Pin::new_unchecked(&mut *mutex) };
|
||||
mutex.with(|state, _irq| {
|
||||
let serial = state.classes.get_serial();
|
||||
let serial = Pin::new(serial);
|
||||
|
||||
serial.poll_write(cx, buf)
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
pub struct UsbSerial<'bus, 'a, B: UsbBus> {
|
||||
inner: CdcAcmClass<'bus, B>,
|
||||
read_buf: RingBuffer<'a>,
|
||||
write_buf: RingBuffer<'a>,
|
||||
read_waker: WakerRegistration,
|
||||
write_waker: WakerRegistration,
|
||||
write_state: WriteState,
|
||||
read_error: bool,
|
||||
write_error: bool,
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B: UsbBus> AsyncBufRead for UsbSerial<'bus, 'a, B> {
|
||||
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<io::Result<&[u8]>> {
|
||||
let this = self.get_mut();
|
||||
|
||||
if this.read_error {
|
||||
this.read_error = false;
|
||||
return Poll::Ready(Err(io::Error::Other));
|
||||
}
|
||||
|
||||
let buf = this.read_buf.pop_buf();
|
||||
if buf.is_empty() {
|
||||
this.read_waker.register(cx.waker());
|
||||
return Poll::Pending;
|
||||
}
|
||||
Poll::Ready(Ok(buf))
|
||||
}
|
||||
|
||||
fn consume(self: Pin<&mut Self>, amt: usize) {
|
||||
self.get_mut().read_buf.pop(amt);
|
||||
}
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B: UsbBus> AsyncWrite for UsbSerial<'bus, 'a, B> {
|
||||
fn poll_write(
|
||||
self: Pin<&mut Self>,
|
||||
cx: &mut Context<'_>,
|
||||
buf: &[u8],
|
||||
) -> Poll<io::Result<usize>> {
|
||||
let this = self.get_mut();
|
||||
|
||||
if this.write_error {
|
||||
this.write_error = false;
|
||||
return Poll::Ready(Err(io::Error::Other));
|
||||
}
|
||||
|
||||
let write_buf = this.write_buf.push_buf();
|
||||
if write_buf.is_empty() {
|
||||
this.write_waker.register(cx.waker());
|
||||
return Poll::Pending;
|
||||
}
|
||||
|
||||
let count = write_buf.len().min(buf.len());
|
||||
write_buf[..count].copy_from_slice(&buf[..count]);
|
||||
this.write_buf.push(count);
|
||||
|
||||
this.flush_write();
|
||||
Poll::Ready(Ok(count))
|
||||
}
|
||||
}
|
||||
|
||||
/// Keeps track of the type of the last written packet.
|
||||
enum WriteState {
|
||||
/// No packets in-flight
|
||||
Idle,
|
||||
|
||||
/// Short packet currently in-flight
|
||||
Short,
|
||||
|
||||
/// Full packet current in-flight. A full packet must be followed by a short packet for the host
|
||||
/// OS to see the transaction. The data is the number of subsequent full packets sent so far. A
|
||||
/// short packet is forced every SHORT_PACKET_INTERVAL packets so that the OS sees data in a
|
||||
/// timely manner.
|
||||
Full(usize),
|
||||
}
|
||||
|
||||
impl<'bus, 'a, B: UsbBus> UsbSerial<'bus, 'a, B> {
|
||||
pub fn new(
|
||||
alloc: &'bus UsbBusAllocator<B>,
|
||||
read_buf: &'a mut [u8],
|
||||
write_buf: &'a mut [u8],
|
||||
) -> Self {
|
||||
Self {
|
||||
inner: CdcAcmClass::new(alloc, 64),
|
||||
read_buf: RingBuffer::new(read_buf),
|
||||
write_buf: RingBuffer::new(write_buf),
|
||||
read_waker: WakerRegistration::new(),
|
||||
write_waker: WakerRegistration::new(),
|
||||
write_state: WriteState::Idle,
|
||||
read_error: false,
|
||||
write_error: false,
|
||||
}
|
||||
}
|
||||
|
||||
fn flush_write(&mut self) {
|
||||
/// If this many full size packets have been sent in a row, a short packet will be sent so that the
|
||||
/// host sees the data in a timely manner.
|
||||
const SHORT_PACKET_INTERVAL: usize = 10;
|
||||
|
||||
let full_size_packets = match self.write_state {
|
||||
WriteState::Full(c) => c,
|
||||
_ => 0,
|
||||
};
|
||||
|
||||
let ep_size = self.inner.max_packet_size() as usize;
|
||||
let max_size = if full_size_packets > SHORT_PACKET_INTERVAL {
|
||||
ep_size - 1
|
||||
} else {
|
||||
ep_size
|
||||
};
|
||||
|
||||
let buf = {
|
||||
let buf = self.write_buf.pop_buf();
|
||||
if buf.len() > max_size {
|
||||
&buf[..max_size]
|
||||
} else {
|
||||
buf
|
||||
}
|
||||
};
|
||||
|
||||
if !buf.is_empty() {
|
||||
let count = match self.inner.write_packet(buf) {
|
||||
Ok(c) => c,
|
||||
Err(UsbError::WouldBlock) => 0,
|
||||
Err(_) => {
|
||||
self.write_error = true;
|
||||
return;
|
||||
}
|
||||
};
|
||||
|
||||
if buf.len() == ep_size {
|
||||
self.write_state = WriteState::Full(full_size_packets + 1);
|
||||
} else {
|
||||
self.write_state = WriteState::Short;
|
||||
}
|
||||
self.write_buf.pop(count);
|
||||
} else if full_size_packets > 0 {
|
||||
if let Err(e) = self.inner.write_packet(&[]) {
|
||||
if !matches!(e, UsbError::WouldBlock) {
|
||||
self.write_error = true;
|
||||
}
|
||||
return;
|
||||
}
|
||||
self.write_state = WriteState::Idle;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<B> UsbClass<B> for UsbSerial<'_, '_, B>
|
||||
where
|
||||
B: UsbBus,
|
||||
{
|
||||
fn get_configuration_descriptors(&self, writer: &mut DescriptorWriter) -> Result<(), UsbError> {
|
||||
self.inner.get_configuration_descriptors(writer)
|
||||
}
|
||||
|
||||
fn reset(&mut self) {
|
||||
self.inner.reset();
|
||||
self.read_buf.clear();
|
||||
self.write_buf.clear();
|
||||
self.write_state = WriteState::Idle;
|
||||
}
|
||||
|
||||
fn endpoint_in_complete(&mut self, addr: EndpointAddress) {
|
||||
if addr == self.inner.write_ep_address() {
|
||||
self.write_waker.wake();
|
||||
|
||||
self.flush_write();
|
||||
}
|
||||
}
|
||||
|
||||
fn endpoint_out(&mut self, addr: EndpointAddress) {
|
||||
if addr == self.inner.read_ep_address() {
|
||||
let buf = self.read_buf.push_buf();
|
||||
let count = match self.inner.read_packet(buf) {
|
||||
Ok(c) => c,
|
||||
Err(UsbError::WouldBlock) => 0,
|
||||
Err(_) => {
|
||||
self.read_error = true;
|
||||
return;
|
||||
}
|
||||
};
|
||||
|
||||
if count > 0 {
|
||||
self.read_buf.push(count);
|
||||
self.read_waker.wake();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn control_in(&mut self, xfer: ControlIn<B>) {
|
||||
self.inner.control_in(xfer);
|
||||
}
|
||||
|
||||
fn control_out(&mut self, xfer: ControlOut<B>) {
|
||||
self.inner.control_out(xfer);
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user