Lift thread-context feature restrictions
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parent
bce250bbdc
commit
d5e66f6f87
@ -1,9 +1,6 @@
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#[cfg(feature = "executor-interrupt")]
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compile_error!("`executor-interrupt` is not supported with `arch-riscv32`.");
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#[cfg(feature = "thread-context")]
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compile_error!("`thread-context` is not supported with `arch-riscv32`.");
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#[cfg(feature = "executor-thread")]
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pub use thread::*;
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#[cfg(feature = "executor-thread")]
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@ -30,6 +27,13 @@ mod thread {
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pub struct RiscVThreadContext;
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impl ThreadContext for RiscVThreadContext {
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#[cfg(feature = "thread-context")]
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fn context(&self) -> OpaqueThreadContext {
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// Enabling thread-context is not incorrect, just wasteful.
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OpaqueThreadContext(0)
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}
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#[cfg(not(feature = "thread-context"))]
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fn context(&self) -> OpaqueThreadContext {
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OpaqueThreadContext(())
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}
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@ -1,12 +1,6 @@
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#[cfg(feature = "executor-interrupt")]
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compile_error!("`executor-interrupt` is not supported with `arch-xtensa`.");
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#[cfg(feature = "thread-context")]
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compile_error!(
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"`thread-context` is not supported with `arch-xtensa`.\
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Use a multicore-safe executor from esp-hal instead." // obviously, this is too specific to ESP32
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);
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#[cfg(feature = "executor-thread")]
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pub use thread::*;
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#[cfg(feature = "executor-thread")]
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@ -17,7 +11,7 @@ mod thread {
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use crate::raw::OpaqueThreadContext;
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use crate::thread::ThreadContext;
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/// global atomic used to keep track of whether there is work to do since sev() is not available on RISCV
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/// global atomic used to keep track of whether there is work to do since sev() is not available on Xtensa
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static SIGNAL_WORK_THREAD_MODE: AtomicBool = AtomicBool::new(false);
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#[export_name = "__thread_mode_pender"]
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@ -31,6 +25,13 @@ mod thread {
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pub struct XtensaThreadContext;
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impl ThreadContext for XtensaThreadContext {
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#[cfg(feature = "thread-context")]
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fn context(&self) -> OpaqueThreadContext {
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// Enabling thread-context is not incorrect, just wasteful.
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OpaqueThreadContext(0)
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}
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#[cfg(not(feature = "thread-context"))]
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fn context(&self) -> OpaqueThreadContext {
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OpaqueThreadContext(())
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}
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@ -43,8 +44,8 @@ mod thread {
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let token: critical_section::RawRestoreState;
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core::arch::asm!("rsil {0}, 5", out(reg) token);
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// we do not care about race conditions between the load and store operations, interrupts
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// will only set this value to true.
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// we do not care about race conditions between the load and store operations,
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// interrupts will only set this value to true.
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// if there is work to do, loop back to polling
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if SIGNAL_WORK_THREAD_MODE.load(Ordering::SeqCst) {
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SIGNAL_WORK_THREAD_MODE.store(false, Ordering::SeqCst);
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