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Merge remote-tracking branch 'upstream/master' into u32-partition

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This commit is contained in:
Rasmus Melchior Jacobsen 2023-04-11 07:36:23 +02:00
commit d8c92c53d6
93 changed files with 3701 additions and 1266 deletions
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5
ci.sh
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@ -49,6 +49,7 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32f411ce,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32f413vh,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32f429zi,log,exti,time-driver-any,unstable-traits,embedded-sdmmc \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32f730i8,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32h755zi-cm7,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32h7b3ai,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features nightly,stm32l476vg,defmt,exti,time-driver-any,unstable-traits \
@ -65,6 +66,8 @@ cargo batch \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f107vc,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f103re,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32f100c4,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32h503rb,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features nightly,stm32h562ag,defmt,exti,time-driver-any,unstable-traits \
--- build --release --manifest-path embassy-boot/nrf/Cargo.toml --target thumbv7em-none-eabi --features embassy-nrf/nrf52840 \
--- build --release --manifest-path embassy-boot/nrf/Cargo.toml --target thumbv8m.main-none-eabihf --features embassy-nrf/nrf9160-ns \
--- build --release --manifest-path embassy-boot/rp/Cargo.toml --target thumbv6m-none-eabi \
@ -86,6 +89,7 @@ cargo batch \
--- build --release --manifest-path examples/stm32c0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32c0 \
--- build --release --manifest-path examples/stm32g0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32g0 \
--- build --release --manifest-path examples/stm32g4/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32g4 \
--- build --release --manifest-path examples/stm32h5/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h5 \
--- build --release --manifest-path examples/stm32h7/Cargo.toml --target thumbv7em-none-eabi --out-dir out/examples/stm32h7 \
--- build --release --manifest-path examples/stm32l0/Cargo.toml --target thumbv6m-none-eabi --out-dir out/examples/stm32l0 \
--- build --release --manifest-path examples/stm32l1/Cargo.toml --target thumbv7m-none-eabi --out-dir out/examples/stm32l1 \
@ -115,6 +119,7 @@ cargo batch \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32g071rb --out-dir out/tests/nucleo-stm32g071rb \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi --out-dir out/tests/nucleo-stm32h755zi \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32wb55rg --out-dir out/tests/nucleo-stm32wb55rg \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h563zi --out-dir out/tests/nucleo-stm32h563zi \
--- build --release --manifest-path tests/stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32u585ai --out-dir out/tests/iot-stm32u585ai \
--- build --release --manifest-path tests/rp/Cargo.toml --target thumbv6m-none-eabi --out-dir out/tests/rpi-pico \
--- build --release --manifest-path tests/nrf/Cargo.toml --target thumbv7em-none-eabi --out-dir out/tests/nrf52840-dk \

2
embassy-boot/boot/Cargo.toml
View File

@ -24,6 +24,7 @@ features = ["defmt"]
[dependencies]
defmt = { version = "0.3", optional = true }
digest = "0.10"
log = { version = "0.4", optional = true }
ed25519-dalek = { version = "1.0.1", default_features = false, features = ["u32_backend"], optional = true }
embassy-sync = { version = "0.1.0", path = "../../embassy-sync" }
@ -37,6 +38,7 @@ log = "0.4"
env_logger = "0.9"
rand = "0.7" # ed25519-dalek v1.0.1 depends on this exact version
futures = { version = "0.3", features = ["executor"] }
sha1 = "0.10.5"
[dev-dependencies.ed25519-dalek]
default_features = false

30
embassy-boot/boot/src/digest_adapters/ed25519_dalek.rs Normal file
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@ -0,0 +1,30 @@
use digest::typenum::U64;
use digest::{FixedOutput, HashMarker, OutputSizeUser, Update};
use ed25519_dalek::Digest as _;
pub struct Sha512(ed25519_dalek::Sha512);
impl Default for Sha512 {
fn default() -> Self {
Self(ed25519_dalek::Sha512::new())
}
}
impl Update for Sha512 {
fn update(&mut self, data: &[u8]) {
self.0.update(data)
}
}
impl FixedOutput for Sha512 {
fn finalize_into(self, out: &mut digest::Output<Self>) {
let result = self.0.finalize();
out.as_mut_slice().copy_from_slice(result.as_slice())
}
}
impl OutputSizeUser for Sha512 {
type OutputSize = U64;
}
impl HashMarker for Sha512 {}

5
embassy-boot/boot/src/digest_adapters/mod.rs Normal file
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@ -0,0 +1,5 @@
#[cfg(feature = "ed25519-dalek")]
pub(crate) mod ed25519_dalek;
#[cfg(feature = "ed25519-salty")]
pub(crate) mod salty;

29
embassy-boot/boot/src/digest_adapters/salty.rs Normal file
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@ -0,0 +1,29 @@
use digest::typenum::U64;
use digest::{FixedOutput, HashMarker, OutputSizeUser, Update};
pub struct Sha512(salty::Sha512);
impl Default for Sha512 {
fn default() -> Self {
Self(salty::Sha512::new())
}
}
impl Update for Sha512 {
fn update(&mut self, data: &[u8]) {
self.0.update(data)
}
}
impl FixedOutput for Sha512 {
fn finalize_into(self, out: &mut digest::Output<Self>) {
let result = self.0.finalize();
out.as_mut_slice().copy_from_slice(result.as_slice())
}
}
impl OutputSizeUser for Sha512 {
type OutputSize = U64;
}
impl HashMarker for Sha512 {}

128
embassy-boot/boot/src/firmware_updater.rs
View File

@ -1,3 +1,4 @@
use digest::Digest;
use embedded_storage::nor_flash::{NorFlash, NorFlashError, NorFlashErrorKind};
use embedded_storage_async::nor_flash::NorFlash as AsyncNorFlash;
@ -121,28 +122,27 @@ impl FirmwareUpdater {
#[cfg(feature = "ed25519-dalek")]
{
use ed25519_dalek::{Digest, PublicKey, Sha512, Signature, SignatureError, Verifier};
use ed25519_dalek::{PublicKey, Signature, SignatureError, Verifier};
use crate::digest_adapters::ed25519_dalek::Sha512;
let into_signature_error = |e: SignatureError| FirmwareUpdaterError::Signature(e.into());
let public_key = PublicKey::from_bytes(_public_key).map_err(into_signature_error)?;
let signature = Signature::from_bytes(_signature).map_err(into_signature_error)?;
let mut digest = Sha512::new();
for offset in (0.._update_len).step_by(_aligned.len()) {
self.dfu.read(_state_and_dfu_flash, offset as u32, _aligned).await?;
let len = core::cmp::min(_update_len - offset, _aligned.len());
digest.update(&_aligned[..len]);
}
let mut message = [0; 64];
self.hash::<_, Sha512>(_state_and_dfu_flash, _update_len, _aligned, &mut message)
.await?;
public_key
.verify(&digest.finalize(), &signature)
.map_err(into_signature_error)?
public_key.verify(&message, &signature).map_err(into_signature_error)?
}
#[cfg(feature = "ed25519-salty")]
{
use salty::constants::{PUBLICKEY_SERIALIZED_LENGTH, SIGNATURE_SERIALIZED_LENGTH};
use salty::{PublicKey, Sha512, Signature};
use salty::{PublicKey, Signature};
use crate::digest_adapters::salty::Sha512;
fn into_signature_error<E>(_: E) -> FirmwareUpdaterError {
FirmwareUpdaterError::Signature(signature::Error::default())
@ -153,14 +153,10 @@ impl FirmwareUpdater {
let signature: [u8; SIGNATURE_SERIALIZED_LENGTH] = _signature.try_into().map_err(into_signature_error)?;
let signature = Signature::try_from(&signature).map_err(into_signature_error)?;
let mut digest = Sha512::new();
for offset in (0.._update_len).step_by(_aligned.len()) {
self.dfu.read(_state_and_dfu_flash, offset as u32, _aligned).await?;
let len = core::cmp::min(_update_len - offset, _aligned.len());
digest.update(&_aligned[..len]);
}
let mut message = [0; 64];
self.hash::<_, Sha512>(_state_and_dfu_flash, _update_len, _aligned, &mut message)
.await?;
let message = digest.finalize();
let r = public_key.verify(&message, &signature);
trace!(
"Verifying with public key {}, signature {} and message {} yields ok: {}",
@ -175,6 +171,25 @@ impl FirmwareUpdater {
self.set_magic(_aligned, SWAP_MAGIC, _state_and_dfu_flash).await
}
/// Verify the update in DFU with any digest.
pub async fn hash<F: AsyncNorFlash, D: Digest>(
&mut self,
dfu_flash: &mut F,
update_len: usize,
chunk_buf: &mut [u8],
output: &mut [u8],
) -> Result<(), FirmwareUpdaterError> {
let update_len = update_len as u32;
let mut digest = D::new();
for offset in (0..update_len).step_by(chunk_buf.len()) {
self.dfu.read(dfu_flash, offset, chunk_buf).await?;
let len = core::cmp::min((update_len - offset) as usize, chunk_buf.len());
digest.update(&chunk_buf[..len]);
}
output.copy_from_slice(digest.finalize().as_slice());
Ok(())
}
/// Mark to trigger firmware swap on next boot.
///
/// # Safety
@ -328,28 +343,26 @@ impl FirmwareUpdater {
#[cfg(feature = "ed25519-dalek")]
{
use ed25519_dalek::{Digest, PublicKey, Sha512, Signature, SignatureError, Verifier};
use ed25519_dalek::{PublicKey, Signature, SignatureError, Verifier};
use crate::digest_adapters::ed25519_dalek::Sha512;
let into_signature_error = |e: SignatureError| FirmwareUpdaterError::Signature(e.into());
let public_key = PublicKey::from_bytes(_public_key).map_err(into_signature_error)?;
let signature = Signature::from_bytes(_signature).map_err(into_signature_error)?;
let mut digest = Sha512::new();
for offset in (0.._update_len).step_by(_aligned.len()) {
self.dfu.read_blocking(_state_and_dfu_flash, offset as u32, _aligned)?;
let len = core::cmp::min(_update_len - offset, _aligned.len());
digest.update(&_aligned[..len]);
}
let mut message = [0; 64];
self.hash_blocking::<_, Sha512>(_state_and_dfu_flash, _update_len, _aligned, &mut message)?;
public_key
.verify(&digest.finalize(), &signature)
.map_err(into_signature_error)?
public_key.verify(&message, &signature).map_err(into_signature_error)?
}
#[cfg(feature = "ed25519-salty")]
{
use salty::constants::{PUBLICKEY_SERIALIZED_LENGTH, SIGNATURE_SERIALIZED_LENGTH};
use salty::{PublicKey, Sha512, Signature};
use salty::{PublicKey, Signature};
use crate::digest_adapters::salty::Sha512;
fn into_signature_error<E>(_: E) -> FirmwareUpdaterError {
FirmwareUpdaterError::Signature(signature::Error::default())
@ -360,14 +373,9 @@ impl FirmwareUpdater {
let signature: [u8; SIGNATURE_SERIALIZED_LENGTH] = _signature.try_into().map_err(into_signature_error)?;
let signature = Signature::try_from(&signature).map_err(into_signature_error)?;
let mut digest = Sha512::new();
for offset in (0.._update_len).step_by(_aligned.len()) {
self.dfu.read_blocking(_state_and_dfu_flash, offset as u32, _aligned)?;
let len = core::cmp::min(_update_len - offset, _aligned.len());
digest.update(&_aligned[..len]);
}
let mut message = [0; 64];
self.hash_blocking::<_, Sha512>(_state_and_dfu_flash, _update_len, _aligned, &mut message)?;
let message = digest.finalize();
let r = public_key.verify(&message, &signature);
trace!(
"Verifying with public key {}, signature {} and message {} yields ok: {}",
@ -382,6 +390,25 @@ impl FirmwareUpdater {
self.set_magic_blocking(_aligned, SWAP_MAGIC, _state_and_dfu_flash)
}
/// Verify the update in DFU with any digest.
pub fn hash_blocking<F: NorFlash, D: Digest>(
&mut self,
dfu_flash: &mut F,
update_len: usize,
chunk_buf: &mut [u8],
output: &mut [u8],
) -> Result<(), FirmwareUpdaterError> {
let update_len = update_len as u32;
let mut digest = D::new();
for offset in (0..update_len).step_by(chunk_buf.len()) {
self.dfu.read_blocking(dfu_flash, offset, chunk_buf)?;
let len = core::cmp::min((update_len - offset) as usize, chunk_buf.len());
digest.update(&chunk_buf[..len]);
}
output.copy_from_slice(digest.finalize().as_slice());
Ok(())
}
/// Mark to trigger firmware swap on next boot.
///
/// # Safety
@ -478,3 +505,32 @@ impl FirmwareUpdater {
Ok(self.dfu)
}
}
#[cfg(test)]
mod tests {
use futures::executor::block_on;
use sha1::{Digest, Sha1};
use super::*;
use crate::mem_flash::MemFlash;
#[test]
fn can_verify_sha1() {
const STATE: Partition = Partition::new(0, 4096);
const DFU: Partition = Partition::new(65536, 131072);
let mut flash = MemFlash::<131072, 4096, 8>::default();
let update = [0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66];
let mut to_write = [0; 4096];
to_write[..7].copy_from_slice(update.as_slice());
let mut updater = FirmwareUpdater::new(DFU, STATE);
block_on(updater.write_firmware(0, to_write.as_slice(), &mut flash)).unwrap();
let mut chunk_buf = [0; 2];
let mut hash = [0; 20];
block_on(updater.hash::<_, Sha1>(&mut flash, update.len(), &mut chunk_buf, &mut hash)).unwrap();
assert_eq!(Sha1::digest(update).as_slice(), hash);
}
}

1
embassy-boot/boot/src/lib.rs
View File

@ -6,6 +6,7 @@
mod fmt;
mod boot_loader;
mod digest_adapters;
mod firmware_updater;
mod mem_flash;
mod partition;

4
embassy-embedded-hal/Cargo.toml
View File

@ -19,8 +19,8 @@ nightly = ["embedded-hal-async", "embedded-storage-async"]
[dependencies]
embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true }
embedded-storage = "0.3.0"
embedded-storage-async = { version = "0.4.0", optional = true }
nb = "1.0.0"

27
embassy-embedded-hal/src/adapter.rs
View File

@ -36,27 +36,22 @@ where
E: embedded_hal_1::i2c::Error + 'static,
T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>,
{
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), Self::Error> {
self.wrapped.read(address, buffer)
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.wrapped.read(address, read)
}
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), Self::Error> {
self.wrapped.write(address, bytes)
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.wrapped.write(address, write)
}
async fn write_read<'a>(
&'a mut self,
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.wrapped.write_read(address, write, read)
}
async fn transaction(
&mut self,
address: u8,
bytes: &'a [u8],
buffer: &'a mut [u8],
) -> Result<(), Self::Error> {
self.wrapped.write_read(address, bytes, buffer)
}
async fn transaction<'a, 'b>(
&'a mut self,
address: u8,
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;

2
embassy-embedded-hal/src/lib.rs
View File

@ -1,7 +1,7 @@
#![cfg_attr(not(feature = "std"), no_std)]
#![cfg_attr(
feature = "nightly",
feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections, try_blocks)
)]
#![cfg_attr(feature = "nightly", allow(incomplete_features))]
#![warn(missing_docs)]

42
embassy-embedded-hal/src/shared_bus/asynch/i2c.rs
View File

@ -54,35 +54,35 @@ where
M: RawMutex + 'static,
BUS: i2c::I2c + 'static,
{
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
bus.read(address, read).await.map_err(I2cDeviceError::I2c)?;
Ok(())
}
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
bus.write(address, write).await.map_err(I2cDeviceError::I2c)?;
Ok(())
}
async fn write_read<'a>(
&'a mut self,
async fn write_read(
&mut self,
address: u8,
wr_buffer: &'a [u8],
rd_buffer: &'a mut [u8],
write: &[u8],
read: &mut [u8],
) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.write_read(address, wr_buffer, rd_buffer)
bus.write_read(address, write, read)
.await
.map_err(I2cDeviceError::I2c)?;
Ok(())
}
async fn transaction<'a, 'b>(
&'a mut self,
async fn transaction(
&mut self,
address: u8,
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
operations: &mut [embedded_hal_async::i2c::Operation<'_>],
) -> Result<(), I2cDeviceError<BUS::Error>> {
let _ = address;
let _ = operations;
@ -121,25 +121,25 @@ where
M: RawMutex + 'static,
BUS: i2c::I2c + SetConfig + 'static,
{
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
Ok(())
}
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
Ok(())
}
async fn write_read<'a>(
&'a mut self,
async fn write_read(
&mut self,
address: u8,
wr_buffer: &'a [u8],
rd_buffer: &'a mut [u8],
wr_buffer: &[u8],
rd_buffer: &mut [u8],
) -> Result<(), I2cDeviceError<BUS::Error>> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
@ -149,11 +149,7 @@ where
Ok(())
}
async fn transaction<'a, 'b>(
&'a mut self,
address: u8,
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
) -> Result<(), I2cDeviceError<BUS::Error>> {
async fn transaction(&mut self, address: u8, operations: &mut [i2c::Operation<'_>]) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()

175
embassy-embedded-hal/src/shared_bus/asynch/spi.rs
View File

@ -25,12 +25,11 @@
//! let spi_dev2 = SpiDevice::new(spi_bus, cs_pin2);
//! let display2 = ST7735::new(spi_dev2, dc2, rst2, Default::default(), 160, 128);
//! ```
use core::future::Future;
use embassy_sync::blocking_mutex::raw::RawMutex;
use embassy_sync::mutex::Mutex;
use embedded_hal_1::digital::OutputPin;
use embedded_hal_1::spi::ErrorType;
use embedded_hal_1::spi::Operation;
use embedded_hal_async::spi;
use crate::shared_bus::SpiDeviceError;
@ -57,33 +56,92 @@ where
type Error = SpiDeviceError<BUS::Error, CS::Error>;
}
unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
impl<M, BUS, CS> spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex + 'static,
BUS: spi::SpiBusFlush + 'static,
M: RawMutex,
BUS: spi::SpiBusRead,
CS: OutputPin,
{
type Bus = BUS;
async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
where
F: FnOnce(*mut Self::Bus) -> Fut,
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
{
async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = f(&mut *bus).await;
let op_res: Result<(), BUS::Error> = try {
for buf in operations {
bus.read(buf).await?;
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
}
}
impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: spi::SpiBusWrite,
CS: OutputPin,
{
async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res: Result<(), BUS::Error> = try {
for buf in operations {
bus.write(buf).await?;
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
}
}
impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: spi::SpiBus,
CS: OutputPin,
{
async fn transaction(&mut self, operations: &mut [spi::Operation<'_, u8>]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res: Result<(), BUS::Error> = try {
for op in operations {
match op {
Operation::Read(buf) => bus.read(buf).await?,
Operation::Write(buf) => bus.write(buf).await?,
Operation::Transfer(read, write) => bus.transfer(read, write).await?,
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
}
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
}
}
@ -114,33 +172,94 @@ where
type Error = SpiDeviceError<BUS::Error, CS::Error>;
}
unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex + 'static,
BUS: spi::SpiBusFlush + SetConfig + 'static,
M: RawMutex,
BUS: spi::SpiBusWrite + SetConfig,
CS: OutputPin,
{
type Bus = BUS;
async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
where
F: FnOnce(*mut Self::Bus) -> Fut,
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
{
async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = f(&mut *bus).await;
let op_res: Result<(), BUS::Error> = try {
for buf in operations {
bus.write(buf).await?;
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
}
}
impl<M, BUS, CS> spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex,
BUS: spi::SpiBusRead + SetConfig,
CS: OutputPin,
{
async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res: Result<(), BUS::Error> = try {
for buf in operations {
bus.read(buf).await?;
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
}
}
impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex,
BUS: spi::SpiBus + SetConfig,
CS: OutputPin,
{
async fn transaction(&mut self, operations: &mut [spi::Operation<'_, u8>]) -> Result<(), Self::Error> {
let mut bus = self.bus.lock().await;
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res: Result<(), BUS::Error> = try {
for op in operations {
match op {
Operation::Read(buf) => bus.read(buf).await?,
Operation::Write(buf) => bus.write(buf).await?,
Operation::Transfer(read, write) => bus.transfer(read, write).await?,
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
}
}
};
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush().await;
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
}
}

56
embassy-embedded-hal/src/shared_bus/blocking/i2c.rs
View File

@ -72,34 +72,6 @@ where
let _ = operations;
todo!()
}
fn write_iter<B: IntoIterator<Item = u8>>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
todo!()
}
fn write_iter_read<B: IntoIterator<Item = u8>>(
&mut self,
addr: u8,
bytes: B,
buffer: &mut [u8],
) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
let _ = buffer;
todo!()
}
fn transaction_iter<'a, O: IntoIterator<Item = Operation<'a>>>(
&mut self,
address: u8,
operations: O,
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
}
impl<'a, M, BUS, E> embedded_hal_02::blocking::i2c::Write for I2cDevice<'_, M, BUS>
@ -204,32 +176,4 @@ where
let _ = operations;
todo!()
}
fn write_iter<B: IntoIterator<Item = u8>>(&mut self, addr: u8, bytes: B) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
todo!()
}
fn write_iter_read<B: IntoIterator<Item = u8>>(
&mut self,
addr: u8,
bytes: B,
buffer: &mut [u8],
) -> Result<(), Self::Error> {
let _ = addr;
let _ = bytes;
let _ = buffer;
todo!()
}
fn transaction_iter<'a, O: IntoIterator<Item = Operation<'a>>>(
&mut self,
address: u8,
operations: O,
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()
}
}

157
embassy-embedded-hal/src/shared_bus/blocking/spi.rs
View File

@ -23,8 +23,7 @@ use core::cell::RefCell;
use embassy_sync::blocking_mutex::raw::RawMutex;
use embassy_sync::blocking_mutex::Mutex;
use embedded_hal_1::digital::OutputPin;
use embedded_hal_1::spi;
use embedded_hal_1::spi::SpiBusFlush;
use embedded_hal_1::spi::{self, Operation, SpiBus, SpiBusRead, SpiBusWrite};
use crate::shared_bus::SpiDeviceError;
use crate::SetConfig;
@ -50,30 +49,85 @@ where
type Error = SpiDeviceError<BUS::Error, CS::Error>;
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
impl<BUS, M, CS> embedded_hal_1::spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBusFlush,
BUS: SpiBusRead,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> {
fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = f(&mut bus);
let op_res = operations.iter_mut().try_for_each(|buf| bus.read(buf));
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
})
}
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBusWrite,
CS: OutputPin,
{
fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res = operations.iter().try_for_each(|buf| bus.write(buf));
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
})
}
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBus,
CS: OutputPin,
{
fn transaction(&mut self, operations: &mut [Operation<'_, u8>]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res = operations.iter_mut().try_for_each(|op| match op {
Operation::Read(buf) => bus.read(buf),
Operation::Write(buf) => bus.write(buf),
Operation::Transfer(read, write) => bus.transfer(read, write),
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf),
});
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
})
}
}
@ -89,11 +143,11 @@ where
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = bus.transfer(words);
let op_res = bus.transfer(words);
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
})
}
}
@ -110,11 +164,11 @@ where
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = bus.write(words);
let op_res = bus.write(words);
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
})
}
}
@ -146,30 +200,85 @@ where
type Error = SpiDeviceError<BUS::Error, CS::Error>;
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
impl<BUS, M, CS> embedded_hal_1::spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBusFlush + SetConfig,
BUS: SpiBusRead + SetConfig,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(&mut self, f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>) -> Result<R, Self::Error> {
fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let f_res = f(&mut bus);
let op_res = operations.iter_mut().try_for_each(|buf| bus.read(buf));
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(f_res)
Ok(op_res)
})
}
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBusWrite + SetConfig,
CS: OutputPin,
{
fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res = operations.iter().try_for_each(|buf| bus.write(buf));
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
})
}
}
impl<BUS, M, CS> embedded_hal_1::spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
where
M: RawMutex,
BUS: SpiBus + SetConfig,
CS: OutputPin,
{
fn transaction(&mut self, operations: &mut [Operation<'_, u8>]) -> Result<(), Self::Error> {
self.bus.lock(|bus| {
let mut bus = bus.borrow_mut();
bus.set_config(&self.config);
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
let op_res = operations.iter_mut().try_for_each(|op| match op {
Operation::Read(buf) => bus.read(buf),
Operation::Write(buf) => bus.write(buf),
Operation::Transfer(read, write) => bus.transfer(read, write),
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf),
});
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
flush_res.map_err(SpiDeviceError::Spi)?;
cs_res.map_err(SpiDeviceError::Cs)?;
Ok(op_res)
})
}
}

19
embassy-executor/Cargo.toml
View File

@ -14,21 +14,18 @@ categories = [
[package.metadata.embassy_docs]
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-executor-v$VERSION/embassy-executor/src/"
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-executor/src/"
features = ["nightly", "defmt"]
features = ["nightly", "defmt", "pender-callback"]
flavors = [
{ name = "std", target = "x86_64-unknown-linux-gnu", features = ["std"] },
{ name = "wasm", target = "wasm32-unknown-unknown", features = ["wasm"] },
{ name = "thumbv6m-none-eabi", target = "thumbv6m-none-eabi", features = [] },
{ name = "thumbv7m-none-eabi", target = "thumbv7m-none-eabi", features = [] },
{ name = "thumbv7em-none-eabi", target = "thumbv7em-none-eabi", features = [] },
{ name = "thumbv7em-none-eabihf", target = "thumbv7em-none-eabihf", features = [] },
{ name = "thumbv8m.base-none-eabi", target = "thumbv8m.base-none-eabi", features = [] },
{ name = "thumbv8m.main-none-eabi", target = "thumbv8m.main-none-eabi", features = [] },
{ name = "thumbv8m.main-none-eabihf", target = "thumbv8m.main-none-eabihf", features = [] },
{ name = "std", target = "x86_64-unknown-linux-gnu", features = ["arch-std", "executor-thread"] },
{ name = "wasm", target = "wasm32-unknown-unknown", features = ["arch-wasm", "executor-thread"] },
{ name = "cortex-m", target = "thumbv7em-none-eabi", features = ["arch-cortex-m", "executor-thread", "executor-interrupt"] },
{ name = "riscv32", target = "riscv32imac-unknown-none-elf", features = ["arch-riscv32", "executor-thread"] },
]
[package.metadata.docs.rs]
features = ["std", "nightly", "defmt"]
default-target = "thumbv7em-none-eabi"
targets = ["thumbv7em-none-eabi"]
features = ["nightly", "defmt", "pender-callback", "arch-cortex-m", "executor-thread", "executor-interrupt"]
[features]

28
embassy-executor/src/raw/mod.rs
View File

@ -22,7 +22,6 @@ use core::ptr::NonNull;
use core::task::{Context, Poll};
use atomic_polyfill::{AtomicU32, Ordering};
use critical_section::CriticalSection;
#[cfg(feature = "integrated-timers")]
use embassy_time::driver::{self, AlarmHandle};
#[cfg(feature = "integrated-timers")]
@ -373,11 +372,11 @@ impl SyncExecutor {
/// - `task` must be set up to run in this executor.
/// - `task` must NOT be already enqueued (in this executor or another one).
#[inline(always)]
unsafe fn enqueue(&self, cs: CriticalSection, task: TaskRef) {
unsafe fn enqueue(&self, task: TaskRef) {
#[cfg(feature = "rtos-trace")]
trace::task_ready_begin(task.as_ptr() as u32);
if self.run_queue.enqueue(cs, task) {
if self.run_queue.enqueue(task) {
self.pender.pend();
}
}
@ -394,9 +393,7 @@ impl SyncExecutor {
#[cfg(feature = "rtos-trace")]
trace::task_new(task.as_ptr() as u32);
critical_section::with(|cs| {
self.enqueue(cs, task);
})
self.enqueue(task);
}
/// # Safety
@ -552,24 +549,25 @@ impl Executor {
///
/// You can obtain a `TaskRef` from a `Waker` using [`task_from_waker`].
pub fn wake_task(task: TaskRef) {
critical_section::with(|cs| {
let header = task.header();
let state = header.state.load(Ordering::Relaxed);
let header = task.header();
let res = header.state.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |state| {
// If already scheduled, or if not started,
if (state & STATE_RUN_QUEUED != 0) || (state & STATE_SPAWNED == 0) {
return;
None
} else {
// Mark it as scheduled
Some(state | STATE_RUN_QUEUED)
}
});
// Mark it as scheduled
header.state.store(state | STATE_RUN_QUEUED, Ordering::Relaxed);
if res.is_ok() {
// We have just marked the task as scheduled, so enqueue it.
unsafe {
let executor = header.executor.get().unwrap_unchecked();
executor.enqueue(cs, task);
executor.enqueue(task);
}
})
}
}
#[cfg(feature = "integrated-timers")]

18
embassy-executor/src/raw/run_queue.rs
View File

@ -2,7 +2,6 @@ use core::ptr;
use core::ptr::NonNull;
use atomic_polyfill::{AtomicPtr, Ordering};
use critical_section::CriticalSection;
use super::{TaskHeader, TaskRef};
@ -46,11 +45,18 @@ impl RunQueue {
///
/// `item` must NOT be already enqueued in any queue.
#[inline(always)]
pub(crate) unsafe fn enqueue(&self, _cs: CriticalSection, task: TaskRef) -> bool {
let prev = self.head.load(Ordering::Relaxed);
task.header().run_queue_item.next.store(prev, Ordering::Relaxed);
self.head.store(task.as_ptr() as _, Ordering::Relaxed);
prev.is_null()
pub(crate) unsafe fn enqueue(&self, task: TaskRef) -> bool {
let mut was_empty = false;
self.head
.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |prev| {
was_empty = prev.is_null();
task.header().run_queue_item.next.store(prev, Ordering::Relaxed);
Some(task.as_ptr() as *mut _)
})
.ok();
was_empty
}
/// Empty the queue, then call `on_task` for each task that was in the queue.

12
embassy-lora/Cargo.toml
View File

@ -9,9 +9,9 @@ src_base = "https://github.com/embassy-rs/embassy/blob/embassy-lora-v$VERSION/em
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-lora/src/"
features = ["time", "defmt"]
flavors = [
{ name = "sx126x", target = "thumbv7em-none-eabihf", features = ["sx126x"] },
{ name = "sx127x", target = "thumbv7em-none-eabihf", features = ["sx127x", "embassy-stm32/stm32wl55jc-cm4", "embassy-stm32/time-driver-any"] },
{ name = "stm32wl", target = "thumbv7em-none-eabihf", features = ["stm32wl", "embassy-stm32/stm32wl55jc-cm4", "embassy-stm32/time-driver-any"] },
{ name = "sx126x", target = "thumbv7em-none-eabihf", features = ["sx126x"] },
{ name = "sx127x", target = "thumbv7em-none-eabihf", features = ["sx127x"] },
{ name = "stm32wl", target = "thumbv7em-none-eabihf", features = ["stm32wl", "embassy-stm32?/stm32wl55jc-cm4", "embassy-stm32?/time-driver-any"] },
]
[lib]
@ -19,7 +19,7 @@ flavors = [
[features]
sx126x = []
sx127x = []
stm32wl = ["embassy-stm32", "embassy-stm32/subghz"]
stm32wl = ["dep:embassy-stm32"]
time = []
defmt = ["dep:defmt", "lorawan/defmt", "lorawan-device/defmt"]
@ -31,8 +31,8 @@ log = { version = "0.4.14", optional = true }
embassy-time = { version = "0.1.0", path = "../embassy-time" }
embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", default-features = false, optional = true }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
embassy-hal-common = { version = "0.1.0", path = "../embassy-hal-common", default-features = false }
futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
embedded-hal = { version = "0.2", features = ["unproven"] }

4
embassy-nrf/Cargo.toml
View File

@ -87,8 +87,8 @@ embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional=true }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true}
embedded-io = { version = "0.4.0", features = ["async"], optional = true }
defmt = { version = "0.3", optional = true }

49
embassy-nrf/src/twim.rs
View File

@ -846,20 +846,6 @@ mod eh1 {
self.blocking_write(address, buffer)
}
fn write_iter<B>(&mut self, _address: u8, _bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
}
fn write_iter_read<B>(&mut self, _address: u8, _bytes: B, _buffer: &mut [u8]) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
@ -871,13 +857,6 @@ mod eh1 {
) -> Result<(), Self::Error> {
todo!();
}
fn transaction_iter<'a, O>(&mut self, _address: u8, _operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = embedded_hal_1::i2c::Operation<'a>>,
{
todo!();
}
}
}
@ -885,28 +864,22 @@ mod eh1 {
mod eha {
use super::*;
impl<'d, T: Instance> embedded_hal_async::i2c::I2c for Twim<'d, T> {
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), Error> {
self.read(address, buffer).await
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.read(address, read).await
}
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), Error> {
self.write(address, bytes).await
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.write(address, write).await
}
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.write_read(address, write, read).await
}
async fn write_read<'a>(
&'a mut self,
async fn transaction(
&mut self,
address: u8,
wr_buffer: &'a [u8],
rd_buffer: &'a mut [u8],
) -> Result<(), Error> {
self.write_read(address, wr_buffer, rd_buffer).await
}
async fn transaction<'a, 'b>(
&'a mut self,
address: u8,
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
) -> Result<(), Error> {
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;
todo!()

6
embassy-rp/Cargo.toml
View File

@ -65,9 +65,9 @@ rp2040-pac2 = { git = "https://github.com/embassy-rs/rp2040-pac2", rev="017e3c90
#rp2040-pac2 = { path = "../../rp2040-pac2", features = ["rt"] }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true}
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true}
embedded-hal-nb = { version = "=1.0.0-alpha.2", optional = true}
paste = "1.0"
pio-proc = {version= "0.2", optional = true}

59
embassy-rp/src/gpio.rs
View File

@ -437,6 +437,37 @@ impl<'d, T: Pin> OutputOpenDrain<'d, T> {
pub fn is_low(&self) -> bool {
self.pin.is_low()
}
/// Returns current pin level
#[inline]
pub fn get_level(&self) -> Level {
self.is_high().into()
}
#[inline]
pub async fn wait_for_high(&mut self) {
self.pin.wait_for_high().await;
}
#[inline]
pub async fn wait_for_low(&mut self) {
self.pin.wait_for_low().await;
}
#[inline]
pub async fn wait_for_rising_edge(&mut self) {
self.pin.wait_for_rising_edge().await;
}
#[inline]
pub async fn wait_for_falling_edge(&mut self) {
self.pin.wait_for_falling_edge().await;
}
#[inline]
pub async fn wait_for_any_edge(&mut self) {
self.pin.wait_for_any_edge().await;
}
}
/// GPIO flexible pin.
@ -1117,4 +1148,32 @@ mod eh1 {
Ok(())
}
}
#[cfg(feature = "nightly")]
impl<'d, T: Pin> embedded_hal_async::digital::Wait for OutputOpenDrain<'d, T> {
async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
self.wait_for_high().await;
Ok(())
}
async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
self.wait_for_low().await;
Ok(())
}
async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_rising_edge().await;
Ok(())
}
async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_falling_edge().await;
Ok(())
}
async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
self.wait_for_any_edge().await;
Ok(())
}
}
}

107
embassy-rp/src/i2c.rs
View File

@ -490,14 +490,14 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
}
}
fn read_blocking_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
if buffer.is_empty() {
fn read_blocking_internal(&mut self, read: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
if read.is_empty() {
return Err(Error::InvalidReadBufferLength);
}
let p = T::regs();
let lastindex = buffer.len() - 1;
for (i, byte) in buffer.iter_mut().enumerate() {
let lastindex = read.len() - 1;
for (i, byte) in read.iter_mut().enumerate() {
let first = i == 0;
let last = i == lastindex;
@ -524,15 +524,15 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
Ok(())
}
fn write_blocking_internal(&mut self, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
if bytes.is_empty() {
fn write_blocking_internal(&mut self, write: &[u8], send_stop: bool) -> Result<(), Error> {
if write.is_empty() {
return Err(Error::InvalidWriteBufferLength);
}
let p = T::regs();
for (i, byte) in bytes.iter().enumerate() {
let last = i == bytes.len() - 1;
for (i, byte) in write.iter().enumerate() {
let last = i == write.len() - 1;
// NOTE(unsafe) We have &mut self
unsafe {
@ -572,21 +572,21 @@ impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
// Blocking public API
// =========================
pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
Self::setup(address.into())?;
self.read_blocking_internal(buffer, true, true)
self.read_blocking_internal(read, true, true)
// Automatic Stop
}
pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
Self::setup(address.into())?;
self.write_blocking_internal(bytes, true)
self.write_blocking_internal(write, true)
}
pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
Self::setup(address.into())?;
self.write_blocking_internal(bytes, false)?;
self.read_blocking_internal(buffer, true, true)
self.write_blocking_internal(write, false)?;
self.read_blocking_internal(read, true, true)
// Automatic Stop
}
}
@ -644,48 +644,22 @@ mod eh1 {
}
impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> {
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, buffer)
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_iter<B>(&mut self, address: u8, bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
let mut peekable = bytes.into_iter().peekable();
Self::setup(address.into())?;
while let Some(tx) = peekable.next() {
self.write_blocking_internal(&[tx], peekable.peek().is_none())?;
}
Ok(())
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn write_iter_read<B>(&mut self, address: u8, bytes: B, buffer: &mut [u8]) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
let peekable = bytes.into_iter().peekable();
Self::setup(address.into())?;
for tx in peekable {
self.write_blocking_internal(&[tx], false)?
}
self.read_blocking_internal(buffer, true, true)
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
fn transaction<'a>(
fn transaction(
&mut self,
address: u8,
operations: &mut [embedded_hal_1::i2c::Operation<'a>],
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
Self::setup(address.into())?;
for i in 0..operations.len() {
@ -697,22 +671,6 @@ mod eh1 {
}
Ok(())
}
fn transaction_iter<'a, O>(&mut self, address: u8, operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = embedded_hal_1::i2c::Operation<'a>>,
{
Self::setup(address.into())?;
let mut peekable = operations.into_iter().peekable();
while let Some(operation) = peekable.next() {
let last = peekable.peek().is_none();
match operation {
embedded_hal_1::i2c::Operation::Read(buf) => self.read_blocking_internal(buf, false, last)?,
embedded_hal_1::i2c::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
}
}
Ok(())
}
}
}
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
@ -727,36 +685,29 @@ mod nightly {
A: AddressMode + Into<u16> + 'static,
T: Instance + 'd,
{
async fn read<'a>(&'a mut self, address: A, read: &'a mut [u8]) -> Result<(), Self::Error> {
async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
let addr: u16 = address.into();
Self::setup(addr)?;
self.read_async_internal(read, false, true).await
}
async fn write<'a>(&'a mut self, address: A, write: &'a [u8]) -> Result<(), Self::Error> {
async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
let addr: u16 = address.into();
Self::setup(addr)?;
self.write_async_internal(write.iter().copied(), true).await
}
async fn write_read<'a>(
&'a mut self,
address: A,
write: &'a [u8],
read: &'a mut [u8],
) -> Result<(), Self::Error> {
async fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
let addr: u16 = address.into();
Self::setup(addr)?;
self.write_async_internal(write.iter().cloned(), false).await?;
self.read_async_internal(read, false, true).await
}
async fn transaction<'a, 'b>(
&'a mut self,
address: A,
operations: &'a mut [Operation<'b>],
) -> Result<(), Self::Error> {
async fn transaction(&mut self, address: A, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
let addr: u16 = address.into();
let mut iterator = operations.iter_mut();

1
embassy-rp/src/spi.rs
View File

@ -19,6 +19,7 @@ pub enum Error {
}
#[non_exhaustive]
#[derive(Clone)]
pub struct Config {
pub frequency: u32,
pub phase: Phase,

94
embassy-stm32/Cargo.toml
View File

@ -8,10 +8,7 @@ license = "MIT OR Apache-2.0"
src_base = "https://github.com/embassy-rs/embassy/blob/embassy-stm32-v$VERSION/embassy-stm32/src/"
src_base_git = "https://github.com/embassy-rs/embassy/blob/$COMMIT/embassy-stm32/src/"
# TODO: sdmmc
# TODO: net
# TODO: subghz
features = ["nightly", "defmt", "unstable-pac", "unstable-traits", "exti", "time-driver-any"]
features = ["nightly", "defmt", "unstable-pac", "unstable-traits", "exti", "time-driver-any", "time"]
flavors = [
{ regex_feature = "stm32f0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32f1.*", target = "thumbv7m-none-eabi" },
@ -22,6 +19,7 @@ flavors = [
{ regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32h5.*", target = "thumbv8m.main-none-eabihf" },
{ regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" },
{ regex_feature = "stm32l0.*", target = "thumbv6m-none-eabi" },
{ regex_feature = "stm32l1.*", target = "thumbv7m-none-eabi" },
@ -44,9 +42,9 @@ embassy-net-driver = { version = "0.1.0", path = "../embassy-net-driver" }
embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
embedded-hal-nb = { version = "=1.0.0-alpha.1", optional = true}
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true}
embedded-hal-nb = { version = "=1.0.0-alpha.2", optional = true}
embedded-storage = "0.3.0"
@ -60,7 +58,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "46d1b1c2ff13e31e282ec1e352421721694f126a", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
stm32-metapac = { version = "2", features = ["rt"] }
stm32-metapac = "5"
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@ -69,15 +67,18 @@ seq-macro = "0.3.0"
cfg-if = "1.0.0"
embedded-io = { version = "0.4.0", features = ["async"], optional = true }
[dev-dependencies]
critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { version = "2", default-features = false, features = ["metadata"]}
stm32-metapac = { version = "5", default-features = false, features = ["metadata"]}
[features]
default = ["stm32-metapac/rt"]
defmt = ["dep:defmt", "bxcan/unstable-defmt", "embassy-sync/defmt", "embassy-executor/defmt", "embassy-embedded-hal/defmt", "embassy-hal-common/defmt", "embedded-io?/defmt", "embassy-usb-driver?/defmt", "embassy-net-driver/defmt"]
memory-x = ["stm32-metapac/memory-x"]
subghz = []
exti = []
# Enables additional driver features that depend on embassy-time
@ -830,6 +831,37 @@ stm32g4a1ke = [ "stm32-metapac/stm32g4a1ke" ]
stm32g4a1me = [ "stm32-metapac/stm32g4a1me" ]
stm32g4a1re = [ "stm32-metapac/stm32g4a1re" ]
stm32g4a1ve = [ "stm32-metapac/stm32g4a1ve" ]
stm32h503cb = [ "stm32-metapac/stm32h503cb" ]
stm32h503eb = [ "stm32-metapac/stm32h503eb" ]
stm32h503kb = [ "stm32-metapac/stm32h503kb" ]
stm32h503rb = [ "stm32-metapac/stm32h503rb" ]
stm32h562ag = [ "stm32-metapac/stm32h562ag" ]
stm32h562ai = [ "stm32-metapac/stm32h562ai" ]
stm32h562ig = [ "stm32-metapac/stm32h562ig" ]
stm32h562ii = [ "stm32-metapac/stm32h562ii" ]
stm32h562rg = [ "stm32-metapac/stm32h562rg" ]
stm32h562ri = [ "stm32-metapac/stm32h562ri" ]
stm32h562vg = [ "stm32-metapac/stm32h562vg" ]
stm32h562vi = [ "stm32-metapac/stm32h562vi" ]
stm32h562zg = [ "stm32-metapac/stm32h562zg" ]
stm32h562zi = [ "stm32-metapac/stm32h562zi" ]
stm32h563ag = [ "stm32-metapac/stm32h563ag" ]
stm32h563ai = [ "stm32-metapac/stm32h563ai" ]
stm32h563ig = [ "stm32-metapac/stm32h563ig" ]
stm32h563ii = [ "stm32-metapac/stm32h563ii" ]
stm32h563mi = [ "stm32-metapac/stm32h563mi" ]
stm32h563rg = [ "stm32-metapac/stm32h563rg" ]
stm32h563ri = [ "stm32-metapac/stm32h563ri" ]
stm32h563vg = [ "stm32-metapac/stm32h563vg" ]
stm32h563vi = [ "stm32-metapac/stm32h563vi" ]
stm32h563zg = [ "stm32-metapac/stm32h563zg" ]
stm32h563zi = [ "stm32-metapac/stm32h563zi" ]
stm32h573ai = [ "stm32-metapac/stm32h573ai" ]
stm32h573ii = [ "stm32-metapac/stm32h573ii" ]
stm32h573mi = [ "stm32-metapac/stm32h573mi" ]
stm32h573ri = [ "stm32-metapac/stm32h573ri" ]
stm32h573vi = [ "stm32-metapac/stm32h573vi" ]
stm32h573zi = [ "stm32-metapac/stm32h573zi" ]
stm32h723ve = [ "stm32-metapac/stm32h723ve" ]
stm32h723vg = [ "stm32-metapac/stm32h723vg" ]
stm32h723ze = [ "stm32-metapac/stm32h723ze" ]
@ -1312,6 +1344,22 @@ stm32l562qe = [ "stm32-metapac/stm32l562qe" ]
stm32l562re = [ "stm32-metapac/stm32l562re" ]
stm32l562ve = [ "stm32-metapac/stm32l562ve" ]
stm32l562ze = [ "stm32-metapac/stm32l562ze" ]
stm32u535cb = [ "stm32-metapac/stm32u535cb" ]
stm32u535cc = [ "stm32-metapac/stm32u535cc" ]
stm32u535ce = [ "stm32-metapac/stm32u535ce" ]
stm32u535je = [ "stm32-metapac/stm32u535je" ]
stm32u535nc = [ "stm32-metapac/stm32u535nc" ]
stm32u535ne = [ "stm32-metapac/stm32u535ne" ]
stm32u535rb = [ "stm32-metapac/stm32u535rb" ]
stm32u535rc = [ "stm32-metapac/stm32u535rc" ]
stm32u535re = [ "stm32-metapac/stm32u535re" ]
stm32u535vc = [ "stm32-metapac/stm32u535vc" ]
stm32u535ve = [ "stm32-metapac/stm32u535ve" ]
stm32u545ce = [ "stm32-metapac/stm32u545ce" ]
stm32u545je = [ "stm32-metapac/stm32u545je" ]
stm32u545ne = [ "stm32-metapac/stm32u545ne" ]
stm32u545re = [ "stm32-metapac/stm32u545re" ]
stm32u545ve = [ "stm32-metapac/stm32u545ve" ]
stm32u575ag = [ "stm32-metapac/stm32u575ag" ]
stm32u575ai = [ "stm32-metapac/stm32u575ai" ]
stm32u575cg = [ "stm32-metapac/stm32u575cg" ]
@ -1333,6 +1381,32 @@ stm32u585qi = [ "stm32-metapac/stm32u585qi" ]
stm32u585ri = [ "stm32-metapac/stm32u585ri" ]
stm32u585vi = [ "stm32-metapac/stm32u585vi" ]
stm32u585zi = [ "stm32-metapac/stm32u585zi" ]
stm32u595ai = [ "stm32-metapac/stm32u595ai" ]
stm32u595aj = [ "stm32-metapac/stm32u595aj" ]
stm32u595qi = [ "stm32-metapac/stm32u595qi" ]
stm32u595qj = [ "stm32-metapac/stm32u595qj" ]
stm32u595ri = [ "stm32-metapac/stm32u595ri" ]
stm32u595rj = [ "stm32-metapac/stm32u595rj" ]
stm32u595vi = [ "stm32-metapac/stm32u595vi" ]
stm32u595vj = [ "stm32-metapac/stm32u595vj" ]
stm32u595zi = [ "stm32-metapac/stm32u595zi" ]
stm32u595zj = [ "stm32-metapac/stm32u595zj" ]
stm32u599bj = [ "stm32-metapac/stm32u599bj" ]
stm32u599ni = [ "stm32-metapac/stm32u599ni" ]
stm32u599nj = [ "stm32-metapac/stm32u599nj" ]
stm32u599vi = [ "stm32-metapac/stm32u599vi" ]
stm32u599vj = [ "stm32-metapac/stm32u599vj" ]
stm32u599zi = [ "stm32-metapac/stm32u599zi" ]
stm32u599zj = [ "stm32-metapac/stm32u599zj" ]
stm32u5a5aj = [ "stm32-metapac/stm32u5a5aj" ]
stm32u5a5qj = [ "stm32-metapac/stm32u5a5qj" ]
stm32u5a5rj = [ "stm32-metapac/stm32u5a5rj" ]
stm32u5a5vj = [ "stm32-metapac/stm32u5a5vj" ]
stm32u5a5zj = [ "stm32-metapac/stm32u5a5zj" ]
stm32u5a9bj = [ "stm32-metapac/stm32u5a9bj" ]
stm32u5a9nj = [ "stm32-metapac/stm32u5a9nj" ]
stm32u5a9vj = [ "stm32-metapac/stm32u5a9vj" ]
stm32u5a9zj = [ "stm32-metapac/stm32u5a9zj" ]
stm32wb10cc = [ "stm32-metapac/stm32wb10cc" ]
stm32wb15cc = [ "stm32-metapac/stm32wb15cc" ]
stm32wb30ce = [ "stm32-metapac/stm32wb30ce" ]

130
embassy-stm32/build.rs
View File

@ -3,9 +3,9 @@ use std::fmt::Write as _;
use std::path::PathBuf;
use std::{env, fs};
use proc_macro2::TokenStream;
use proc_macro2::{Ident, TokenStream};
use quote::{format_ident, quote};
use stm32_metapac::metadata::METADATA;
use stm32_metapac::metadata::{MemoryRegionKind, METADATA};
fn main() {
let chip_name = match env::vars()
@ -50,7 +50,7 @@ fn main() {
// We *shouldn't* have singletons for these, but the HAL currently requires
// singletons, for using with RccPeripheral to enable/disable clocks to them.
"rcc" => {
if r.version.starts_with("h7") || r.version.starts_with("f4") {
if r.version.starts_with("h5") || r.version.starts_with("h7") || r.version.starts_with("f4") {
singletons.push("MCO1".to_string());
singletons.push("MCO2".to_string());
}
@ -106,6 +106,94 @@ fn main() {
}
});
// ========
// Generate FLASH regions
let mut flash_regions = TokenStream::new();
let flash_memory_regions: Vec<_> = METADATA
.memory
.iter()
.filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
.collect();
for region in flash_memory_regions.iter() {
let region_name = format_ident!("{}", get_flash_region_name(region.name));
let bank_variant = format_ident!(
"{}",
if region.name.starts_with("BANK_1") {
"Bank1"
} else if region.name.starts_with("BANK_2") {
"Bank2"
} else if region.name == "OTP" {
"Otp"
} else {
continue;
}
);
let base = region.address;
let size = region.size;
let settings = region.settings.as_ref().unwrap();
let erase_size = settings.erase_size;
let write_size = settings.write_size;
let erase_value = settings.erase_value;
flash_regions.extend(quote! {
pub const #region_name: crate::flash::FlashRegion = crate::flash::FlashRegion {
bank: crate::flash::FlashBank::#bank_variant,
base: #base,
size: #size,
erase_size: #erase_size,
write_size: #write_size,
erase_value: #erase_value,
};
});
let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
flash_regions.extend(quote! {
#[cfg(flash)]
pub struct #region_type<'d>(pub &'static crate::flash::FlashRegion, pub(crate) embassy_hal_common::PeripheralRef<'d, crate::peripherals::FLASH>,);
});
}
let (fields, (inits, region_names)): (Vec<TokenStream>, (Vec<TokenStream>, Vec<Ident>)) = flash_memory_regions
.iter()
.map(|f| {
let region_name = get_flash_region_name(f.name);
let field_name = format_ident!("{}", region_name.to_lowercase());
let field_type = format_ident!("{}", get_flash_region_type_name(f.name));
let field = quote! {
pub #field_name: #field_type<'d>
};
let region_name = format_ident!("{}", region_name);
let init = quote! {
#field_name: #field_type(&#region_name, unsafe { p.clone_unchecked()})
};
(field, (init, region_name))
})
.unzip();
let regions_len = flash_memory_regions.len();
flash_regions.extend(quote! {
#[cfg(flash)]
pub struct FlashLayout<'d> {
#(#fields),*
}
#[cfg(flash)]
impl<'d> FlashLayout<'d> {
pub(crate) fn new(mut p: embassy_hal_common::PeripheralRef<'d, crate::peripherals::FLASH>) -> Self {
Self {
#(#inits),*
}
}
}
pub const FLASH_REGIONS: [&crate::flash::FlashRegion; #regions_len] = [
#(&#region_names),*
];
});
g.extend(quote! { pub mod flash_regions { #flash_regions } });
// ========
// Generate DMA IRQs.
@ -451,7 +539,10 @@ fn main() {
// MCO is special
if pin.signal.starts_with("MCO_") {
// Supported in H7 only for now
if regs.version.starts_with("h7") || regs.version.starts_with("f4") {
if regs.version.starts_with("h5")
|| regs.version.starts_with("h7")
|| regs.version.starts_with("f4")
{
peri = format_ident!("{}", pin.signal.replace("_", ""));
} else {
continue;
@ -578,11 +669,25 @@ fn main() {
// ========
// Write foreach_foo! macrotables
let mut flash_regions_table: Vec<Vec<String>> = Vec::new();
let mut interrupts_table: Vec<Vec<String>> = Vec::new();
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
let mut pins_table: Vec<Vec<String>> = Vec::new();
let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
for m in METADATA
.memory
.iter()
.filter(|m| m.kind == MemoryRegionKind::Flash && m.settings.is_some())
{
let settings = m.settings.as_ref().unwrap();
let mut row = Vec::new();
row.push(get_flash_region_type_name(m.name));
row.push(settings.write_size.to_string());
row.push(settings.erase_size.to_string());
flash_regions_table.push(row);
}
let gpio_base = METADATA.peripherals.iter().find(|p| p.name == "GPIOA").unwrap().address as u32;
let gpio_stride = 0x400;
@ -679,6 +784,7 @@ fn main() {
let mut m = String::new();
make_table(&mut m, "foreach_flash_region", &flash_regions_table);
make_table(&mut m, "foreach_interrupt", &interrupts_table);
make_table(&mut m, "foreach_peripheral", &peripherals_table);
make_table(&mut m, "foreach_pin", &pins_table);
@ -831,3 +937,19 @@ macro_rules! {} {{
)
.unwrap();
}
fn get_flash_region_name(name: &str) -> String {
let name = name.replace("BANK_", "BANK").replace("REGION_", "REGION");
if name.contains("REGION") {
name
} else {
name + "_REGION"
}
}
fn get_flash_region_type_name(name: &str) -> String {
get_flash_region_name(name)
.replace("BANK", "Bank")
.replace("REGION", "Region")
.replace("_", "")
}

11
embassy-stm32/src/adc/mod.rs
View File

@ -7,21 +7,18 @@
#[cfg_attr(adc_v4, path = "v4.rs")]
mod _version;
#[cfg(not(any(adc_f1, adc_v1)))]
#[cfg(not(adc_f1))]
mod resolution;
#[cfg(not(adc_v1))]
mod sample_time;
#[allow(unused)]
pub use _version::*;
#[cfg(not(any(adc_f1, adc_v1)))]
#[cfg(not(adc_f1))]
pub use resolution::Resolution;
#[cfg(not(adc_v1))]
pub use sample_time::SampleTime;
use crate::peripherals;
#[cfg(not(adc_v1))]
pub struct Adc<'d, T: Instance> {
#[allow(unused)]
adc: crate::PeripheralRef<'d, T>,
@ -44,9 +41,9 @@ pub(crate) mod sealed {
}
}
#[cfg(not(any(adc_f1, adc_v2, adc_v4)))]
#[cfg(not(any(adc_f1, adc_v1, adc_v2, adc_v4)))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> {}
#[cfg(any(adc_f1, adc_v2, adc_v4))]
#[cfg(any(adc_f1, adc_v1, adc_v2, adc_v4))]
pub trait Instance: sealed::Instance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {}
pub trait AdcPin<T: Instance>: sealed::AdcPin<T> {}

8
embassy-stm32/src/adc/resolution.rs
View File

@ -1,4 +1,4 @@
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
pub enum Resolution {
TwelveBit,
@ -19,7 +19,7 @@ pub enum Resolution {
impl Default for Resolution {
fn default() -> Self {
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
{
Self::TwelveBit
}
@ -40,7 +40,7 @@ impl From<Resolution> for crate::pac::adc::vals::Res {
Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
}
}
@ -56,7 +56,7 @@ impl Resolution {
Resolution::TwelveBit => (1 << 12) - 1,
Resolution::TenBit => (1 << 10) - 1,
Resolution::EightBit => (1 << 8) - 1,
#[cfg(any(adc_v2, adc_v3, adc_g0))]
#[cfg(any(adc_v1, adc_v2, adc_v3, adc_g0))]
Resolution::SixBit => (1 << 6) - 1,
}
}

2
embassy-stm32/src/adc/sample_time.rs
View File

@ -25,7 +25,7 @@ macro_rules! impl_sample_time {
};
}
#[cfg(adc_f1)]
#[cfg(any(adc_f1, adc_v1))]
impl_sample_time!(
"1.5",
Cycles1_5,

170
embassy-stm32/src/adc/v1.rs
View File

@ -1 +1,171 @@
use embassy_hal_common::into_ref;
use embedded_hal_02::blocking::delay::DelayUs;
use crate::adc::{Adc, AdcPin, Instance, InternalChannel, Resolution, SampleTime};
use crate::peripherals::ADC;
use crate::Peripheral;
pub const VDDA_CALIB_MV: u32 = 3300;
pub const VREF_INT: u32 = 1230;
pub struct Vbat;
impl InternalChannel<ADC> for Vbat {}
impl super::sealed::InternalChannel<ADC> for Vbat {
fn channel(&self) -> u8 {
18
}
}
pub struct Vref;
impl InternalChannel<ADC> for Vref {}
impl super::sealed::InternalChannel<ADC> for Vref {
fn channel(&self) -> u8 {
17
}
}
pub struct Temperature;
impl InternalChannel<ADC> for Temperature {}
impl super::sealed::InternalChannel<ADC> for Temperature {
fn channel(&self) -> u8 {
16
}
}
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::enable();
T::reset();
// Delay 1μs when using HSI14 as the ADC clock.
//
// Table 57. ADC characteristics
// tstab = 14 * 1/fadc
delay.delay_us(1);
let s = Self {
adc,
sample_time: Default::default(),
};
s.calibrate();
s
}
pub fn enable_vbat(&self, _delay: &mut impl DelayUs<u32>) -> Vbat {
// SMP must be ≥ 56 ADC clock cycles when using HSI14.
//
// 6.3.20 Vbat monitoring characteristics
// ts_vbat ≥ 4μs
unsafe {
T::regs().ccr().modify(|reg| reg.set_vbaten(true));
}
Vbat
}
pub fn enable_vref(&self, delay: &mut impl DelayUs<u32>) -> Vref {
// Table 28. Embedded internal reference voltage
// tstart = 10μs
unsafe {
T::regs().ccr().modify(|reg| reg.set_vrefen(true));
}
delay.delay_us(10);
Vref
}
pub fn enable_temperature(&self, delay: &mut impl DelayUs<u32>) -> Temperature {
// SMP must be ≥ 56 ADC clock cycles when using HSI14.
//
// 6.3.19 Temperature sensor characteristics
// tstart ≤ 10μs
// ts_temp ≥ 4μs
unsafe {
T::regs().ccr().modify(|reg| reg.set_tsen(true));
}
delay.delay_us(10);
Temperature
}
fn calibrate(&self) {
unsafe {
// A.7.1 ADC calibration code example
if T::regs().cr().read().aden() {
T::regs().cr().modify(|reg| reg.set_addis(true));
}
while T::regs().cr().read().aden() {
// spin
}
T::regs().cfgr1().modify(|reg| reg.set_dmaen(false));
T::regs().cr().modify(|reg| reg.set_adcal(true));
while T::regs().cr().read().adcal() {
// spin
}
}
}
pub fn set_sample_time(&mut self, sample_time: SampleTime) {
self.sample_time = sample_time;
}
pub fn set_resolution(&mut self, resolution: Resolution) {
unsafe {
T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
}
}
pub fn read<P>(&mut self, pin: &mut P) -> u16
where
P: AdcPin<T> + crate::gpio::sealed::Pin,
{
let channel = pin.channel();
unsafe {
pin.set_as_analog();
self.read_channel(channel)
}
}
pub fn read_internal(&mut self, channel: &mut impl InternalChannel<T>) -> u16 {
let channel = channel.channel();
unsafe { self.read_channel(channel) }
}
unsafe fn read_channel(&mut self, channel: u8) -> u16 {
// A.7.2 ADC enable sequence code example
if T::regs().isr().read().adrdy() {
T::regs().isr().modify(|reg| reg.set_adrdy(true));
}
T::regs().cr().modify(|reg| reg.set_aden(true));
while !T::regs().isr().read().adrdy() {
// ES0233, 2.4.3 ADEN bit cannot be set immediately after the ADC calibration
// Workaround: When the ADC calibration is complete (ADCAL = 0), keep setting the
// ADEN bit until the ADRDY flag goes high.
T::regs().cr().modify(|reg| reg.set_aden(true));
}
T::regs().isr().modify(|reg| {
reg.set_eoc(true);
reg.set_eosmp(true);
});
// A.7.5 Single conversion sequence code example - Software trigger
T::regs().chselr().write(|reg| reg.set_chselx(channel as usize, true));
T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
T::regs().cr().modify(|reg| reg.set_adstart(true));
while !T::regs().isr().read().eoc() {
// spin
}
let value = T::regs().dr().read().0 as u16;
// A.7.3 ADC disable code example
T::regs().cr().modify(|reg| reg.set_adstp(true));
while T::regs().cr().read().adstp() {
// spin
}
T::regs().cr().modify(|reg| reg.set_addis(true));
while T::regs().cr().read().aden() {
// spin
}
value
}
}

11
embassy-stm32/src/dma/gpdma.rs
View File

@ -190,6 +190,10 @@ mod low_level_api {
fence(Ordering::SeqCst);
let ch = dma.ch(channel_number as _);
// Reset ch
ch.cr().write(|w| w.set_reset(true));
ch.llr().write(|_| {}); // no linked list
ch.tr1().write(|w| {
w.set_sdw(data_size.into());
@ -252,7 +256,7 @@ mod low_level_api {
/// Gets the running status of the channel
pub unsafe fn is_running(dma: Gpdma, ch: u8) -> bool {
let ch = dma.ch(ch as _);
!ch.sr().read().idlef()
!ch.sr().read().tcf()
}
/// Gets the total remaining transfers for the channel
@ -291,7 +295,10 @@ mod low_level_api {
}
if sr.suspf() || sr.tcf() {
ch.cr().write(|w| w.set_reset(true));
// disable all xxIEs to prevent the irq from firing again.
ch.cr().write(|_| {});
// Wake the future. It'll look at tcf and see it's set.
STATE.channels[state_index].waker.wake();
}
}

25
embassy-stm32/src/eth/v2/mod.rs
View File

@ -9,7 +9,7 @@ pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
use super::*;
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::{AnyPin, Speed};
use crate::pac::{ETH, RCC, SYSCFG};
use crate::pac::ETH;
use crate::Peripheral;
const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
@ -60,16 +60,33 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
unsafe {
// Enable the necessary Clocks
// NOTE(unsafe) We have exclusive access to the registers
#[cfg(not(rcc_h5))]
critical_section::with(|_| {
RCC.apb4enr().modify(|w| w.set_syscfgen(true));
RCC.ahb1enr().modify(|w| {
crate::pac::RCC.apb4enr().modify(|w| w.set_syscfgen(true));
crate::pac::RCC.ahb1enr().modify(|w| {
w.set_eth1macen(true);
w.set_eth1txen(true);
w.set_eth1rxen(true);
});
// RMII
SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
});
#[cfg(rcc_h5)]
critical_section::with(|_| {
crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
crate::pac::RCC.ahb1enr().modify(|w| {
w.set_ethen(true);
w.set_ethtxen(true);
w.set_ethrxen(true);
});
// RMII
crate::pac::SBS
.pmcr()
.modify(|w| w.set_eth_sel_phy(crate::pac::sbs::vals::EthSelPhy::B_0X4));
});
config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);

18
embassy-stm32/src/exti.rs
View File

@ -25,11 +25,11 @@ fn cpu_regs() -> pac::exti::Exti {
EXTI
}
#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
fn exticr_regs() -> pac::syscfg::Syscfg {
pac::SYSCFG
}
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
fn exticr_regs() -> pac::exti::Exti {
EXTI
}
@ -39,9 +39,9 @@ fn exticr_regs() -> pac::afio::Afio {
}
pub unsafe fn on_irq() {
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
let bits = EXTI.pr(0).read().0;
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
// Mask all the channels that fired.
@ -53,9 +53,9 @@ pub unsafe fn on_irq() {
}
// Clear pending
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
EXTI.pr(0).write_value(Lines(bits));
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
{
EXTI.rpr(0).write_value(Lines(bits));
EXTI.fpr(0).write_value(Lines(bits));
@ -213,9 +213,9 @@ impl<'a> ExtiInputFuture<'a> {
EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
// clear pending bit
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5)))]
#[cfg(not(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50)))]
EXTI.pr(0).write(|w| w.set_line(pin, true));
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5))]
#[cfg(any(exti_c0, exti_g0, exti_l5, exti_u5, exti_h5, exti_h50))]
{
EXTI.rpr(0).write(|w| w.set_line(pin, true));
EXTI.fpr(0).write(|w| w.set_line(pin, true));
@ -364,7 +364,7 @@ pub(crate) unsafe fn init() {
foreach_exti_irq!(enable_irq);
#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1)))]
#[cfg(not(any(rcc_wb, rcc_wl5, rcc_wle, stm32f1, exti_h5, exti_h50)))]
<crate::peripherals::SYSCFG as crate::rcc::sealed::RccPeripheral>::enable();
#[cfg(stm32f1)]
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable();

211
embassy-stm32/src/flash/common.rs Normal file
View File

@ -0,0 +1,211 @@
use atomic_polyfill::{fence, Ordering};
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use super::{family, Error, FlashLayout, FlashRegion, FlashSector, FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
use crate::flash::FlashBank;
use crate::Peripheral;
pub struct Flash<'d> {
inner: PeripheralRef<'d, crate::peripherals::FLASH>,
}
impl<'d> Flash<'d> {
pub fn new(p: impl Peripheral<P = crate::peripherals::FLASH> + 'd) -> Self {
into_ref!(p);
Self { inner: p }
}
pub fn into_regions(self) -> FlashLayout<'d> {
FlashLayout::new(self.release())
}
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
blocking_read(FLASH_BASE as u32, FLASH_SIZE as u32, offset, bytes)
}
pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
unsafe { blocking_write(FLASH_BASE as u32, FLASH_SIZE as u32, offset, bytes) }
}
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
unsafe { blocking_erase(FLASH_BASE as u32, from, to) }
}
pub(crate) fn release(self) -> PeripheralRef<'d, crate::peripherals::FLASH> {
let mut flash = self;
unsafe { flash.inner.clone_unchecked() }
}
}
fn blocking_read(base: u32, size: u32, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
if offset + bytes.len() as u32 > size {
return Err(Error::Size);
}
let start_address = base + offset;
let flash_data = unsafe { core::slice::from_raw_parts(start_address as *const u8, bytes.len()) };
bytes.copy_from_slice(flash_data);
Ok(())
}
unsafe fn blocking_write(base: u32, size: u32, offset: u32, bytes: &[u8]) -> Result<(), Error> {
if offset + bytes.len() as u32 > size {
return Err(Error::Size);
}
if offset % WRITE_SIZE as u32 != 0 || bytes.len() % WRITE_SIZE != 0 {
return Err(Error::Unaligned);
}
let mut address = base + offset;
trace!("Writing {} bytes at 0x{:x}", bytes.len(), address);
for chunk in bytes.chunks(WRITE_SIZE) {
critical_section::with(|_| {
family::clear_all_err();
fence(Ordering::SeqCst);
family::unlock();
fence(Ordering::SeqCst);
family::begin_write();
fence(Ordering::SeqCst);
let _on_drop = OnDrop::new(|| {
family::end_write();
fence(Ordering::SeqCst);
family::lock();
});
family::blocking_write(address, chunk.try_into().unwrap())
})?;
address += WRITE_SIZE as u32;
}
Ok(())
}
unsafe fn blocking_erase(base: u32, from: u32, to: u32) -> Result<(), Error> {
let start_address = base + from;
let end_address = base + to;
let regions = family::get_flash_regions();
// Test if the address range is aligned at sector base addresses
let mut address = start_address;
while address < end_address {
let sector = get_sector(address, regions);
if sector.start != address {
return Err(Error::Unaligned);
}
address += sector.size;
}
if address != end_address {
return Err(Error::Unaligned);
}
trace!("Erasing from 0x{:x} to 0x{:x}", start_address, end_address);
let mut address = start_address;
while address < end_address {
let sector = get_sector(address, regions);
trace!("Erasing sector: {:?}", sector);
critical_section::with(|_| {
family::clear_all_err();
fence(Ordering::SeqCst);
family::unlock();
fence(Ordering::SeqCst);
let _on_drop = OnDrop::new(|| {
family::lock();
});
family::blocking_erase_sector(&sector)
})?;
address += sector.size;
}
Ok(())
}
pub(crate) fn get_sector(address: u32, regions: &[&FlashRegion]) -> FlashSector {
let mut current_bank = FlashBank::Bank1;
let mut bank_offset = 0;
for region in regions {
if region.bank != current_bank {
current_bank = region.bank;
bank_offset = 0;
}
if address < region.end() {
let index_in_region = (address - region.base) / region.erase_size;
return FlashSector {
bank: region.bank,
index_in_bank: bank_offset + index_in_region as u8,
start: region.base + index_in_region * region.erase_size,
size: region.erase_size,
};
}
bank_offset += region.sectors();
}
panic!("Flash sector not found");
}
impl FlashRegion {
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
blocking_read(self.base, self.size, offset, bytes)
}
pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
unsafe { blocking_write(self.base, self.size, offset, bytes) }
}
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
unsafe { blocking_erase(self.base, from, to) }
}
}
foreach_flash_region! {
($type_name:ident, $write_size:literal, $erase_size:literal) => {
impl crate::_generated::flash_regions::$type_name<'_> {
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
blocking_read(self.0.base, self.0.size, offset, bytes)
}
pub fn blocking_write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
unsafe { blocking_write(self.0.base, self.0.size, offset, bytes) }
}
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
unsafe { blocking_erase(self.0.base, from, to) }
}
}
impl embedded_storage::nor_flash::ErrorType for crate::_generated::flash_regions::$type_name<'_> {
type Error = Error;
}
impl embedded_storage::nor_flash::ReadNorFlash for crate::_generated::flash_regions::$type_name<'_> {
const READ_SIZE: usize = 1;
fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(offset, bytes)
}
fn capacity(&self) -> usize {
self.0.size as usize
}
}
impl embedded_storage::nor_flash::NorFlash for crate::_generated::flash_regions::$type_name<'_> {
const WRITE_SIZE: usize = $write_size;
const ERASE_SIZE: usize = $erase_size;
fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(offset, bytes)
}
fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
self.blocking_erase(from, to)
}
}
};
}

96
embassy-stm32/src/flash/f3.rs
View File

@ -1,9 +1,16 @@
use core::convert::TryInto;
use core::ptr::write_volatile;
use atomic_polyfill::{fence, Ordering};
use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
pac::FLASH.cr().modify(|w| w.set_lock(true));
}
@ -13,58 +20,55 @@ pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_fkeyr(0xCDEF_89AB));
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
pub(crate) unsafe fn begin_write() {
assert_eq!(0, WRITE_SIZE % 2);
pac::FLASH.cr().write(|w| w.set_pg(true));
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
for chunk in buf.chunks(2) {
write_volatile(offset as *mut u16, u16::from_le_bytes(chunk[0..2].try_into().unwrap()));
offset += chunk.len() as u32;
ret = blocking_wait_ready();
if ret.is_err() {
break;
}
}
ret
};
pac::FLASH.cr().write(|w| w.set_pg(false));
ret
}
pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
for page in (from..to).step_by(super::ERASE_SIZE) {
pac::FLASH.cr().modify(|w| {
w.set_per(true);
});
pub(crate) unsafe fn end_write() {
pac::FLASH.cr().write(|w| w.set_pg(false));
}
pac::FLASH.ar().write(|w| w.set_far(page));
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
let mut address = start_address;
for chunk in buf.chunks(2) {
write_volatile(address as *mut u16, u16::from_le_bytes(chunk.try_into().unwrap()));
address += chunk.len() as u32;
pac::FLASH.cr().modify(|w| {
w.set_strt(true);
});
let mut ret: Result<(), Error> = blocking_wait_ready();
if !pac::FLASH.sr().read().eop() {
trace!("FLASH: EOP not set");
ret = Err(Error::Prog);
} else {
pac::FLASH.sr().write(|w| w.set_eop(true));
}
pac::FLASH.cr().modify(|w| w.set_per(false));
clear_all_err();
if ret.is_err() {
return ret;
}
// prevents parallelism errors
fence(Ordering::SeqCst);
}
blocking_wait_ready()
}
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
pac::FLASH.cr().modify(|w| {
w.set_per(true);
});
pac::FLASH.ar().write(|w| w.set_far(sector.start));
pac::FLASH.cr().modify(|w| {
w.set_strt(true);
});
let mut ret: Result<(), Error> = blocking_wait_ready();
if !pac::FLASH.sr().read().eop() {
trace!("FLASH: EOP not set");
ret = Err(Error::Prog);
} else {
pac::FLASH.sr().write(|w| w.set_eop(true));
}
pac::FLASH.cr().modify(|w| w.set_per(false));
clear_all_err();
if ret.is_err() {
return ret;
}
Ok(())
}
@ -82,7 +86,7 @@ pub(crate) unsafe fn clear_all_err() {
});
}
pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.sr().read();

277
embassy-stm32/src/flash/f4.rs
View File

@ -2,27 +2,108 @@ use core::convert::TryInto;
use core::ptr::write_volatile;
use core::sync::atomic::{fence, Ordering};
use super::{ERASE_SIZE, FLASH_BASE, FLASH_SIZE};
use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
const SECOND_BANK_SECTOR_START: u32 = 12;
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
mod alt_regions {
use embassy_hal_common::PeripheralRef;
use stm32_metapac::FLASH_SIZE;
unsafe fn is_dual_bank() -> bool {
match FLASH_SIZE / 1024 {
// 1 MB devices depend on configuration
1024 => {
if cfg!(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479)) {
pac::FLASH.optcr().read().db1m()
} else {
false
use crate::_generated::flash_regions::{BANK1_REGION1, BANK1_REGION2, BANK1_REGION3};
use crate::flash::{Bank1Region1, Bank1Region2, Flash, FlashBank, FlashRegion};
use crate::peripherals::FLASH;
pub const ALT_BANK1_REGION3: FlashRegion = FlashRegion {
size: 3 * BANK1_REGION3.erase_size,
..BANK1_REGION3
};
pub const ALT_BANK2_REGION1: FlashRegion = FlashRegion {
bank: FlashBank::Bank2,
base: BANK1_REGION1.base + FLASH_SIZE as u32 / 2,
..BANK1_REGION1
};
pub const ALT_BANK2_REGION2: FlashRegion = FlashRegion {
bank: FlashBank::Bank2,
base: BANK1_REGION2.base + FLASH_SIZE as u32 / 2,
..BANK1_REGION2
};
pub const ALT_BANK2_REGION3: FlashRegion = FlashRegion {
bank: FlashBank::Bank2,
base: BANK1_REGION3.base + FLASH_SIZE as u32 / 2,
size: 3 * BANK1_REGION3.erase_size,
..BANK1_REGION3
};
pub const ALT_FLASH_REGIONS: [&FlashRegion; 6] = [
&BANK1_REGION1,
&BANK1_REGION2,
&ALT_BANK1_REGION3,
&ALT_BANK2_REGION1,
&ALT_BANK2_REGION2,
&ALT_BANK2_REGION3,
];
pub type AltBank1Region1<'d> = Bank1Region1<'d>;
pub type AltBank1Region2<'d> = Bank1Region2<'d>;
pub struct AltBank1Region3<'d>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>);
pub struct AltBank2Region1<'d>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>);
pub struct AltBank2Region2<'d>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>);
pub struct AltBank2Region3<'d>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>);
pub struct AltFlashLayout<'d> {
pub bank1_region1: AltBank1Region1<'d>,
pub bank1_region2: AltBank1Region2<'d>,
pub bank1_region3: AltBank1Region3<'d>,
pub bank2_region1: AltBank2Region1<'d>,
pub bank2_region2: AltBank2Region2<'d>,
pub bank2_region3: AltBank2Region3<'d>,
}
impl<'d> Flash<'d> {
pub fn into_alt_regions(self) -> AltFlashLayout<'d> {
unsafe { crate::pac::FLASH.optcr().modify(|r| r.set_db1m(true)) };
// SAFETY: We never expose the cloned peripheral references, and their instance is not public.
// Also, all flash region operations are protected with a cs.
let mut p = self.release();
AltFlashLayout {
bank1_region1: Bank1Region1(&BANK1_REGION1, unsafe { p.clone_unchecked() }),
bank1_region2: Bank1Region2(&BANK1_REGION2, unsafe { p.clone_unchecked() }),
bank1_region3: AltBank1Region3(&ALT_BANK1_REGION3, unsafe { p.clone_unchecked() }),
bank2_region1: AltBank2Region1(&ALT_BANK2_REGION1, unsafe { p.clone_unchecked() }),
bank2_region2: AltBank2Region2(&ALT_BANK2_REGION2, unsafe { p.clone_unchecked() }),
bank2_region3: AltBank2Region3(&ALT_BANK2_REGION3, unsafe { p.clone_unchecked() }),
}
}
// 2 MB devices are always dual bank
2048 => true,
// All other devices are single bank
_ => false,
}
impl Drop for AltFlashLayout<'_> {
fn drop(&mut self) {
unsafe {
super::lock();
crate::pac::FLASH.optcr().modify(|r| r.set_db1m(false))
};
}
}
}
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
pub use alt_regions::{AltFlashLayout, ALT_FLASH_REGIONS};
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
if unsafe { pac::FLASH.optcr().read().db1m() } {
&ALT_FLASH_REGIONS
} else {
&FLASH_REGIONS
}
}
#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479)))]
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
@ -34,93 +115,34 @@ pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
pub(crate) unsafe fn begin_write() {
assert_eq!(0, WRITE_SIZE % 4);
pac::FLASH.cr().write(|w| {
w.set_pg(true);
w.set_psize(pac::flash::vals::Psize::PSIZE32);
});
}
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
// prevents parallelism errors
fence(Ordering::SeqCst);
}
ret = blocking_wait_ready();
if ret.is_err() {
break;
}
}
ret
};
pub(crate) unsafe fn end_write() {
pac::FLASH.cr().write(|w| w.set_pg(false));
ret
}
struct FlashSector {
index: u8,
size: u32,
}
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
let mut address = start_address;
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
address += val.len() as u32;
fn get_sector(addr: u32, dual_bank: bool) -> FlashSector {
let offset = addr - FLASH_BASE as u32;
let bank_size = match dual_bank {
true => FLASH_SIZE / 2,
false => FLASH_SIZE,
} as u32;
let bank = offset / bank_size;
let offset_in_bank = offset % bank_size;
let index_in_bank = if offset_in_bank >= ERASE_SIZE as u32 / 2 {
4 + offset_in_bank / ERASE_SIZE as u32
} else {
offset_in_bank / (ERASE_SIZE as u32 / 8)
};
// First 4 sectors are 16KB, then one 64KB, and rest are 128KB
let size = match index_in_bank {
0..=3 => 16 * 1024,
4 => 64 * 1024,
_ => 128 * 1024,
};
let index = if bank == 1 {
SECOND_BANK_SECTOR_START + index_in_bank
} else {
index_in_bank
} as u8;
FlashSector { index, size }
}
pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
let mut addr = from;
let dual_bank = is_dual_bank();
while addr < to {
let sector = get_sector(addr, dual_bank);
erase_sector(sector.index)?;
addr += sector.size;
// prevents parallelism errors
fence(Ordering::SeqCst);
}
Ok(())
blocking_wait_ready()
}
unsafe fn erase_sector(sector: u8) -> Result<(), Error> {
let bank = sector / SECOND_BANK_SECTOR_START as u8;
let snb = (bank << 4) + (sector % SECOND_BANK_SECTOR_START as u8);
trace!("Erasing sector: {}", sector);
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
let snb = ((sector.bank as u8) << 4) + sector.index_in_bank;
pac::FLASH.cr().modify(|w| {
w.set_ser(true);
@ -148,7 +170,7 @@ pub(crate) unsafe fn clear_all_err() {
});
}
pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.sr().read();
@ -173,3 +195,80 @@ pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
}
}
}
#[cfg(test)]
mod tests {
use super::*;
use crate::flash::{get_sector, FlashBank};
#[test]
#[cfg(stm32f429)]
fn can_get_sector_single_bank() {
const SMALL_SECTOR_SIZE: u32 = 16 * 1024;
const MEDIUM_SECTOR_SIZE: u32 = 64 * 1024;
const LARGE_SECTOR_SIZE: u32 = 128 * 1024;
let assert_sector = |index_in_bank: u8, start: u32, size: u32, address: u32| {
assert_eq!(
FlashSector {
bank: FlashBank::Bank1,
index_in_bank,
start,
size
},
get_sector(address, &FLASH_REGIONS)
)
};
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
assert_sector(11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
assert_sector(11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
let assert_sector = |bank: FlashBank, index_in_bank: u8, start: u32, size: u32, address: u32| {
assert_eq!(
FlashSector {
bank,
index_in_bank,
start,
size
},
get_sector(address, &ALT_FLASH_REGIONS)
)
};
assert_sector(FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
assert_sector(FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
assert_sector(FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
assert_sector(FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
assert_sector(FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
assert_sector(FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
assert_sector(FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
assert_sector(FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
assert_sector(FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0806_0000);
assert_sector(FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
assert_sector(FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_0000);
assert_sector(FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_3FFF);
assert_sector(FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_C000);
assert_sector(FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_FFFF);
assert_sector(FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_0000);
assert_sector(FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_FFFF);
assert_sector(FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080A_0000);
assert_sector(FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080B_FFFF);
assert_sector(FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
assert_sector(FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
}
}

139
embassy-stm32/src/flash/f7.rs
View File

@ -2,9 +2,14 @@ use core::convert::TryInto;
use core::ptr::write_volatile;
use core::sync::atomic::{fence, Ordering};
use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
pac::FLASH.cr().modify(|w| w.set_lock(true));
}
@ -14,64 +19,36 @@ pub(crate) unsafe fn unlock() {
pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
pub(crate) unsafe fn begin_write() {
assert_eq!(0, WRITE_SIZE % 4);
pac::FLASH.cr().write(|w| {
w.set_pg(true);
w.set_psize(pac::flash::vals::Psize::PSIZE32);
});
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
// prevents parallelism errors
fence(Ordering::SeqCst);
}
ret = blocking_wait_ready();
if ret.is_err() {
break;
}
}
ret
};
pac::FLASH.cr().write(|w| w.set_pg(false));
ret
}
pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
let start_sector = if from >= (super::FLASH_BASE + super::ERASE_SIZE / 2) as u32 {
4 + (from - super::FLASH_BASE as u32) / super::ERASE_SIZE as u32
} else {
(from - super::FLASH_BASE as u32) / (super::ERASE_SIZE as u32 / 8)
};
pub(crate) unsafe fn end_write() {
pac::FLASH.cr().write(|w| w.set_pg(false));
}
let end_sector = if to >= (super::FLASH_BASE + super::ERASE_SIZE / 2) as u32 {
4 + (to - super::FLASH_BASE as u32) / super::ERASE_SIZE as u32
} else {
(to - super::FLASH_BASE as u32) / (super::ERASE_SIZE as u32 / 8)
};
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
let mut address = start_address;
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
address += val.len() as u32;
for sector in start_sector..end_sector {
let ret = erase_sector(sector as u8);
if ret.is_err() {
return ret;
}
// prevents parallelism errors
fence(Ordering::SeqCst);
}
Ok(())
blocking_wait_ready()
}
unsafe fn erase_sector(sector: u8) -> Result<(), Error> {
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
pac::FLASH.cr().modify(|w| {
w.set_ser(true);
w.set_snb(sector)
w.set_snb(sector.index_in_bank)
});
pac::FLASH.cr().modify(|w| {
@ -107,7 +84,7 @@ pub(crate) unsafe fn clear_all_err() {
});
}
pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.sr().read();
@ -132,3 +109,75 @@ pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
}
}
}
#[cfg(test)]
mod tests {
use super::*;
use crate::flash::{get_sector, FlashBank};
#[test]
#[cfg(stm32f732)]
fn can_get_sector() {
const SMALL_SECTOR_SIZE: u32 = 16 * 1024;
const MEDIUM_SECTOR_SIZE: u32 = 64 * 1024;
const LARGE_SECTOR_SIZE: u32 = 128 * 1024;
let assert_sector = |index_in_bank: u8, start: u32, size: u32, address: u32| {
assert_eq!(
FlashSector {
bank: FlashBank::Bank1,
index_in_bank,
start,
size
},
get_sector(address, &FLASH_REGIONS)
)
};
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
assert_sector(7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0806_0000);
assert_sector(7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
}
#[test]
#[cfg(stm32f769)]
fn can_get_sector() {
const SMALL_SECTOR_SIZE: u32 = 32 * 1024;
const MEDIUM_SECTOR_SIZE: u32 = 128 * 1024;
const LARGE_SECTOR_SIZE: u32 = 256 * 1024;
let assert_sector = |index_in_bank: u8, start: u32, size: u32, address: u32| {
assert_eq!(
FlashSector {
bank: FlashBank::Bank1,
index_in_bank,
start,
size
},
get_sector(address, &FLASH_REGIONS)
)
};
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_7FFF);
assert_sector(3, 0x0801_8000, SMALL_SECTOR_SIZE, 0x0801_8000);
assert_sector(3, 0x0801_8000, SMALL_SECTOR_SIZE, 0x0801_FFFF);
assert_sector(4, 0x0802_0000, MEDIUM_SECTOR_SIZE, 0x0802_0000);
assert_sector(4, 0x0802_0000, MEDIUM_SECTOR_SIZE, 0x0803_FFFF);
assert_sector(5, 0x0804_0000, LARGE_SECTOR_SIZE, 0x0804_0000);
assert_sector(5, 0x0804_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
assert_sector(7, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080C_0000);
assert_sector(7, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
}
}

95
embassy-stm32/src/flash/h7.rs
View File

@ -1,13 +1,18 @@
use core::convert::TryInto;
use core::ptr::write_volatile;
use atomic_polyfill::{fence, Ordering};
use super::{FlashRegion, FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
const SECOND_BANK_OFFSET: usize = 0x0010_0000;
const fn is_dual_bank() -> bool {
super::FLASH_SIZE / 2 > super::ERASE_SIZE
FLASH_REGIONS.len() == 2
}
pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
@ -20,90 +25,64 @@ pub(crate) unsafe fn lock() {
pub(crate) unsafe fn unlock() {
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
if is_dual_bank() {
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
}
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
let bank = if !is_dual_bank() || (offset - super::FLASH_BASE as u32) < SECOND_BANK_OFFSET as u32 {
pub(crate) unsafe fn begin_write() {
assert_eq!(0, WRITE_SIZE % 4);
}
pub(crate) unsafe fn end_write() {}
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
// We cannot have the write setup sequence in begin_write as it depends on the address
let bank = if start_address < BANK1_REGION.end() {
pac::FLASH.bank(0)
} else {
pac::FLASH.bank(1)
};
bank.cr().write(|w| {
w.set_pg(true);
w.set_psize(2); // 32 bits at once
});
cortex_m::asm::isb();
cortex_m::asm::dsb();
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
fence(Ordering::SeqCst);
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
'outer: for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
trace!("Writing at {:x}", offset);
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
let mut res = None;
let mut address = start_address;
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
address += val.len() as u32;
ret = blocking_wait_ready(bank);
bank.sr().modify(|w| {
if w.eop() {
w.set_eop(true);
}
});
if ret.is_err() {
break 'outer;
}
res = Some(blocking_wait_ready(bank));
bank.sr().modify(|w| {
if w.eop() {
w.set_eop(true);
}
});
if res.unwrap().is_err() {
break;
}
ret
};
}
bank.cr().write(|w| w.set_pg(false));
cortex_m::asm::isb();
cortex_m::asm::dsb();
core::sync::atomic::fence(core::sync::atomic::Ordering::SeqCst);
fence(Ordering::SeqCst);
ret
res.unwrap()
}
pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
let from = from - super::FLASH_BASE as u32;
let to = to - super::FLASH_BASE as u32;
let (start, end) = if to <= super::FLASH_SIZE as u32 {
let start_sector = from / super::ERASE_SIZE as u32;
let end_sector = to / super::ERASE_SIZE as u32;
(start_sector, end_sector)
} else {
error!("Attempting to write outside of defined sectors {:x} {:x}", from, to);
return Err(Error::Unaligned);
};
trace!("Erasing sectors from {} to {}", start, end);
for sector in start..end {
let bank = if sector >= 8 { 1 } else { 0 };
let ret = erase_sector(pac::FLASH.bank(bank), (sector % 8) as u8);
if ret.is_err() {
return ret;
}
}
Ok(())
}
unsafe fn erase_sector(bank: pac::flash::Bank, sector: u8) -> Result<(), Error> {
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
let bank = pac::FLASH.bank(sector.bank as usize);
bank.cr().modify(|w| {
w.set_ser(true);
w.set_snb(sector)
w.set_snb(sector.index_in_bank)
});
bank.cr().modify(|w| {
@ -160,7 +139,7 @@ unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
});
}
pub(crate) unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
loop {
let sr = bank.sr().read();

139
embassy-stm32/src/flash/l.rs
View File

@ -1,9 +1,15 @@
use core::convert::TryInto;
use core::ptr::write_volatile;
use atomic_polyfill::{fence, Ordering};
use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
use crate::flash::Error;
use crate::pac;
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().modify(|w| w.set_lock(true));
@ -33,82 +39,75 @@ pub(crate) unsafe fn unlock() {
}
}
pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error> {
pub(crate) unsafe fn begin_write() {
assert_eq!(0, WRITE_SIZE % 4);
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().write(|w| w.set_pg(true));
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
for chunk in buf.chunks(super::WRITE_SIZE) {
for val in chunk.chunks(4) {
write_volatile(offset as *mut u32, u32::from_le_bytes(val[0..4].try_into().unwrap()));
offset += val.len() as u32;
}
ret = blocking_wait_ready();
if ret.is_err() {
break;
}
}
ret
};
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().write(|w| w.set_pg(false));
ret
}
pub(crate) unsafe fn blocking_erase(from: u32, to: u32) -> Result<(), Error> {
for page in (from..to).step_by(super::ERASE_SIZE) {
#[cfg(any(flash_l0, flash_l1))]
{
pac::FLASH.pecr().modify(|w| {
w.set_erase(true);
w.set_prog(true);
});
pub(crate) unsafe fn end_write() {
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().write(|w| w.set_pg(false));
}
write_volatile(page as *mut u32, 0xFFFFFFFF);
}
pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
let mut address = start_address;
for val in buf.chunks(4) {
write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
address += val.len() as u32;
#[cfg(any(flash_wl, flash_wb, flash_l4))]
{
let idx = (page - super::FLASH_BASE as u32) / super::ERASE_SIZE as u32;
#[cfg(flash_l4)]
let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
pac::FLASH.cr().modify(|w| {
w.set_per(true);
w.set_pnb(idx as u8);
#[cfg(any(flash_wl, flash_wb))]
w.set_strt(true);
#[cfg(any(flash_l4))]
w.set_start(true);
#[cfg(any(flash_l4))]
w.set_bker(bank);
});
}
let ret: Result<(), Error> = blocking_wait_ready();
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().modify(|w| w.set_per(false));
#[cfg(any(flash_l0, flash_l1))]
pac::FLASH.pecr().modify(|w| {
w.set_erase(false);
w.set_prog(false);
});
clear_all_err();
if ret.is_err() {
return ret;
}
// prevents parallelism errors
fence(Ordering::SeqCst);
}
Ok(())
blocking_wait_ready()
}
pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
#[cfg(any(flash_l0, flash_l1))]
{
pac::FLASH.pecr().modify(|w| {
w.set_erase(true);
w.set_prog(true);
});
write_volatile(sector.start as *mut u32, 0xFFFFFFFF);
}
#[cfg(any(flash_wl, flash_wb, flash_l4))]
{
let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
#[cfg(flash_l4)]
let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
pac::FLASH.cr().modify(|w| {
w.set_per(true);
w.set_pnb(idx as u8);
#[cfg(any(flash_wl, flash_wb))]
w.set_strt(true);
#[cfg(any(flash_l4))]
w.set_start(true);
#[cfg(any(flash_l4))]
w.set_bker(bank);
});
}
let ret: Result<(), Error> = blocking_wait_ready();
#[cfg(any(flash_wl, flash_wb, flash_l4))]
pac::FLASH.cr().modify(|w| w.set_per(false));
#[cfg(any(flash_l0, flash_l1))]
pac::FLASH.pecr().modify(|w| {
w.set_erase(false);
w.set_prog(false);
});
clear_all_err();
ret
}
pub(crate) unsafe fn clear_all_err() {
@ -149,7 +148,7 @@ pub(crate) unsafe fn clear_all_err() {
});
}
pub(crate) unsafe fn blocking_wait_ready() -> Result<(), Error> {
unsafe fn blocking_wait_ready() -> Result<(), Error> {
loop {
let sr = pac::FLASH.sr().read();

163
embassy-stm32/src/flash/mod.rs
View File

@ -1,89 +1,67 @@
use embassy_hal_common::{into_ref, PeripheralRef};
use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
pub use crate::pac::{ERASE_SIZE, ERASE_VALUE, FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
use crate::peripherals::FLASH;
use crate::Peripheral;
const FLASH_END: usize = FLASH_BASE + FLASH_SIZE;
#[cfg(flash)]
mod common;
#[cfg_attr(any(flash_wl, flash_wb, flash_l0, flash_l1, flash_l4), path = "l.rs")]
#[cfg(flash)]
pub use common::*;
pub use crate::_generated::flash_regions::*;
pub use crate::pac::{FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct FlashRegion {
pub bank: FlashBank,
pub base: u32,
pub size: u32,
pub erase_size: u32,
pub write_size: u32,
pub erase_value: u8,
}
#[derive(Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct FlashSector {
pub bank: FlashBank,
pub index_in_bank: u8,
pub start: u32,
pub size: u32,
}
#[derive(Clone, Copy, Debug, PartialEq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FlashBank {
Bank1 = 0,
Bank2 = 1,
Otp,
}
impl FlashRegion {
pub const fn end(&self) -> u32 {
self.base + self.size
}
pub const fn sectors(&self) -> u8 {
(self.size / self.erase_size) as u8
}
}
#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_wl, flash_wb), path = "l.rs")]
#[cfg_attr(flash_f3, path = "f3.rs")]
#[cfg_attr(flash_f4, path = "f4.rs")]
#[cfg_attr(flash_f7, path = "f7.rs")]
#[cfg_attr(flash_h7, path = "h7.rs")]
#[cfg_attr(
not(any(
flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f3, flash_f4, flash_f7, flash_h7
)),
path = "other.rs"
)]
mod family;
pub struct Flash<'d> {
_inner: PeripheralRef<'d, FLASH>,
}
impl<'d> Flash<'d> {
pub fn new(p: impl Peripheral<P = FLASH> + 'd) -> Self {
into_ref!(p);
Self { _inner: p }
}
pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
let offset = FLASH_BASE as u32 + offset;
if offset as usize >= FLASH_END || offset as usize + bytes.len() > FLASH_END {
return Err(Error::Size);
}
let flash_data = unsafe { core::slice::from_raw_parts(offset as *const u8, bytes.len()) };
bytes.copy_from_slice(flash_data);
Ok(())
}
pub fn blocking_write(&mut self, offset: u32, buf: &[u8]) -> Result<(), Error> {
let offset = FLASH_BASE as u32 + offset;
if offset as usize + buf.len() > FLASH_END {
return Err(Error::Size);
}
if offset as usize % WRITE_SIZE != 0 || buf.len() as usize % WRITE_SIZE != 0 {
return Err(Error::Unaligned);
}
trace!("Writing {} bytes at 0x{:x}", buf.len(), offset);
self.clear_all_err();
unsafe {
family::unlock();
let res = family::blocking_write(offset, buf);
family::lock();
res
}
}
pub fn blocking_erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
let from = FLASH_BASE as u32 + from;
let to = FLASH_BASE as u32 + to;
if to < from || to as usize > FLASH_END {
return Err(Error::Size);
}
if (from as usize % ERASE_SIZE) != 0 || (to as usize % ERASE_SIZE) != 0 {
return Err(Error::Unaligned);
}
self.clear_all_err();
unsafe {
family::unlock();
let res = family::blocking_erase(from, to);
family::lock();
res
}
}
fn clear_all_err(&mut self) {
unsafe { family::clear_all_err() };
}
}
impl Drop for Flash<'_> {
fn drop(&mut self) {
unsafe { family::lock() };
}
}
#[allow(unused_imports)]
pub use family::*;
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
@ -97,10 +75,6 @@ pub enum Error {
Parallelism,
}
impl<'d> ErrorType for Flash<'d> {
type Error = Error;
}
impl NorFlashError for Error {
fn kind(&self) -> NorFlashErrorKind {
match self {
@ -110,28 +84,3 @@ impl NorFlashError for Error {
}
}
}
impl<'d> ReadNorFlash for Flash<'d> {
const READ_SIZE: usize = WRITE_SIZE;
fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(offset, bytes)
}
fn capacity(&self) -> usize {
FLASH_SIZE
}
}
impl<'d> NorFlash for Flash<'d> {
const WRITE_SIZE: usize = WRITE_SIZE;
const ERASE_SIZE: usize = ERASE_SIZE;
fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
self.blocking_erase(from, to)
}
fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(offset, bytes)
}
}

29
embassy-stm32/src/flash/other.rs Normal file
View File

@ -0,0 +1,29 @@
#![allow(unused)]
use super::{Error, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
&FLASH_REGIONS
}
pub(crate) unsafe fn lock() {
unimplemented!();
}
pub(crate) unsafe fn unlock() {
unimplemented!();
}
pub(crate) unsafe fn begin_write() {
unimplemented!();
}
pub(crate) unsafe fn end_write() {
unimplemented!();
}
pub(crate) unsafe fn blocking_write(_start_address: u32, _buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
unimplemented!();
}
pub(crate) unsafe fn blocking_erase_sector(_sector: &FlashSector) -> Result<(), Error> {
unimplemented!();
}
pub(crate) unsafe fn clear_all_err() {
unimplemented!();
}

75
embassy-stm32/src/i2c/timeout.rs
View File

@ -28,64 +28,64 @@ impl<'d, T: Instance, TXDMA, RXDMA> TimeoutI2c<'d, T, TXDMA, RXDMA> {
}
/// Blocking read with a custom timeout
pub fn blocking_read_timeout(&mut self, addr: u8, buffer: &mut [u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_read_timeout(addr, buffer, timeout_fn(timeout))
pub fn blocking_read_timeout(&mut self, addr: u8, read: &mut [u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_read_timeout(addr, read, timeout_fn(timeout))
}
/// Blocking read with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(addr, buffer, self.timeout)
pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(addr, read, self.timeout)
}
/// Blocking write with a custom timeout
pub fn blocking_write_timeout(&mut self, addr: u8, bytes: &[u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_write_timeout(addr, bytes, timeout_fn(timeout))
pub fn blocking_write_timeout(&mut self, addr: u8, write: &[u8], timeout: Duration) -> Result<(), Error> {
self.i2c.blocking_write_timeout(addr, write, timeout_fn(timeout))
}
/// Blocking write with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(addr, bytes, self.timeout)
pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(addr, write, self.timeout)
}
/// Blocking write-read with a custom timeout
pub fn blocking_write_read_timeout(
&mut self,
addr: u8,
bytes: &[u8],
buffer: &mut [u8],
write: &[u8],
read: &mut [u8],
timeout: Duration,
) -> Result<(), Error> {
self.i2c
.blocking_write_read_timeout(addr, bytes, buffer, timeout_fn(timeout))
.blocking_write_read_timeout(addr, write, read, timeout_fn(timeout))
}
/// Blocking write-read with default timeout, provided in [`TimeoutI2c::new()`]
pub fn blocking_write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(addr, bytes, buffer, self.timeout)
pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(addr, write, read, self.timeout)
}
}
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::Read for TimeoutI2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(addr, buffer)
fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(addr, read)
}
}
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::Write for TimeoutI2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(addr, bytes)
fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(addr, write)
}
}
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_02::blocking::i2c::WriteRead for TimeoutI2c<'d, T, TXDMA, RXDMA> {
type Error = Error;
fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(addr, bytes, buffer)
fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(addr, write, read)
}
}
@ -98,45 +98,24 @@ mod eh1 {
}
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::I2c for TimeoutI2c<'d, T, TXDMA, RXDMA> {
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, buffer)
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_iter<B>(&mut self, _address: u8, _bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn write_iter_read<B>(&mut self, _address: u8, _bytes: B, _buffer: &mut [u8]) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
fn transaction<'a>(
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'a>],
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
fn transaction_iter<'a, O>(&mut self, _address: u8, _operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = embedded_hal_1::i2c::Operation<'a>>,
{
todo!();
}
}
}

73
embassy-stm32/src/i2c/v1.rs
View File

@ -307,18 +307,18 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
pub fn blocking_read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(addr, buffer, || Ok(()))
pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(addr, read, || Ok(()))
}
pub fn blocking_write_timeout(
&mut self,
addr: u8,
bytes: &[u8],
write: &[u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
unsafe {
self.write_bytes(addr, bytes, &check_timeout)?;
self.write_bytes(addr, write, &check_timeout)?;
// Send a STOP condition
T::regs().cr1().modify(|reg| reg.set_stop(true));
// Wait for STOP condition to transmit.
@ -331,49 +331,49 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
Ok(())
}
pub fn blocking_write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(addr, bytes, || Ok(()))
pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(addr, write, || Ok(()))
}
pub fn blocking_write_read_timeout(
&mut self,
addr: u8,
bytes: &[u8],
buffer: &mut [u8],
write: &[u8],
read: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
unsafe { self.write_bytes(addr, bytes, &check_timeout)? };
self.blocking_read_timeout(addr, buffer, &check_timeout)?;
unsafe { self.write_bytes(addr, write, &check_timeout)? };
self.blocking_read_timeout(addr, read, &check_timeout)?;
Ok(())
}
pub fn blocking_write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(addr, bytes, buffer, || Ok(()))
pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(addr, write, read, || Ok(()))
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
type Error = Error;
fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(addr, buffer)
fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(addr, read)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
type Error = Error;
fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(addr, bytes)
fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(addr, write)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
type Error = Error;
fn write_read(&mut self, addr: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(addr, bytes, buffer)
fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(addr, write, read)
}
}
@ -402,46 +402,25 @@ mod eh1 {
}
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T> {
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, buffer)
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_iter<B>(&mut self, _address: u8, _bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn write_iter_read<B>(&mut self, _address: u8, _bytes: B, _buffer: &mut [u8]) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
fn transaction<'a>(
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'a>],
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
fn transaction_iter<'a, O>(&mut self, _address: u8, _operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = embedded_hal_1::i2c::Operation<'a>>,
{
todo!();
}
}
}

160
embassy-stm32/src/i2c/v2.rs
View File

@ -262,7 +262,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
if T::regs().isr().read().txis() {
T::regs().txdr().write(|w| w.set_txdata(0));
}
if T::regs().isr().read().txe() {
if !T::regs().isr().read().txe() {
T::regs().isr().modify(|w| w.set_txe(true))
}
}
@ -345,12 +345,12 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
fn read_internal(
&mut self,
address: u8,
buffer: &mut [u8],
read: &mut [u8],
restart: bool,
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
let completed_chunks = buffer.len() / 255;
let total_chunks = if completed_chunks * 255 == buffer.len() {
let completed_chunks = read.len() / 255;
let total_chunks = if completed_chunks * 255 == read.len() {
completed_chunks
} else {
completed_chunks + 1
@ -360,7 +360,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
unsafe {
Self::master_read(
address,
buffer.len().min(255),
read.len().min(255),
Stop::Automatic,
last_chunk_idx != 0,
restart,
@ -368,7 +368,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
)?;
}
for (number, chunk) in buffer.chunks_mut(255).enumerate() {
for (number, chunk) in read.chunks_mut(255).enumerate() {
if number != 0 {
// NOTE(unsafe) We have &mut self
unsafe {
@ -391,12 +391,12 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
fn write_internal(
&mut self,
address: u8,
bytes: &[u8],
write: &[u8],
send_stop: bool,
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
let completed_chunks = bytes.len() / 255;
let total_chunks = if completed_chunks * 255 == bytes.len() {
let completed_chunks = write.len() / 255;
let total_chunks = if completed_chunks * 255 == write.len() {
completed_chunks
} else {
completed_chunks + 1
@ -410,14 +410,14 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
unsafe {
Self::master_write(
address,
bytes.len().min(255),
write.len().min(255),
Stop::Software,
last_chunk_idx != 0,
&check_timeout,
)?;
}
for (number, chunk) in bytes.chunks(255).enumerate() {
for (number, chunk) in write.chunks(255).enumerate() {
if number != 0 {
// NOTE(unsafe) We have &mut self
unsafe {
@ -448,7 +448,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
async fn write_dma_internal(
&mut self,
address: u8,
bytes: &[u8],
write: &[u8],
first_slice: bool,
last_slice: bool,
check_timeout: impl Fn() -> Result<(), Error>,
@ -456,7 +456,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
where
TXDMA: crate::i2c::TxDma<T>,
{
let total_len = bytes.len();
let total_len = write.len();
let completed_chunks = total_len / 255;
let total_chunks = if completed_chunks * 255 == total_len {
completed_chunks
@ -476,7 +476,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
let ch = &mut self.tx_dma;
let request = ch.request();
crate::dma::write(ch, request, bytes, dst)
crate::dma::write(ch, request, write, dst)
};
let state = T::state();
@ -641,25 +641,25 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
// =========================
// Async public API
pub async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error>
pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
if bytes.is_empty() {
self.write_internal(address, bytes, true, || Ok(()))
if write.is_empty() {
self.write_internal(address, write, true, || Ok(()))
} else {
self.write_dma_internal(address, bytes, true, true, || Ok(())).await
self.write_dma_internal(address, write, true, true, || Ok(())).await
}
}
pub async fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error>
pub async fn write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error>
where
TXDMA: crate::i2c::TxDma<T>,
{
if bytes.is_empty() {
if write.is_empty() {
return Err(Error::ZeroLengthTransfer);
}
let mut iter = bytes.iter();
let mut iter = write.iter();
let mut first = true;
let mut current = iter.next();
@ -685,21 +685,21 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
}
}
pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error>
pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error>
where
TXDMA: super::TxDma<T>,
RXDMA: super::RxDma<T>,
{
if bytes.is_empty() {
self.write_internal(address, bytes, false, || Ok(()))?;
if write.is_empty() {
self.write_internal(address, write, false, || Ok(()))?;
} else {
self.write_dma_internal(address, bytes, true, true, || Ok(())).await?;
self.write_dma_internal(address, write, true, true, || Ok(())).await?;
}
if buffer.is_empty() {
self.read_internal(address, buffer, true, || Ok(()))?;
if read.is_empty() {
self.read_internal(address, read, true, || Ok(()))?;
} else {
self.read_dma_internal(address, buffer, true, || Ok(())).await?;
self.read_dma_internal(address, read, true, || Ok(())).await?;
}
Ok(())
@ -711,57 +711,57 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
pub fn blocking_read_timeout(
&mut self,
address: u8,
buffer: &mut [u8],
read: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.read_internal(address, buffer, false, &check_timeout)
self.read_internal(address, read, false, &check_timeout)
// Automatic Stop
}
pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(address, buffer, || Ok(()))
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
self.blocking_read_timeout(address, read, || Ok(()))
}
pub fn blocking_write_timeout(
&mut self,
address: u8,
bytes: &[u8],
write: &[u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.write_internal(address, bytes, true, &check_timeout)
self.write_internal(address, write, true, &check_timeout)
}
pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(address, bytes, || Ok(()))
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
self.blocking_write_timeout(address, write, || Ok(()))
}
pub fn blocking_write_read_timeout(
&mut self,
address: u8,
bytes: &[u8],
buffer: &mut [u8],
write: &[u8],
read: &mut [u8],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
self.write_internal(address, bytes, false, &check_timeout)?;
self.read_internal(address, buffer, true, &check_timeout)
self.write_internal(address, write, false, &check_timeout)?;
self.read_internal(address, read, true, &check_timeout)
// Automatic Stop
}
pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(address, bytes, buffer, || Ok(()))
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
self.blocking_write_read_timeout(address, write, read, || Ok(()))
}
pub fn blocking_write_vectored_timeout(
&mut self,
address: u8,
bytes: &[&[u8]],
write: &[&[u8]],
check_timeout: impl Fn() -> Result<(), Error>,
) -> Result<(), Error> {
if bytes.is_empty() {
if write.is_empty() {
return Err(Error::ZeroLengthTransfer);
}
let first_length = bytes[0].len();
let last_slice_index = bytes.len() - 1;
let first_length = write[0].len();
let last_slice_index = write.len() - 1;
// NOTE(unsafe) We have &mut self
unsafe {
@ -774,7 +774,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
)?;
}
for (idx, slice) in bytes.iter().enumerate() {
for (idx, slice) in write.iter().enumerate() {
let slice_len = slice.len();
let completed_chunks = slice_len / 255;
let total_chunks = if completed_chunks * 255 == slice_len {
@ -828,8 +828,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
Ok(())
}
pub fn blocking_write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error> {
self.blocking_write_vectored_timeout(address, bytes, || Ok(()))
pub fn blocking_write_vectored(&mut self, address: u8, write: &[&[u8]]) -> Result<(), Error> {
self.blocking_write_vectored_timeout(address, write, || Ok(()))
}
}
@ -847,16 +847,16 @@ mod eh02 {
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
type Error = Error;
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, bytes)
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
}
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
type Error = Error;
fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, bytes, buffer)
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
}
}
@ -1010,46 +1010,25 @@ mod eh1 {
}
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, NoDma, NoDma> {
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, buffer)
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_read(address, read)
}
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, buffer)
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.blocking_write(address, write)
}
fn write_iter<B>(&mut self, _address: u8, _bytes: B) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, write, read)
}
fn write_iter_read<B>(&mut self, _address: u8, _bytes: B, _buffer: &mut [u8]) -> Result<(), Self::Error>
where
B: IntoIterator<Item = u8>,
{
todo!();
}
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
self.blocking_write_read(address, wr_buffer, rd_buffer)
}
fn transaction<'a>(
fn transaction(
&mut self,
_address: u8,
_operations: &mut [embedded_hal_1::i2c::Operation<'a>],
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
todo!();
}
fn transaction_iter<'a, O>(&mut self, _address: u8, _operations: O) -> Result<(), Self::Error>
where
O: IntoIterator<Item = embedded_hal_1::i2c::Operation<'a>>,
{
todo!();
}
}
}
@ -1059,27 +1038,22 @@ mod eha {
use super::*;
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
async fn read<'a>(&'a mut self, address: u8, read: &'a mut [u8]) -> Result<(), Self::Error> {
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
self.read(address, read).await
}
async fn write<'a>(&'a mut self, address: u8, write: &'a [u8]) -> Result<(), Self::Error> {
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
self.write(address, write).await
}
async fn write_read<'a>(
&'a mut self,
address: u8,
write: &'a [u8],
read: &'a mut [u8],
) -> Result<(), Self::Error> {
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
self.write_read(address, write, read).await
}
async fn transaction<'a, 'b>(
&'a mut self,
async fn transaction(
&mut self,
address: u8,
operations: &'a mut [embedded_hal_1::i2c::Operation<'b>],
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
) -> Result<(), Self::Error> {
let _ = address;
let _ = operations;

8
embassy-stm32/src/lib.rs
View File

@ -43,9 +43,6 @@ pub mod i2c;
#[cfg(crc)]
pub mod crc;
#[cfg(any(
flash_l0, flash_l1, flash_wl, flash_wb, flash_l4, flash_f3, flash_f4, flash_f7, flash_h7
))]
pub mod flash;
pub mod pwm;
#[cfg(quadspi)]
@ -56,6 +53,8 @@ pub mod rng;
pub mod sdmmc;
#[cfg(spi)]
pub mod spi;
#[cfg(stm32wl)]
pub mod subghz;
#[cfg(usart)]
pub mod usart;
#[cfg(all(usb, feature = "time"))]
@ -65,9 +64,6 @@ pub mod usb_otg;
#[cfg(iwdg)]
pub mod wdg;
#[cfg(feature = "subghz")]
pub mod subghz;
// This must go last, so that it sees all the impl_foo! macros defined earlier.
pub(crate) mod _generated {
#![allow(dead_code)]

124
embassy-stm32/src/pwm/complementary_pwm.rs Normal file
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@ -0,0 +1,124 @@
use core::marker::PhantomData;
use embassy_hal_common::{into_ref, PeripheralRef};
pub use stm32_metapac::timer::vals::Ckd;
use super::simple_pwm::*;
use super::*;
#[allow(unused_imports)]
use crate::gpio::sealed::{AFType, Pin};
use crate::gpio::AnyPin;
use crate::time::Hertz;
use crate::Peripheral;
pub struct ComplementaryPwmPin<'d, Perip, Channel> {
_pin: PeripheralRef<'d, AnyPin>,
phantom: PhantomData<(Perip, Channel)>,
}
macro_rules! complementary_channel_impl {
($new_chx:ident, $channel:ident, $pin_trait:ident, $complementary_pin_trait:ident) => {
impl<'d, Perip: CaptureCompare16bitInstance> ComplementaryPwmPin<'d, Perip, $channel> {
pub fn $new_chx(pin: impl Peripheral<P = impl $complementary_pin_trait<Perip>> + 'd) -> Self {
into_ref!(pin);
critical_section::with(|_| unsafe {
pin.set_low();
pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
#[cfg(gpio_v2)]
pin.set_speed(crate::gpio::Speed::VeryHigh);
});
ComplementaryPwmPin {
_pin: pin.map_into(),
phantom: PhantomData,
}
}
}
};
}
complementary_channel_impl!(new_ch1, Ch1, Channel1Pin, Channel1ComplementaryPin);
complementary_channel_impl!(new_ch2, Ch2, Channel2Pin, Channel2ComplementaryPin);
complementary_channel_impl!(new_ch3, Ch3, Channel3Pin, Channel3ComplementaryPin);
complementary_channel_impl!(new_ch4, Ch4, Channel4Pin, Channel4ComplementaryPin);
pub struct ComplementaryPwm<'d, T> {
inner: PeripheralRef<'d, T>,
}
impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
pub fn new(
tim: impl Peripheral<P = T> + 'd,
_ch1: Option<PwmPin<'d, T, Ch1>>,
_ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
_ch2: Option<PwmPin<'d, T, Ch2>>,
_ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>,
_ch3: Option<PwmPin<'d, T, Ch3>>,
_ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>,
_ch4: Option<PwmPin<'d, T, Ch4>>,
_ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
freq: Hertz,
) -> Self {
Self::new_inner(tim, freq)
}
fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
into_ref!(tim);
T::enable();
<T as crate::rcc::sealed::RccPeripheral>::reset();
let mut this = Self { inner: tim };
this.inner.set_frequency(freq);
this.inner.start();
unsafe {
this.inner.enable_outputs(true);
this.inner
.set_output_compare_mode(Channel::Ch1, OutputCompareMode::PwmMode1);
this.inner
.set_output_compare_mode(Channel::Ch2, OutputCompareMode::PwmMode1);
this.inner
.set_output_compare_mode(Channel::Ch3, OutputCompareMode::PwmMode1);
this.inner
.set_output_compare_mode(Channel::Ch4, OutputCompareMode::PwmMode1);
}
this
}
pub fn enable(&mut self, channel: Channel) {
unsafe {
self.inner.enable_channel(channel, true);
self.inner.enable_complementary_channel(channel, true);
}
}
pub fn disable(&mut self, channel: Channel) {
unsafe {
self.inner.enable_complementary_channel(channel, false);
self.inner.enable_channel(channel, false);
}
}
pub fn set_freq(&mut self, freq: Hertz) {
self.inner.set_frequency(freq);
}
pub fn get_max_duty(&self) -> u16 {
unsafe { self.inner.get_max_compare_value() }
}
pub fn set_duty(&mut self, channel: Channel, duty: u16) {
assert!(duty < self.get_max_duty());
unsafe { self.inner.set_compare_value(channel, duty) }
}
pub fn set_dead_time_clock_division(&mut self, value: Ckd) {
unsafe { self.inner.set_dead_time_clock_division(value) }
}
pub fn set_dead_time_value(&mut self, value: u8) {
unsafe { self.inner.set_dead_time_value(value) }
}
}

40
embassy-stm32/src/pwm/mod.rs
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@ -1,5 +1,8 @@
pub mod complementary_pwm;
pub mod simple_pwm;
use stm32_metapac::timer::vals::Ckd;
#[cfg(feature = "unstable-pac")]
pub mod low_level {
pub use super::sealed::*;
@ -67,6 +70,14 @@ pub(crate) mod sealed {
unsafe fn get_max_compare_value(&self) -> u16;
}
pub trait ComplementaryCaptureCompare16bitInstance: CaptureCompare16bitInstance {
unsafe fn set_dead_time_clock_division(&mut self, value: Ckd);
unsafe fn set_dead_time_value(&mut self, value: u8);
unsafe fn enable_complementary_channel(&mut self, channel: Channel, enable: bool);
}
pub trait CaptureCompare32bitInstance: crate::timer::sealed::GeneralPurpose32bitInstance {
unsafe fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode);
@ -82,6 +93,12 @@ pub trait CaptureCompare16bitInstance:
sealed::CaptureCompare16bitInstance + crate::timer::GeneralPurpose16bitInstance + 'static
{
}
pub trait ComplementaryCaptureCompare16bitInstance:
sealed::ComplementaryCaptureCompare16bitInstance + crate::timer::AdvancedControlInstance + 'static
{
}
pub trait CaptureCompare32bitInstance:
sealed::CaptureCompare32bitInstance + CaptureCompare16bitInstance + crate::timer::GeneralPurpose32bitInstance + 'static
{
@ -209,6 +226,29 @@ foreach_interrupt! {
impl CaptureCompare16bitInstance for crate::peripherals::$inst {
}
impl crate::pwm::sealed::ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {
unsafe fn set_dead_time_clock_division(&mut self, value: Ckd) {
use crate::timer::sealed::AdvancedControlInstance;
Self::regs_advanced().cr1().modify(|w| w.set_ckd(value));
}
unsafe fn set_dead_time_value(&mut self, value: u8) {
use crate::timer::sealed::AdvancedControlInstance;
Self::regs_advanced().bdtr().modify(|w| w.set_dtg(value));
}
unsafe fn enable_complementary_channel(&mut self, channel: Channel, enable: bool) {
use crate::timer::sealed::AdvancedControlInstance;
Self::regs_advanced()
.ccer()
.modify(|w| w.set_ccne(channel.raw(), enable));
}
}
impl ComplementaryCaptureCompare16bitInstance for crate::peripherals::$inst {
}
};
}

606
embassy-stm32/src/rcc/h5.rs Normal file
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@ -0,0 +1,606 @@
use core::marker::PhantomData;
use stm32_metapac::rcc::vals::{Hpre, Ppre, Timpre};
use crate::pac::pwr::vals::Vos;
use crate::pac::rcc::vals::{Hseext, Hsidiv, Mco1, Mco2, Pllrge, Pllsrc, Pllvcosel, Sw};
use crate::pac::{FLASH, PWR, RCC};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::{peripherals, Peripheral};
/// HSI speed
pub const HSI_FREQ: Hertz = Hertz(64_000_000);
/// CSI speed
pub const CSI_FREQ: Hertz = Hertz(4_000_000);
/// HSI48 speed
pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
/// LSI speed
pub const LSI_FREQ: Hertz = Hertz(32_000);
const VCO_MIN: u32 = 150_000_000;
const VCO_MAX: u32 = 420_000_000;
const VCO_WIDE_MIN: u32 = 128_000_000;
const VCO_WIDE_MAX: u32 = 560_000_000;
/// Voltage Scale
///
/// Represents the voltage range feeding the CPU core. The maximum core
/// clock frequency depends on this value.
#[derive(Copy, Clone, PartialEq)]
pub enum VoltageScale {
/// VOS 0 range VCORE 1.30V - 1.40V
Scale0,
/// VOS 1 range VCORE 1.15V - 1.26V
Scale1,
/// VOS 2 range VCORE 1.05V - 1.15V
Scale2,
/// VOS 3 range VCORE 0.95V - 1.05V
Scale3,
}
pub enum HseMode {
/// crystal/ceramic oscillator (HSEBYP=0)
Oscillator,
/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
BypassAnalog,
/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
BypassDigital,
}
pub struct Hse {
/// HSE frequency.
pub freq: Hertz,
/// HSE mode.
pub mode: HseMode,
}
pub enum Hsi {
/// 64Mhz
Mhz64,
/// 32Mhz (divided by 2)
Mhz32,
/// 16Mhz (divided by 4)
Mhz16,
/// 8Mhz (divided by 8)
Mhz8,
}
pub enum Sysclk {
/// HSI selected as sysclk
HSI,
/// HSE selected as sysclk
HSE,
/// CSI selected as sysclk
CSI,
/// PLL1_P selected as sysclk
Pll1P,
}
pub enum PllSource {
Hsi,
Csi,
Hse,
}
pub struct Pll {
/// Source clock selection.
pub source: PllSource,
/// PLL pre-divider (DIVM). Must be between 1 and 63.
pub prediv: u8,
/// PLL multiplication factor. Must be between 4 and 512.
pub mul: u16,
/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
/// On PLL1, it must be even (in particular, it cannot be 1.)
pub divp: Option<u16>,
/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
pub divq: Option<u16>,
/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
pub divr: Option<u16>,
}
/// AHB prescaler
#[derive(Clone, Copy, PartialEq)]
pub enum AHBPrescaler {
NotDivided,
Div2,
Div4,
Div8,
Div16,
Div64,
Div128,
Div256,
Div512,
}
impl AHBPrescaler {
fn div(&self, clk: Hertz) -> Hertz {
match self {
Self::NotDivided => clk,
Self::Div2 => clk / 2u32,
Self::Div4 => clk / 4u32,
Self::Div8 => clk / 8u32,
Self::Div16 => clk / 16u32,
Self::Div64 => clk / 64u32,
Self::Div128 => clk / 128u32,
Self::Div256 => clk / 256u32,
Self::Div512 => clk / 512u32,
}
}
}
/// APB prescaler
#[derive(Clone, Copy)]
pub enum APBPrescaler {
NotDivided,
Div2,
Div4,
Div8,
Div16,
}
impl APBPrescaler {
fn div(&self, clk: Hertz) -> Hertz {
match self {
Self::NotDivided => clk,
Self::Div2 => clk / 2u32,
Self::Div4 => clk / 4u32,
Self::Div8 => clk / 8u32,
Self::Div16 => clk / 16u32,
}
}
fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz {
match (tim, self) {
// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a
// division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2
(TimerPrescaler::DefaultX2, Self::NotDivided) => clk,
(TimerPrescaler::DefaultX2, Self::Div2) => clk,
(TimerPrescaler::DefaultX2, Self::Div4) => clk / 2u32,
(TimerPrescaler::DefaultX2, Self::Div8) => clk / 4u32,
(TimerPrescaler::DefaultX2, Self::Div16) => clk / 8u32,
// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2
// corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
// this makes NO SENSE and is different than in the H7. Mistake in the RM??
(TimerPrescaler::DefaultX4, Self::NotDivided) => clk * 2u32,
(TimerPrescaler::DefaultX4, Self::Div2) => clk,
(TimerPrescaler::DefaultX4, Self::Div4) => clk / 2u32,
(TimerPrescaler::DefaultX4, Self::Div8) => clk / 2u32,
(TimerPrescaler::DefaultX4, Self::Div16) => clk / 4u32,
}
}
}
/// APB prescaler
#[derive(Clone, Copy)]
pub enum TimerPrescaler {
DefaultX2,
DefaultX4,
}
impl From<TimerPrescaler> for Timpre {
fn from(value: TimerPrescaler) -> Self {
match value {
TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2,
TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4,
}
}
}
impl From<APBPrescaler> for Ppre {
fn from(val: APBPrescaler) -> Ppre {
match val {
APBPrescaler::NotDivided => Ppre::DIV1,
APBPrescaler::Div2 => Ppre::DIV2,
APBPrescaler::Div4 => Ppre::DIV4,
APBPrescaler::Div8 => Ppre::DIV8,
APBPrescaler::Div16 => Ppre::DIV16,
}
}
}
impl From<AHBPrescaler> for Hpre {
fn from(val: AHBPrescaler) -> Hpre {
match val {
AHBPrescaler::NotDivided => Hpre::DIV1,
AHBPrescaler::Div2 => Hpre::DIV2,
AHBPrescaler::Div4 => Hpre::DIV4,
AHBPrescaler::Div8 => Hpre::DIV8,
AHBPrescaler::Div16 => Hpre::DIV16,
AHBPrescaler::Div64 => Hpre::DIV64,
AHBPrescaler::Div128 => Hpre::DIV128,
AHBPrescaler::Div256 => Hpre::DIV256,
AHBPrescaler::Div512 => Hpre::DIV512,
}
}
}
/// Configuration of the core clocks
#[non_exhaustive]
pub struct Config {
pub hsi: Option<Hsi>,
pub hse: Option<Hse>,
pub csi: bool,
pub hsi48: bool,
pub sys: Sysclk,
pub pll1: Option<Pll>,
pub pll2: Option<Pll>,
#[cfg(rcc_h5)]
pub pll3: Option<Pll>,
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
pub apb3_pre: APBPrescaler,
pub timer_prescaler: TimerPrescaler,
pub voltage_scale: VoltageScale,
}
impl Default for Config {
fn default() -> Self {
Self {
hsi: Some(Hsi::Mhz64),
hse: None,
csi: false,
hsi48: false,
sys: Sysclk::HSI,
pll1: None,
pll2: None,
#[cfg(rcc_h5)]
pll3: None,
ahb_pre: AHBPrescaler::NotDivided,
apb1_pre: APBPrescaler::NotDivided,
apb2_pre: APBPrescaler::NotDivided,
apb3_pre: APBPrescaler::NotDivided,
timer_prescaler: TimerPrescaler::DefaultX2,
voltage_scale: VoltageScale::Scale3,
}
}
}
pub(crate) mod sealed {
pub trait McoInstance {
type Source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8);
}
}
pub trait McoInstance: sealed::McoInstance + 'static {}
pin_trait!(McoPin, McoInstance);
macro_rules! impl_peri {
($peri:ident, $source:ident, $set_source:ident, $set_prescaler:ident) => {
impl sealed::McoInstance for peripherals::$peri {
type Source = $source;
unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8) {
RCC.cfgr().modify(|w| {
w.$set_source(source);
w.$set_prescaler(prescaler);
});
}
}
impl McoInstance for peripherals::$peri {}
};
}
impl_peri!(MCO1, Mco1, set_mco1, set_mco1pre);
impl_peri!(MCO2, Mco2, set_mco2, set_mco2pre);
pub struct Mco<'d, T: McoInstance> {
phantom: PhantomData<&'d mut T>,
}
impl<'d, T: McoInstance> Mco<'d, T> {
pub fn new(
_peri: impl Peripheral<P = T> + 'd,
_pin: impl Peripheral<P = impl McoPin<T>> + 'd,
_source: T::Source,
) -> Self {
todo!();
}
}
pub(crate) unsafe fn init(config: Config) {
let (vos, max_clk) = match config.voltage_scale {
VoltageScale::Scale0 => (Vos::SCALE0, Hertz(250_000_000)),
VoltageScale::Scale1 => (Vos::SCALE1, Hertz(200_000_000)),
VoltageScale::Scale2 => (Vos::SCALE2, Hertz(150_000_000)),
VoltageScale::Scale3 => (Vos::SCALE3, Hertz(100_000_000)),
};
// Configure voltage scale.
PWR.voscr().modify(|w| w.set_vos(vos));
while !PWR.vossr().read().vosrdy() {}
// Configure HSI
let hsi = match config.hsi {
None => {
RCC.cr().modify(|w| w.set_hsion(false));
None
}
Some(hsi) => {
let (freq, hsidiv) = match hsi {
Hsi::Mhz64 => (HSI_FREQ / 1u32, Hsidiv::DIV1),
Hsi::Mhz32 => (HSI_FREQ / 2u32, Hsidiv::DIV2),
Hsi::Mhz16 => (HSI_FREQ / 4u32, Hsidiv::DIV4),
Hsi::Mhz8 => (HSI_FREQ / 8u32, Hsidiv::DIV8),
};
RCC.cr().modify(|w| {
w.set_hsidiv(hsidiv);
w.set_hsion(true);
});
while !RCC.cr().read().hsirdy() {}
Some(freq)
}
};
// Configure HSE
let hse = match config.hse {
None => {
RCC.cr().modify(|w| w.set_hseon(false));
None
}
Some(hse) => {
let (byp, ext) = match hse.mode {
HseMode::Oscillator => (false, Hseext::ANALOG),
HseMode::BypassAnalog => (true, Hseext::ANALOG),
HseMode::BypassDigital => (true, Hseext::DIGITAL),
};
RCC.cr().modify(|w| {
w.set_hsebyp(byp);
w.set_hseext(ext);
});
RCC.cr().modify(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
Some(hse.freq)
}
};
// Configure HSI48.
RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
let _hsi48 = match config.hsi48 {
false => None,
true => {
while !RCC.cr().read().hsi48rdy() {}
Some(CSI_FREQ)
}
};
// Configure CSI.
RCC.cr().modify(|w| w.set_csion(config.csi));
let csi = match config.csi {
false => None,
true => {
while !RCC.cr().read().csirdy() {}
Some(CSI_FREQ)
}
};
// Configure PLLs.
let pll_input = PllInput { csi, hse, hsi };
let pll1 = init_pll(0, config.pll1, &pll_input);
let _pll2 = init_pll(1, config.pll2, &pll_input);
#[cfg(rcc_h5)]
let _pll3 = init_pll(2, config.pll3, &pll_input);
// Configure sysclk
let (sys, sw) = match config.sys {
Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
Sysclk::HSE => (unwrap!(hse), Sw::HSE),
Sysclk::CSI => (unwrap!(csi), Sw::CSI),
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
};
assert!(sys <= max_clk);
let hclk = config.ahb_pre.div(sys);
let apb1 = config.apb1_pre.div(hclk);
let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler);
let apb2 = config.apb2_pre.div(hclk);
let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler);
let apb3 = config.apb3_pre.div(hclk);
flash_setup(hclk, config.voltage_scale);
// Set hpre
let hpre = config.ahb_pre.into();
RCC.cfgr2().modify(|w| w.set_hpre(hpre));
while RCC.cfgr2().read().hpre() != hpre {}
// set ppre
RCC.cfgr2().modify(|w| {
w.set_ppre1(config.apb1_pre.into());
w.set_ppre2(config.apb2_pre.into());
w.set_ppre3(config.apb3_pre.into());
});
RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
RCC.cfgr().modify(|w| w.set_sw(sw));
while RCC.cfgr().read().sws() != sw {}
set_freqs(Clocks {
sys,
ahb1: hclk,
ahb2: hclk,
ahb3: hclk,
ahb4: hclk,
apb1,
apb2,
apb3,
apb1_tim,
apb2_tim,
adc: None,
});
}
struct PllInput {
hsi: Option<Hertz>,
hse: Option<Hertz>,
csi: Option<Hertz>,
}
struct PllOutput {
p: Option<Hertz>,
#[allow(dead_code)]
q: Option<Hertz>,
#[allow(dead_code)]
r: Option<Hertz>,
}
unsafe fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
let Some(config) = config else {
// Stop PLL
RCC.cr().modify(|w| w.set_pllon(num, false));
while RCC.cr().read().pllrdy(num) {}
// "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
RCC.pllcfgr(num).write(|w| {
w.set_divm(0);
});
return PllOutput{
p: None,
q: None,
r: None,
}
};
assert!(1 <= config.prediv && config.prediv <= 63);
assert!(4 <= config.mul && config.mul <= 512);
let (in_clk, src) = match config.source {
PllSource::Hsi => (unwrap!(input.hsi), Pllsrc::HSI),
PllSource::Hse => (unwrap!(input.hse), Pllsrc::HSE),
PllSource::Csi => (unwrap!(input.csi), Pllsrc::CSI),
};
let ref_clk = in_clk / config.prediv as u32;
let ref_range = match ref_clk.0 {
..=1_999_999 => Pllrge::RANGE1,
..=3_999_999 => Pllrge::RANGE2,
..=7_999_999 => Pllrge::RANGE4,
..=16_000_000 => Pllrge::RANGE8,
x => panic!("pll ref_clk out of range: {} mhz", x),
};
// The smaller range (150 to 420 MHz) must
// be chosen when the reference clock frequency is lower than 2 MHz.
let wide_allowed = ref_range != Pllrge::RANGE1;
let vco_clk = ref_clk * config.mul;
let vco_range = match vco_clk.0 {
VCO_MIN..=VCO_MAX => Pllvcosel::MEDIUMVCO,
VCO_WIDE_MIN..=VCO_WIDE_MAX if wide_allowed => Pllvcosel::WIDEVCO,
x => panic!("pll vco_clk out of range: {} mhz", x),
};
let p = config.divp.map(|div| {
assert!(1 <= div && div <= 128);
if num == 0 {
// on PLL1, DIVP must be even.
assert!(div % 2 == 0);
}
vco_clk / div
});
let q = config.divq.map(|div| {
assert!(1 <= div && div <= 128);
vco_clk / div
});
let r = config.divr.map(|div| {
assert!(1 <= div && div <= 128);
vco_clk / div
});
RCC.pllcfgr(num).write(|w| {
w.set_pllsrc(src);
w.set_divm(config.prediv);
w.set_pllvcosel(vco_range);
w.set_pllrge(ref_range);
w.set_pllfracen(false);
w.set_pllpen(p.is_some());
w.set_pllqen(q.is_some());
w.set_pllren(r.is_some());
});
RCC.plldivr(num).write(|w| {
w.set_plln(config.mul - 1);
w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
});
RCC.cr().modify(|w| w.set_pllon(num, true));
while !RCC.cr().read().pllrdy(num) {}
PllOutput { p, q, r }
}
fn flash_setup(clk: Hertz, vos: VoltageScale) {
// RM0481 Rev 1, table 37
// LATENCY WRHIGHFREQ VOS3 VOS2 VOS1 VOS0
// 0 0 0 to 20 MHz 0 to 30 MHz 0 to 34 MHz 0 to 42 MHz
// 1 0 20 to 40 MHz 30 to 60 MHz 34 to 68 MHz 42 to 84 MHz
// 2 1 40 to 60 MHz 60 to 90 MHz 68 to 102 MHz 84 to 126 MHz
// 3 1 60 to 80 MHz 90 to 120 MHz 102 to 136 MHz 126 to 168 MHz
// 4 2 80 to 100 MHz 120 to 150 MHz 136 to 170 MHz 168 to 210 MHz
// 5 2 170 to 200 MHz 210 to 250 MHz
// See RM0433 Rev 7 Table 17. FLASH recommended number of wait
// states and programming delay
let (latency, wrhighfreq) = match (vos, clk.0) {
(VoltageScale::Scale0, ..=42_000_000) => (0, 0),
(VoltageScale::Scale0, ..=84_000_000) => (1, 0),
(VoltageScale::Scale0, ..=126_000_000) => (2, 1),
(VoltageScale::Scale0, ..=168_000_000) => (3, 1),
(VoltageScale::Scale0, ..=210_000_000) => (4, 2),
(VoltageScale::Scale0, ..=250_000_000) => (5, 2),
(VoltageScale::Scale1, ..=34_000_000) => (0, 0),
(VoltageScale::Scale1, ..=68_000_000) => (1, 0),
(VoltageScale::Scale1, ..=102_000_000) => (2, 1),
(VoltageScale::Scale1, ..=136_000_000) => (3, 1),
(VoltageScale::Scale1, ..=170_000_000) => (4, 2),
(VoltageScale::Scale1, ..=200_000_000) => (5, 2),
(VoltageScale::Scale2, ..=30_000_000) => (0, 0),
(VoltageScale::Scale2, ..=60_000_000) => (1, 0),
(VoltageScale::Scale2, ..=90_000_000) => (2, 1),
(VoltageScale::Scale2, ..=120_000_000) => (3, 1),
(VoltageScale::Scale2, ..=150_000_000) => (4, 2),
(VoltageScale::Scale3, ..=20_000_000) => (0, 0),
(VoltageScale::Scale3, ..=40_000_000) => (1, 0),
(VoltageScale::Scale3, ..=60_000_000) => (2, 1),
(VoltageScale::Scale3, ..=80_000_000) => (3, 1),
(VoltageScale::Scale3, ..=100_000_000) => (4, 2),
_ => unreachable!(),
};
defmt::debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
// NOTE(unsafe) Atomic write
unsafe {
FLASH.acr().write(|w| {
w.set_wrhighfreq(wrhighfreq);
w.set_latency(latency);
});
while FLASH.acr().read().latency() != latency {}
}
}

13
embassy-stm32/src/rcc/mod.rs
View File

@ -21,6 +21,7 @@ use crate::time::Hertz;
#[cfg_attr(rcc_u5, path = "u5.rs")]
#[cfg_attr(rcc_wb, path = "wb.rs")]
#[cfg_attr(any(rcc_wl5, rcc_wle), path = "wl.rs")]
#[cfg_attr(any(rcc_h5, rcc_h50), path = "h5.rs")]
mod _version;
pub use _version::*;
@ -36,7 +37,7 @@ pub struct Clocks {
pub apb2: Hertz,
#[cfg(not(any(rcc_c0, rcc_g0)))]
pub apb2_tim: Hertz,
#[cfg(any(rcc_wl5, rcc_wle, rcc_u5))]
#[cfg(any(rcc_wl5, rcc_wle, rcc_h5, rcc_h50, rcc_u5))]
pub apb3: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]
pub apb4: Hertz,
@ -44,14 +45,16 @@ pub struct Clocks {
// AHB
pub ahb1: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_g4, rcc_u5, rcc_wb,
rcc_wl5, rcc_wle
))]
pub ahb2: Hertz,
#[cfg(any(
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5, rcc_wle
rcc_l4, rcc_l5, rcc_f2, rcc_f4, rcc_f410, rcc_f7, rcc_h5, rcc_h50, rcc_h7, rcc_h7ab, rcc_u5, rcc_wb, rcc_wl5,
rcc_wle
))]
pub ahb3: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
pub ahb4: Hertz,
#[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
@ -60,7 +63,7 @@ pub struct Clocks {
#[cfg(stm32f1)]
pub adc: Hertz,
#[cfg(any(rcc_h7, rcc_h7ab))]
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7ab))]
pub adc: Option<Hertz>,
}

72
embassy-stm32/src/spi/mod.rs
View File

@ -258,7 +258,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_spe(true);
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.ifcr().write(|w| w.0 = 0xffff_ffff);
T::REGS.cfg2().modify(|w| {
@ -317,7 +317,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.cfg2().modify(|w| {
w.set_cpha(cpha);
@ -330,7 +330,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn get_current_config(&self) -> Config {
#[cfg(any(spi_v1, spi_f1, spi_v2))]
let cfg = unsafe { T::REGS.cr1().read() };
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let cfg = unsafe { T::REGS.cfg2().read() };
let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
Polarity::IdleLow
@ -383,7 +383,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_spe(true);
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.cr1().modify(|w| {
w.set_csusp(true);
@ -429,7 +429,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -459,7 +459,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
// SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
@ -481,7 +481,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -514,7 +514,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
// SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
@ -534,7 +534,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -619,9 +619,9 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
}
}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
use vals::Br;
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
use vals::Mbr as Br;
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
@ -647,17 +647,17 @@ trait RegsExt {
impl RegsExt for Regs {
fn tx_ptr<W>(&self) -> *mut W {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
let dr = self.dr();
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let dr = self.txdr();
dr.ptr() as *mut W
}
fn rx_ptr<W>(&self) -> *mut W {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
let dr = self.dr();
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let dr = self.rxdr();
dr.ptr() as *mut W
}
@ -667,22 +667,22 @@ fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
if sr.ovr() {
return Err(Error::Overrun);
}
#[cfg(not(any(spi_f1, spi_v3, spi_v4)))]
#[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
if sr.fre() {
return Err(Error::Framing);
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.tifre() {
return Err(Error::Framing);
}
if sr.modf() {
return Err(Error::ModeFault);
}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.crcerr() {
return Err(Error::Crc);
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.crce() {
return Err(Error::Crc);
}
@ -696,11 +696,11 @@ fn spin_until_tx_ready(regs: Regs) -> Result<(), Error> {
check_error_flags(sr)?;
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.txe() {
return Ok(());
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.txp() {
return Ok(());
}
@ -713,11 +713,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
check_error_flags(sr)?;
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.rxne() {
return Ok(());
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.rxp() {
return Ok(());
}
@ -726,11 +726,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
fn flush_rx_fifo(regs: Regs) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
while regs.sr().read().rxne() {
let _ = regs.dr().read();
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
while regs.sr().read().rxp() {
let _ = regs.rxdr().read();
}
@ -739,11 +739,11 @@ fn flush_rx_fifo(regs: Regs) {
fn set_txdmaen(regs: Regs, val: bool) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_txdmaen(val);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_txdmaen(val);
});
@ -752,11 +752,11 @@ fn set_txdmaen(regs: Regs, val: bool) {
fn set_rxdmaen(regs: Regs, val: bool) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_rxdmaen(val);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_rxdmaen(val);
});
@ -768,9 +768,9 @@ fn finish_dma(regs: Regs) {
#[cfg(spi_v2)]
while regs.sr().read().ftlvl() > 0 {}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
while !regs.sr().read().txc() {}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
while regs.sr().read().bsy() {}
// Disable the spi peripheral
@ -780,12 +780,12 @@ fn finish_dma(regs: Regs) {
// The peripheral automatically disables the DMA stream on completion without error,
// but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
@ -799,7 +799,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
unsafe {
ptr::write_volatile(regs.tx_ptr(), tx_word);
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cr1().modify(|reg| reg.set_cstart(true));
}
@ -970,7 +970,7 @@ pub(crate) mod sealed {
}
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
pub fn dsize(&self) -> u8 {
match self {
WordSize::EightBit => 0b0111,
@ -978,7 +978,7 @@ pub(crate) mod sealed {
}
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
pub fn _frxth(&self) -> vals::Fthlv {
match self {
WordSize::EightBit => vals::Fthlv::ONEFRAME,

46
embassy-stm32/src/time.rs
View File

@ -1,7 +1,9 @@
//! Time units
use core::ops::{Div, Mul};
/// Hertz
#[derive(PartialEq, PartialOrd, Clone, Copy, Debug, Eq)]
#[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Hertz(pub u32);
@ -33,3 +35,45 @@ pub fn khz(kilohertz: u32) -> Hertz {
pub fn mhz(megahertz: u32) -> Hertz {
Hertz::mhz(megahertz)
}
impl Mul<u32> for Hertz {
type Output = Hertz;
fn mul(self, rhs: u32) -> Self::Output {
Hertz(self.0 * rhs)
}
}
impl Div<u32> for Hertz {
type Output = Hertz;
fn div(self, rhs: u32) -> Self::Output {
Hertz(self.0 / rhs)
}
}
impl Mul<u16> for Hertz {
type Output = Hertz;
fn mul(self, rhs: u16) -> Self::Output {
self * (rhs as u32)
}
}
impl Div<u16> for Hertz {
type Output = Hertz;
fn div(self, rhs: u16) -> Self::Output {
self / (rhs as u32)
}
}
impl Mul<u8> for Hertz {
type Output = Hertz;
fn mul(self, rhs: u8) -> Self::Output {
self * (rhs as u32)
}
}
impl Div<u8> for Hertz {
type Output = Hertz;
fn div(self, rhs: u8) -> Self::Output {
self / (rhs as u32)
}
}

134
embassy-stm32/src/usb/usb.rs
View File

@ -12,22 +12,29 @@ use embassy_usb_driver as driver;
use embassy_usb_driver::{
Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
};
use pac::common::{Reg, RW};
use pac::usb::vals::{EpType, Stat};
use super::{DmPin, DpPin, Instance};
use crate::gpio::sealed::AFType;
use crate::interrupt::InterruptExt;
use crate::pac::usb::regs;
use crate::pac::usb::vals::{EpType, Stat};
use crate::pac::USBRAM;
use crate::rcc::sealed::RccPeripheral;
use crate::{pac, Peripheral};
use crate::Peripheral;
const EP_COUNT: usize = 8;
#[cfg(any(usb_v1_x1, usb_v1_x2))]
const EP_MEMORY_SIZE: usize = 512;
#[cfg(not(any(usb_v1_x1, usb_v1_x2)))]
const EP_MEMORY_SIZE: usize = 1024;
#[cfg(any(usbram_16x1_512, usbram_16x2_512))]
const USBRAM_SIZE: usize = 512;
#[cfg(usbram_16x2_1024)]
const USBRAM_SIZE: usize = 1024;
#[cfg(usbram_32_2048)]
const USBRAM_SIZE: usize = 2048;
#[cfg(not(usbram_32_2048))]
const USBRAM_ALIGN: usize = 2;
#[cfg(usbram_32_2048)]
const USBRAM_ALIGN: usize = 4;
const NEW_AW: AtomicWaker = AtomicWaker::new();
static BUS_WAKER: AtomicWaker = NEW_AW;
@ -57,25 +64,60 @@ fn invariant(mut r: regs::Epr) -> regs::Epr {
r
}
fn align_len_up(len: u16) -> u16 {
((len as usize + USBRAM_ALIGN - 1) / USBRAM_ALIGN * USBRAM_ALIGN) as u16
}
// Returns (actual_len, len_bits)
fn calc_out_len(len: u16) -> (u16, u16) {
match len {
2..=62 => ((len + 1) / 2 * 2, ((len + 1) / 2) << 10),
63..=480 => ((len + 31) / 32 * 32, (((len + 31) / 32 - 1) << 10) | 0x8000),
// NOTE: this could be 2..=62 with 16bit USBRAM, but not with 32bit. Limit it to 60 for simplicity.
2..=60 => (align_len_up(len), align_len_up(len) / 2 << 10),
61..=1024 => ((len + 31) / 32 * 32, (((len + 31) / 32 - 1) << 10) | 0x8000),
_ => panic!("invalid OUT length {}", len),
}
}
fn ep_in_addr<T: Instance>(index: usize) -> Reg<u16, RW> {
T::regs().ep_mem(index * 4 + 0)
#[cfg(not(usbram_32_2048))]
mod btable {
use super::*;
pub(super) unsafe fn write_in<T: Instance>(index: usize, addr: u16) {
USBRAM.mem(index * 4 + 0).write_value(addr);
}
pub(super) unsafe fn write_in_len<T: Instance>(index: usize, _addr: u16, len: u16) {
USBRAM.mem(index * 4 + 1).write_value(len);
}
pub(super) unsafe fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
USBRAM.mem(index * 4 + 2).write_value(addr);
USBRAM.mem(index * 4 + 3).write_value(max_len_bits);
}
pub(super) unsafe fn read_out_len<T: Instance>(index: usize) -> u16 {
USBRAM.mem(index * 4 + 3).read()
}
}
fn ep_in_len<T: Instance>(index: usize) -> Reg<u16, RW> {
T::regs().ep_mem(index * 4 + 1)
}
fn ep_out_addr<T: Instance>(index: usize) -> Reg<u16, RW> {
T::regs().ep_mem(index * 4 + 2)
}
fn ep_out_len<T: Instance>(index: usize) -> Reg<u16, RW> {
T::regs().ep_mem(index * 4 + 3)
#[cfg(usbram_32_2048)]
mod btable {
use super::*;
pub(super) unsafe fn write_in<T: Instance>(_index: usize, _addr: u16) {}
pub(super) unsafe fn write_in_len<T: Instance>(index: usize, addr: u16, len: u16) {
USBRAM.mem(index * 2).write_value((addr as u32) | ((len as u32) << 16));
}
pub(super) unsafe fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
USBRAM
.mem(index * 2 + 1)
.write_value((addr as u32) | ((max_len_bits as u32) << 16));
}
pub(super) unsafe fn read_out_len<T: Instance>(index: usize) -> u16 {
(USBRAM.mem(index * 2 + 1).read() >> 16) as u16
}
}
struct EndpointBuffer<T: Instance> {
@ -87,23 +129,25 @@ struct EndpointBuffer<T: Instance> {
impl<T: Instance> EndpointBuffer<T> {
fn read(&mut self, buf: &mut [u8]) {
assert!(buf.len() <= self.len as usize);
for i in 0..((buf.len() + 1) / 2) {
let val = unsafe { T::regs().ep_mem(self.addr as usize / 2 + i).read() };
buf[i * 2] = val as u8;
if i * 2 + 1 < buf.len() {
buf[i * 2 + 1] = (val >> 8) as u8;
}
for i in 0..(buf.len() + USBRAM_ALIGN - 1) / USBRAM_ALIGN {
let val = unsafe { USBRAM.mem(self.addr as usize / USBRAM_ALIGN + i).read() };
let n = USBRAM_ALIGN.min(buf.len() - i * USBRAM_ALIGN);
buf[i * USBRAM_ALIGN..][..n].copy_from_slice(&val.to_le_bytes()[..n]);
}
}
fn write(&mut self, buf: &[u8]) {
assert!(buf.len() <= self.len as usize);
for i in 0..((buf.len() + 1) / 2) {
let mut val = buf[i * 2] as u16;
if i * 2 + 1 < buf.len() {
val |= (buf[i * 2 + 1] as u16) << 8;
}
unsafe { T::regs().ep_mem(self.addr as usize / 2 + i).write_value(val) };
for i in 0..(buf.len() + USBRAM_ALIGN - 1) / USBRAM_ALIGN {
let mut val = [0u8; USBRAM_ALIGN];
let n = USBRAM_ALIGN.min(buf.len() - i * USBRAM_ALIGN);
val[..n].copy_from_slice(&buf[i * USBRAM_ALIGN..][..n]);
#[cfg(not(usbram_32_2048))]
let val = u16::from_le_bytes(val);
#[cfg(usbram_32_2048)]
let val = u32::from_le_bytes(val);
unsafe { USBRAM.mem(self.addr as usize / USBRAM_ALIGN + i).write_value(val) };
}
}
}
@ -139,8 +183,12 @@ impl<'d, T: Instance> Driver<'d, T> {
#[cfg(stm32l5)]
unsafe {
crate::peripherals::PWR::enable();
crate::pac::PWR.cr2().modify(|w| w.set_usv(true));
}
pac::PWR.cr2().modify(|w| w.set_usv(true));
#[cfg(pwr_h5)]
unsafe {
crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true))
}
unsafe {
@ -256,8 +304,9 @@ impl<'d, T: Instance> Driver<'d, T> {
}
fn alloc_ep_mem(&mut self, len: u16) -> u16 {
assert!(len as usize % USBRAM_ALIGN == 0);
let addr = self.ep_mem_free;
if addr + len > EP_MEMORY_SIZE as _ {
if addr + len > USBRAM_SIZE as _ {
panic!("Endpoint memory full");
}
self.ep_mem_free += len;
@ -306,10 +355,7 @@ impl<'d, T: Instance> Driver<'d, T> {
let addr = self.alloc_ep_mem(len);
trace!(" len_bits = {:04x}", len_bits);
unsafe {
ep_out_addr::<T>(index).write_value(addr);
ep_out_len::<T>(index).write_value(len_bits);
}
unsafe { btable::write_out::<T>(index, addr, len_bits) }
EndpointBuffer {
addr,
@ -321,13 +367,11 @@ impl<'d, T: Instance> Driver<'d, T> {
assert!(!ep.used_in);
ep.used_in = true;
let len = (max_packet_size + 1) / 2 * 2;
let len = align_len_up(max_packet_size);
let addr = self.alloc_ep_mem(len);
unsafe {
ep_in_addr::<T>(index).write_value(addr);
// ep_in_len is written when actually TXing packets.
}
// ep_in_len is written when actually TXing packets.
unsafe { btable::write_in::<T>(index, addr) }
EndpointBuffer {
addr,
@ -398,7 +442,7 @@ impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
w.set_ctrm(true);
});
#[cfg(usb_v3)]
#[cfg(any(usb_v3, usb_v4))]
regs.bcdr().write(|w| w.set_dppu(true))
}
@ -633,12 +677,12 @@ impl<'d, T: Instance, D> Endpoint<'d, T, D> {
fn write_data(&mut self, buf: &[u8]) {
let index = self.info.addr.index();
self.buf.write(buf);
unsafe { ep_in_len::<T>(index).write_value(buf.len() as _) };
unsafe { btable::write_in_len::<T>(index, self.buf.addr, buf.len() as _) }
}
fn read_data(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
let index = self.info.addr.index();
let rx_len = unsafe { ep_out_len::<T>(index).read() as usize } & 0x3FF;
let rx_len = unsafe { btable::read_out_len::<T>(index) as usize } & 0x3FF;
trace!("READ DONE, rx_len = {}", rx_len);
if rx_len > buf.len() {
return Err(EndpointError::BufferOverflow);

6
embassy-stm32/src/usb_otg/mod.rs
View File

@ -89,6 +89,9 @@ foreach_interrupt!(
} else if #[cfg(stm32h7)] {
const FIFO_DEPTH_WORDS: u16 = 1024;
const ENDPOINT_COUNT: usize = 9;
} else if #[cfg(stm32u5)] {
const FIFO_DEPTH_WORDS: u16 = 320;
const ENDPOINT_COUNT: usize = 6;
} else {
compile_error!("USB_OTG_FS peripheral is not supported by this chip.");
}
@ -137,6 +140,9 @@ foreach_interrupt!(
))] {
const FIFO_DEPTH_WORDS: u16 = 1024;
const ENDPOINT_COUNT: usize = 9;
} else if #[cfg(stm32u5)] {
const FIFO_DEPTH_WORDS: u16 = 1024;
const ENDPOINT_COUNT: usize = 9;
} else {
compile_error!("USB_OTG_HS peripheral is not supported by this chip.");
}

4
embassy-time/Cargo.toml
View File

@ -152,8 +152,8 @@ defmt = { version = "0.3", optional = true }
log = { version = "0.4.14", optional = true }
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true}
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10", optional = true}
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true}
futures-util = { version = "0.3.17", default-features = false }
embassy-sync = { version = "0.1", path = "../embassy-sync" }

20
embassy-time/src/delay.rs
View File

@ -19,14 +19,12 @@ mod eh1 {
use super::*;
impl embedded_hal_1::delay::DelayUs for Delay {
type Error = core::convert::Infallible;
fn delay_us(&mut self, us: u32) -> Result<(), Self::Error> {
Ok(block_for(Duration::from_micros(us as u64)))
fn delay_us(&mut self, us: u32) {
block_for(Duration::from_micros(us as u64))
}
fn delay_ms(&mut self, ms: u32) -> Result<(), Self::Error> {
Ok(block_for(Duration::from_millis(ms as u64)))
fn delay_ms(&mut self, ms: u32) {
block_for(Duration::from_millis(ms as u64))
}
}
}
@ -37,14 +35,12 @@ mod eha {
use crate::Timer;
impl embedded_hal_async::delay::DelayUs for Delay {
type Error = core::convert::Infallible;
async fn delay_us(&mut self, micros: u32) -> Result<(), Self::Error> {
Ok(Timer::after(Duration::from_micros(micros as _)).await)
async fn delay_us(&mut self, micros: u32) {
Timer::after(Duration::from_micros(micros as _)).await
}
async fn delay_ms(&mut self, millis: u32) -> Result<(), Self::Error> {
Ok(Timer::after(Duration::from_millis(millis as _)).await)
async fn delay_ms(&mut self, millis: u32) {
Timer::after(Duration::from_millis(millis as _)).await
}
}
}

7
examples/boot/bootloader/stm32/src/main.rs
View File

@ -5,7 +5,7 @@ use cortex_m_rt::{entry, exception};
#[cfg(feature = "defmt")]
use defmt_rtt as _;
use embassy_boot_stm32::*;
use embassy_stm32::flash::{Flash, ERASE_SIZE};
use embassy_stm32::flash::Flash;
#[entry]
fn main() -> ! {
@ -19,9 +19,10 @@ fn main() -> ! {
}
*/
let mut bl: BootLoader<ERASE_SIZE> = BootLoader::default();
let mut bl: BootLoader<2048> = BootLoader::default();
let flash = Flash::new(p.FLASH);
let mut flash = BootFlash::new(flash);
let layout = flash.into_regions();
let mut flash = BootFlash::new(layout.bank1_region);
let start = bl.prepare(&mut SingleFlashConfig::new(&mut flash));
core::mem::drop(flash);
unsafe { bl.load(start) }

2
examples/rp/.cargo/config.toml
View File

@ -1,5 +1,5 @@
[target.'cfg(all(target_arch = "arm", target_os = "none"))']
runner = "probe-run --chip RP2040"
runner = "probe-rs-cli run --chip RP2040"
[build]
target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+

5
examples/rp/Cargo.toml
View File

@ -6,6 +6,7 @@ license = "MIT OR Apache-2.0"
[dependencies]
embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal", features = ["defmt"] }
embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
@ -30,8 +31,8 @@ display-interface = "0.4.1"
byte-slice-cast = { version = "1.2.0", default-features = false }
smart-leds = "0.3.0"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = "0.2.0-alpha.0"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = "0.2.0-alpha.1"
embedded-io = { version = "0.4.0", features = ["async", "defmt"] }
embedded-storage = { version = "0.3" }
static_cell = "1.0.0"

158
examples/rp/src/bin/spi_display.rs
View File

@ -5,10 +5,13 @@
use core::cell::RefCell;
use defmt::*;
use embassy_embedded_hal::shared_bus::blocking::spi::SpiDeviceWithConfig;
use embassy_executor::Spawner;
use embassy_rp::gpio::{Level, Output};
use embassy_rp::spi;
use embassy_rp::spi::{Blocking, Spi};
use embassy_sync::blocking_mutex::raw::NoopRawMutex;
use embassy_sync::blocking_mutex::Mutex;
use embassy_time::Delay;
use embedded_graphics::image::{Image, ImageRawLE};
use embedded_graphics::mono_font::ascii::FONT_10X20;
@ -21,10 +24,9 @@ use st7789::{Orientation, ST7789};
use {defmt_rtt as _, panic_probe as _};
use crate::my_display_interface::SPIDeviceInterface;
use crate::shared_spi::SpiDeviceWithCs;
use crate::touch::Touch;
//const DISPLAY_FREQ: u32 = 64_000_000;
const DISPLAY_FREQ: u32 = 64_000_000;
const TOUCH_FREQ: u32 = 200_000;
#[embassy_executor::main]
@ -43,16 +45,20 @@ async fn main(_spawner: Spawner) {
//let touch_irq = p.PIN_17;
// create SPI
let mut config = spi::Config::default();
config.frequency = TOUCH_FREQ; // use the lowest freq
config.phase = spi::Phase::CaptureOnSecondTransition;
config.polarity = spi::Polarity::IdleHigh;
let mut display_config = spi::Config::default();
display_config.frequency = DISPLAY_FREQ;
display_config.phase = spi::Phase::CaptureOnSecondTransition;
display_config.polarity = spi::Polarity::IdleHigh;
let mut touch_config = spi::Config::default();
touch_config.frequency = TOUCH_FREQ;
touch_config.phase = spi::Phase::CaptureOnSecondTransition;
touch_config.polarity = spi::Polarity::IdleHigh;
let spi: Spi<'_, _, Blocking> = Spi::new_blocking(p.SPI1, clk, mosi, miso, config);
let spi_bus = RefCell::new(spi);
let spi: Spi<'_, _, Blocking> = Spi::new_blocking(p.SPI1, clk, mosi, miso, touch_config.clone());
let spi_bus: Mutex<NoopRawMutex, _> = Mutex::new(RefCell::new(spi));
let display_spi = SpiDeviceWithCs::new(&spi_bus, Output::new(display_cs, Level::High));
let touch_spi = SpiDeviceWithCs::new(&spi_bus, Output::new(touch_cs, Level::High));
let display_spi = SpiDeviceWithConfig::new(&spi_bus, Output::new(display_cs, Level::High), display_config);
let touch_spi = SpiDeviceWithConfig::new(&spi_bus, Output::new(touch_cs, Level::High), touch_config);
let mut touch = Touch::new(touch_spi);
@ -104,85 +110,9 @@ async fn main(_spawner: Spawner) {
}
}
mod shared_spi {
use core::cell::RefCell;
use core::fmt::Debug;
use embedded_hal_1::digital::OutputPin;
use embedded_hal_1::spi;
use embedded_hal_1::spi::SpiDevice;
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum SpiDeviceWithCsError<BUS, CS> {
#[allow(unused)] // will probably use in the future when adding a flush() to SpiBus
Spi(BUS),
Cs(CS),
}
impl<BUS, CS> spi::Error for SpiDeviceWithCsError<BUS, CS>
where
BUS: spi::Error + Debug,
CS: Debug,
{
fn kind(&self) -> spi::ErrorKind {
match self {
Self::Spi(e) => e.kind(),
Self::Cs(_) => spi::ErrorKind::Other,
}
}
}
pub struct SpiDeviceWithCs<'a, BUS, CS> {
bus: &'a RefCell<BUS>,
cs: CS,
}
impl<'a, BUS, CS> SpiDeviceWithCs<'a, BUS, CS> {
pub fn new(bus: &'a RefCell<BUS>, cs: CS) -> Self {
Self { bus, cs }
}
}
impl<'a, BUS, CS> spi::ErrorType for SpiDeviceWithCs<'a, BUS, CS>
where
BUS: spi::ErrorType,
CS: OutputPin,
{
type Error = SpiDeviceWithCsError<BUS::Error, CS::Error>;
}
impl<'a, BUS, CS> SpiDevice for SpiDeviceWithCs<'a, BUS, CS>
where
BUS: spi::SpiBusFlush,
CS: OutputPin,
{
type Bus = BUS;
fn transaction<R>(
&mut self,
f: impl FnOnce(&mut Self::Bus) -> Result<R, BUS::Error>,
) -> Result<R, Self::Error> {
let mut bus = self.bus.borrow_mut();
self.cs.set_low().map_err(SpiDeviceWithCsError::Cs)?;
let f_res = f(&mut bus);
// On failure, it's important to still flush and deassert CS.
let flush_res = bus.flush();
let cs_res = self.cs.set_high();
let f_res = f_res.map_err(SpiDeviceWithCsError::Spi)?;
flush_res.map_err(SpiDeviceWithCsError::Spi)?;
cs_res.map_err(SpiDeviceWithCsError::Cs)?;
Ok(f_res)
}
}
}
/// Driver for the XPT2046 resistive touchscreen sensor
mod touch {
use embedded_hal_1::spi::{SpiBus, SpiBusRead, SpiBusWrite, SpiDevice};
use embedded_hal_1::spi::{Operation, SpiDevice};
struct Calibration {
x1: i32,
@ -209,7 +139,6 @@ mod touch {
impl<SPI> Touch<SPI>
where
SPI: SpiDevice,
SPI::Bus: SpiBus,
{
pub fn new(spi: SPI) -> Self {
Self { spi }
@ -219,13 +148,12 @@ mod touch {
let mut x = [0; 2];
let mut y = [0; 2];
self.spi
.transaction(|bus| {
bus.write(&[0x90])?;
bus.read(&mut x)?;
bus.write(&[0xd0])?;
bus.read(&mut y)?;
Ok(())
})
.transaction(&mut [
Operation::Write(&[0x90]),
Operation::Read(&mut x),
Operation::Write(&[0xd0]),
Operation::Read(&mut y),
])
.unwrap();
let x = (u16::from_be_bytes(x) >> 3) as i32;
@ -247,7 +175,7 @@ mod touch {
mod my_display_interface {
use display_interface::{DataFormat, DisplayError, WriteOnlyDataCommand};
use embedded_hal_1::digital::OutputPin;
use embedded_hal_1::spi::{SpiBusWrite, SpiDevice};
use embedded_hal_1::spi::SpiDeviceWrite;
/// SPI display interface.
///
@ -259,8 +187,7 @@ mod my_display_interface {
impl<SPI, DC> SPIDeviceInterface<SPI, DC>
where
SPI: SpiDevice,
SPI::Bus: SpiBusWrite,
SPI: SpiDeviceWrite,
DC: OutputPin,
{
/// Create new SPI interface for communciation with a display driver
@ -271,42 +198,27 @@ mod my_display_interface {
impl<SPI, DC> WriteOnlyDataCommand for SPIDeviceInterface<SPI, DC>
where
SPI: SpiDevice,
SPI::Bus: SpiBusWrite,
SPI: SpiDeviceWrite,
DC: OutputPin,
{
fn send_commands(&mut self, cmds: DataFormat<'_>) -> Result<(), DisplayError> {
let r = self.spi.transaction(|bus| {
// 1 = data, 0 = command
if let Err(_) = self.dc.set_low() {
return Ok(Err(DisplayError::DCError));
}
// 1 = data, 0 = command
self.dc.set_low().map_err(|_| DisplayError::DCError)?;
// Send words over SPI
send_u8(bus, cmds)?;
Ok(Ok(()))
});
r.map_err(|_| DisplayError::BusWriteError)?
send_u8(&mut self.spi, cmds).map_err(|_| DisplayError::BusWriteError)?;
Ok(())
}
fn send_data(&mut self, buf: DataFormat<'_>) -> Result<(), DisplayError> {
let r = self.spi.transaction(|bus| {
// 1 = data, 0 = command
if let Err(_) = self.dc.set_high() {
return Ok(Err(DisplayError::DCError));
}
// 1 = data, 0 = command
self.dc.set_high().map_err(|_| DisplayError::DCError)?;
// Send words over SPI
send_u8(bus, buf)?;
Ok(Ok(()))
});
r.map_err(|_| DisplayError::BusWriteError)?
send_u8(&mut self.spi, buf).map_err(|_| DisplayError::BusWriteError)?;
Ok(())
}
}
fn send_u8<T: SpiBusWrite>(spi: &mut T, words: DataFormat<'_>) -> Result<(), T::Error> {
fn send_u8<T: SpiDeviceWrite>(spi: &mut T, words: DataFormat<'_>) -> Result<(), T::Error> {
match words {
DataFormat::U8(slice) => spi.write(slice),
DataFormat::U16(slice) => {

35
examples/stm32f0/src/bin/adc.rs Normal file
View File

@ -0,0 +1,35 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::adc::{Adc, SampleTime};
use embassy_time::{Delay, Duration, Timer};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let mut adc = Adc::new(p.ADC, &mut Delay);
adc.set_sample_time(SampleTime::Cycles71_5);
let mut pin = p.PA1;
let mut vrefint = adc.enable_vref(&mut Delay);
let vrefint_sample = adc.read_internal(&mut vrefint);
let convert_to_millivolts = |sample| {
// From https://www.st.com/resource/en/datasheet/stm32f031c6.pdf
// 6.3.4 Embedded reference voltage
const VREFINT_MV: u32 = 1230; // mV
(u32::from(sample) * VREFINT_MV / u32::from(vrefint_sample)) as u16
};
loop {
let v = adc.read(&mut pin);
info!("--> {} - {} mV", v, convert_to_millivolts(v));
Timer::after(Duration::from_millis(100)).await;
}
}

2
examples/stm32f1/Cargo.toml
View File

@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f103c8", "unstable-pac", "memory-x", "time-driver-any"] }
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f103c8", "unstable-pac", "memory-x", "time-driver-any", "unstable-traits" ] }
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }

2
examples/stm32f3/src/bin/flash.rs
View File

@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
const ADDR: u32 = 0x26000;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank1_region;
info!("Reading...");
let mut buf = [0u8; 8];

13
examples/stm32f4/src/bin/flash.rs
View File

@ -5,7 +5,6 @@
use defmt::{info, unwrap};
use embassy_executor::Spawner;
use embassy_stm32::flash::Flash;
use embedded_storage::nor_flash::{NorFlash, ReadNorFlash};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
@ -13,6 +12,8 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello Flash!");
// Once can also call `into_regions()` to get access to NorFlash implementations
// for each of the unique characteristics.
let mut f = Flash::new(p.FLASH);
// Sector 5
@ -30,19 +31,19 @@ fn test_flash(f: &mut Flash, offset: u32, size: u32) {
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.read(offset, &mut buf));
unwrap!(f.blocking_read(offset, &mut buf));
info!("Read: {=[u8]:x}", buf);
info!("Erasing...");
unwrap!(f.erase(offset, offset + size));
unwrap!(f.blocking_erase(offset, offset + size));
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.read(offset, &mut buf));
unwrap!(f.blocking_read(offset, &mut buf));
info!("Read after erase: {=[u8]:x}", buf);
info!("Writing...");
unwrap!(f.write(
unwrap!(f.blocking_write(
offset,
&[
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
@ -52,7 +53,7 @@ fn test_flash(f: &mut Flash, offset: u32, size: u32) {
info!("Reading...");
let mut buf = [0u8; 32];
unwrap!(f.read(offset, &mut buf));
unwrap!(f.blocking_read(offset, &mut buf));
info!("Read: {=[u8]:x}", buf);
assert_eq!(
&buf[..],

77
examples/stm32f4/src/bin/pwm_complementary.rs Normal file
View File

@ -0,0 +1,77 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::pwm::complementary_pwm::{Ckd, ComplementaryPwm, ComplementaryPwmPin};
use embassy_stm32::pwm::simple_pwm::PwmPin;
use embassy_stm32::pwm::Channel;
use embassy_stm32::time::khz;
use embassy_time::{Duration, Timer};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let ch1 = PwmPin::new_ch1(p.PE9);
let ch1n = ComplementaryPwmPin::new_ch1(p.PA7);
let mut pwm = ComplementaryPwm::new(
p.TIM1,
Some(ch1),
Some(ch1n),
None,
None,
None,
None,
None,
None,
khz(10),
);
/*
Dead-time = T_clk * T_dts * T_dtg
T_dts:
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters
(ETR, TIx),
00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
T_dtg:
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
*/
pwm.set_dead_time_clock_division(Ckd::DIV1);
pwm.set_dead_time_value(0);
let max = pwm.get_max_duty();
pwm.enable(Channel::Ch1);
info!("PWM initialized");
info!("PWM max duty {}", max);
loop {
pwm.set_duty(Channel::Ch1, 0);
Timer::after(Duration::from_millis(300)).await;
pwm.set_duty(Channel::Ch1, max / 4);
Timer::after(Duration::from_millis(300)).await;
pwm.set_duty(Channel::Ch1, max / 2);
Timer::after(Duration::from_millis(300)).await;
pwm.set_duty(Channel::Ch1, max - 1);
Timer::after(Duration::from_millis(300)).await;
}
}

4
examples/stm32f7/src/bin/flash.rs
View File

@ -14,12 +14,12 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello Flash!");
const ADDR: u32 = 0x8_0000;
const ADDR: u32 = 0x8_0000; // This is the offset into the third region, the absolute address is 4x32K + 128K + 0x8_0000.
// wait a bit before accessing the flash
Timer::after(Duration::from_millis(300)).await;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank1_region3;
info!("Reading...");
let mut buf = [0u8; 32];

8
examples/stm32h5/.cargo/config.toml Normal file
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@ -0,0 +1,8 @@
[target.thumbv8m.main-none-eabihf]
runner = 'probe-rs-cli run --chip STM32H563ZITx'
[build]
target = "thumbv8m.main-none-eabihf"
[env]
DEFMT_LOG = "trace"

71
examples/stm32h5/Cargo.toml Normal file
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@ -0,0 +1,71 @@
[package]
edition = "2021"
name = "embassy-stm32h7-examples"
version = "0.1.0"
license = "MIT OR Apache-2.0"
[dependencies]
embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h563zi", "time-driver-any", "exti", "unstable-pac", "unstable-traits"] }
embassy-net = { path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "unstable-traits", "proto-ipv6"] }
embedded-io = { version = "0.4.0", features = ["async"] }
embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
defmt = "0.3"
defmt-rtt = "0.4"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
embedded-nal-async = "0.4.0"
panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
heapless = { version = "0.7.5", default-features = false }
rand_core = "0.6.3"
critical-section = "1.1"
micromath = "2.0.0"
stm32-fmc = "0.2.4"
embedded-storage = "0.3.0"
static_cell = "1.0"
# cargo build/run
[profile.dev]
codegen-units = 1
debug = 2
debug-assertions = true # <-
incremental = false
opt-level = 3 # <-
overflow-checks = true # <-
# cargo test
[profile.test]
codegen-units = 1
debug = 2
debug-assertions = true # <-
incremental = false
opt-level = 3 # <-
overflow-checks = true # <-
# cargo build/run --release
[profile.release]
codegen-units = 1
debug = 2
debug-assertions = false # <-
incremental = false
lto = 'fat'
opt-level = 3 # <-
overflow-checks = false # <-
# cargo test --release
[profile.bench]
codegen-units = 1
debug = 2
debug-assertions = false # <-
incremental = false
lto = 'fat'
opt-level = 3 # <-
overflow-checks = false # <-

5
examples/stm32h5/build.rs Normal file
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@ -0,0 +1,5 @@
fn main() {
println!("cargo:rustc-link-arg-bins=--nmagic");
println!("cargo:rustc-link-arg-bins=-Tlink.x");
println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
}

5
examples/stm32h5/memory.x Normal file
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@ -0,0 +1,5 @@
MEMORY
{
FLASH : ORIGIN = 0x08000000, LENGTH = 0x200000
RAM : ORIGIN = 0x20000000, LENGTH = 0x50000
}

27
examples/stm32h5/src/bin/blinky.rs Normal file
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@ -0,0 +1,27 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::gpio::{Level, Output, Speed};
use embassy_time::{Duration, Timer};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let mut led = Output::new(p.PB0, Level::High, Speed::Low);
loop {
info!("high");
led.set_high();
Timer::after(Duration::from_millis(500)).await;
info!("low");
led.set_low();
Timer::after(Duration::from_millis(500)).await;
}
}

27
examples/stm32h5/src/bin/button_exti.rs Normal file
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@ -0,0 +1,27 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::exti::ExtiInput;
use embassy_stm32::gpio::{Input, Pull};
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let button = Input::new(p.PC13, Pull::Down);
let mut button = ExtiInput::new(button, p.EXTI13);
info!("Press the USER button...");
loop {
button.wait_for_rising_edge().await;
info!("Pressed!");
button.wait_for_falling_edge().await;
info!("Released!");
}
}

133
examples/stm32h5/src/bin/eth.rs Normal file
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@ -0,0 +1,133 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_net::tcp::TcpSocket;
use embassy_net::{Ipv4Address, Stack, StackResources};
use embassy_stm32::eth::generic_smi::GenericSMI;
use embassy_stm32::eth::{Ethernet, PacketQueue};
use embassy_stm32::peripherals::ETH;
use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
use embassy_stm32::rng::Rng;
use embassy_stm32::time::Hertz;
use embassy_stm32::{interrupt, Config};
use embassy_time::{Duration, Timer};
use embedded_io::asynch::Write;
use rand_core::RngCore;
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
macro_rules! singleton {
($val:expr) => {{
type T = impl Sized;
static STATIC_CELL: StaticCell<T> = StaticCell::new();
let (x,) = STATIC_CELL.init(($val,));
x
}};
}
type Device = Ethernet<'static, ETH, GenericSMI>;
#[embassy_executor::task]
async fn net_task(stack: &'static Stack<Device>) -> ! {
stack.run().await
}
#[embassy_executor::main]
async fn main(spawner: Spawner) -> ! {
let mut config = Config::default();
config.rcc.hsi = None;
config.rcc.hsi48 = true; // needed for rng
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::BypassDigital,
});
config.rcc.pll1 = Some(Pll {
source: PllSource::Hse,
prediv: 2,
mul: 125,
divp: Some(2),
divq: Some(2),
divr: None,
});
config.rcc.ahb_pre = AHBPrescaler::NotDivided;
config.rcc.apb1_pre = APBPrescaler::NotDivided;
config.rcc.apb2_pre = APBPrescaler::NotDivided;
config.rcc.apb3_pre = APBPrescaler::NotDivided;
config.rcc.sys = Sysclk::Pll1P;
config.rcc.voltage_scale = VoltageScale::Scale0;
let p = embassy_stm32::init(config);
info!("Hello World!");
// Generate random seed.
let mut rng = Rng::new(p.RNG);
let mut seed = [0; 8];
rng.fill_bytes(&mut seed);
let seed = u64::from_le_bytes(seed);
let eth_int = interrupt::take!(ETH);
let mac_addr = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
let device = Ethernet::new(
singleton!(PacketQueue::<4, 4>::new()),
p.ETH,
eth_int,
p.PA1,
p.PA2,
p.PC1,
p.PA7,
p.PC4,
p.PC5,
p.PG13,
p.PB15,
p.PG11,
GenericSMI,
mac_addr,
0,
);
let config = embassy_net::Config::Dhcp(Default::default());
//let config = embassy_net::Config::Static(embassy_net::StaticConfig {
// address: Ipv4Cidr::new(Ipv4Address::new(10, 42, 0, 61), 24),
// dns_servers: Vec::new(),
// gateway: Some(Ipv4Address::new(10, 42, 0, 1)),
//});
// Init network stack
let stack = &*singleton!(Stack::new(device, config, singleton!(StackResources::<2>::new()), seed));
// Launch network task
unwrap!(spawner.spawn(net_task(&stack)));
info!("Network task initialized");
// Then we can use it!
let mut rx_buffer = [0; 1024];
let mut tx_buffer = [0; 1024];
loop {
let mut socket = TcpSocket::new(&stack, &mut rx_buffer, &mut tx_buffer);
socket.set_timeout(Some(embassy_net::SmolDuration::from_secs(10)));
let remote_endpoint = (Ipv4Address::new(10, 42, 0, 1), 8000);
info!("connecting...");
let r = socket.connect(remote_endpoint).await;
if let Err(e) = r {
info!("connect error: {:?}", e);
Timer::after(Duration::from_secs(3)).await;
continue;
}
info!("connected!");
loop {
let r = socket.write_all(b"Hello\n").await;
if let Err(e) = r {
info!("write error: {:?}", e);
continue;
}
Timer::after(Duration::from_secs(1)).await;
}
}
}

44
examples/stm32h5/src/bin/i2c.rs Normal file
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@ -0,0 +1,44 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::i2c::{Error, I2c, TimeoutI2c};
use embassy_stm32::interrupt;
use embassy_stm32::time::Hertz;
use embassy_time::Duration;
use {defmt_rtt as _, panic_probe as _};
const ADDRESS: u8 = 0x5F;
const WHOAMI: u8 = 0x0F;
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
info!("Hello world!");
let p = embassy_stm32::init(Default::default());
let irq = interrupt::take!(I2C2_EV);
let mut i2c = I2c::new(
p.I2C2,
p.PB10,
p.PB11,
irq,
p.GPDMA1_CH4,
p.GPDMA1_CH5,
Hertz(100_000),
Default::default(),
);
// I2C bus can freeze if SCL line is shorted or due to a broken device that clock stretches for too long.
// TimeoutI2c allows recovering from such errors by throwing `Error::Timeout` after a given delay.
let mut timeout_i2c = TimeoutI2c::new(&mut i2c, Duration::from_millis(1000));
let mut data = [0u8; 1];
match timeout_i2c.blocking_write_read(ADDRESS, &[WHOAMI], &mut data) {
Ok(()) => info!("Whoami: {}", data[0]),
Err(Error::Timeout) => error!("Operation timed out"),
Err(e) => error!("I2c Error: {:?}", e),
}
}

20
examples/stm32h5/src/bin/rng.rs Normal file
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@ -0,0 +1,20 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::rng::Rng;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let mut rng = Rng::new(p.RNG);
let mut buf = [0u8; 16];
unwrap!(rng.async_fill_bytes(&mut buf).await);
info!("random bytes: {:02x}", buf);
}

43
examples/stm32h5/src/bin/usart.rs Normal file
View File

@ -0,0 +1,43 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use cortex_m_rt::entry;
use defmt::*;
use embassy_executor::Executor;
use embassy_stm32::dma::NoDma;
use embassy_stm32::interrupt;
use embassy_stm32::usart::{Config, Uart};
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let config = Config::default();
let irq = interrupt::take!(UART7);
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, NoDma, NoDma, config);
unwrap!(usart.blocking_write(b"Hello Embassy World!\r\n"));
info!("wrote Hello, starting echo");
let mut buf = [0u8; 1];
loop {
unwrap!(usart.blocking_read(&mut buf));
unwrap!(usart.blocking_write(&buf));
}
}
static EXECUTOR: StaticCell<Executor> = StaticCell::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
let executor = EXECUTOR.init(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}

46
examples/stm32h5/src/bin/usart_dma.rs Normal file
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@ -0,0 +1,46 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use core::fmt::Write;
use cortex_m_rt::entry;
use defmt::*;
use embassy_executor::Executor;
use embassy_stm32::dma::NoDma;
use embassy_stm32::interrupt;
use embassy_stm32::usart::{Config, Uart};
use heapless::String;
use static_cell::StaticCell;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::task]
async fn main_task() {
let p = embassy_stm32::init(Default::default());
let config = Config::default();
let irq = interrupt::take!(UART7);
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, p.GPDMA1_CH0, NoDma, config);
for n in 0u32.. {
let mut s: String<128> = String::new();
core::write!(&mut s, "Hello DMA World {}!\r\n", n).unwrap();
usart.write(s.as_bytes()).await.ok();
info!("wrote DMA");
}
}
static EXECUTOR: StaticCell<Executor> = StaticCell::new();
#[entry]
fn main() -> ! {
info!("Hello World!");
let executor = EXECUTOR.init(Executor::new());
executor.run(|spawner| {
unwrap!(spawner.spawn(main_task()));
})
}

58
examples/stm32h5/src/bin/usart_split.rs Normal file
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@ -0,0 +1,58 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
use embassy_stm32::dma::NoDma;
use embassy_stm32::interrupt;
use embassy_stm32::peripherals::{GPDMA1_CH1, UART7};
use embassy_stm32::usart::{Config, Uart, UartRx};
use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
use embassy_sync::channel::Channel;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::task]
async fn writer(mut usart: Uart<'static, UART7, NoDma, NoDma>) {
unwrap!(usart.blocking_write(b"Hello Embassy World!\r\n"));
info!("wrote Hello, starting echo");
let mut buf = [0u8; 1];
loop {
unwrap!(usart.blocking_read(&mut buf));
unwrap!(usart.blocking_write(&buf));
}
}
static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new();
#[embassy_executor::main]
async fn main(spawner: Spawner) -> ! {
let p = embassy_stm32::init(Default::default());
info!("Hello World!");
let config = Config::default();
let irq = interrupt::take!(UART7);
let mut usart = Uart::new(p.UART7, p.PF6, p.PF7, irq, p.GPDMA1_CH0, p.GPDMA1_CH1, config);
unwrap!(usart.blocking_write(b"Type 8 chars to echo!\r\n"));
let (mut tx, rx) = usart.split();
unwrap!(spawner.spawn(reader(rx)));
loop {
let buf = CHANNEL.recv().await;
info!("writing...");
unwrap!(tx.write(&buf).await);
}
}
#[embassy_executor::task]
async fn reader(mut rx: UartRx<'static, UART7, GPDMA1_CH1>) {
let mut buf = [0; 8];
loop {
info!("reading...");
unwrap!(rx.read(&mut buf).await);
CHANNEL.send(buf).await;
}
}

128
examples/stm32h5/src/bin/usb_serial.rs Normal file
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@ -0,0 +1,128 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::{panic, *};
use embassy_executor::Spawner;
use embassy_stm32::rcc::{AHBPrescaler, APBPrescaler, Hse, HseMode, Pll, PllSource, Sysclk, VoltageScale};
use embassy_stm32::time::Hertz;
use embassy_stm32::usb::{Driver, Instance};
use embassy_stm32::{interrupt, pac, Config};
use embassy_usb::class::cdc_acm::{CdcAcmClass, State};
use embassy_usb::driver::EndpointError;
use embassy_usb::Builder;
use futures::future::join;
use {defmt_rtt as _, panic_probe as _};
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi = None;
config.rcc.hsi48 = true; // needed for usb
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::BypassDigital,
});
config.rcc.pll1 = Some(Pll {
source: PllSource::Hse,
prediv: 2,
mul: 125,
divp: Some(2), // 250mhz
divq: None,
divr: None,
});
config.rcc.ahb_pre = AHBPrescaler::Div2;
config.rcc.apb1_pre = APBPrescaler::Div4;
config.rcc.apb2_pre = APBPrescaler::Div2;
config.rcc.apb3_pre = APBPrescaler::Div4;
config.rcc.sys = Sysclk::Pll1P;
config.rcc.voltage_scale = VoltageScale::Scale0;
let p = embassy_stm32::init(config);
info!("Hello World!");
unsafe {
pac::RCC.ccipr4().write(|w| {
w.set_usbsel(pac::rcc::vals::Usbsel::HSI48);
});
}
// Create the driver, from the HAL.
let irq = interrupt::take!(USB_DRD_FS);
let driver = Driver::new(p.USB, irq, p.PA12, p.PA11);
// Create embassy-usb Config
let mut config = embassy_usb::Config::new(0xc0de, 0xcafe);
config.manufacturer = Some("Embassy");
config.product = Some("USB-serial example");
config.serial_number = Some("12345678");
// Required for windows compatiblity.
// https://developer.nordicsemi.com/nRF_Connect_SDK/doc/1.9.1/kconfig/CONFIG_CDC_ACM_IAD.html#help
config.device_class = 0xEF;
config.device_sub_class = 0x02;
config.device_protocol = 0x01;
config.composite_with_iads = true;
// Create embassy-usb DeviceBuilder using the driver and config.
// It needs some buffers for building the descriptors.
let mut device_descriptor = [0; 256];
let mut config_descriptor = [0; 256];
let mut bos_descriptor = [0; 256];
let mut control_buf = [0; 64];
let mut state = State::new();
let mut builder = Builder::new(
driver,
config,
&mut device_descriptor,
&mut config_descriptor,
&mut bos_descriptor,
&mut control_buf,
);
// Create classes on the builder.
let mut class = CdcAcmClass::new(&mut builder, &mut state, 64);
// Build the builder.
let mut usb = builder.build();
// Run the USB device.
let usb_fut = usb.run();
// Do stuff with the class!
let echo_fut = async {
loop {
class.wait_connection().await;
info!("Connected");
let _ = echo(&mut class).await;
info!("Disconnected");
}
};
// Run everything concurrently.
// If we had made everything `'static` above instead, we could do this using separate tasks instead.
join(usb_fut, echo_fut).await;
}
struct Disconnected {}
impl From<EndpointError> for Disconnected {
fn from(val: EndpointError) -> Self {
match val {
EndpointError::BufferOverflow => panic!("Buffer overflow"),
EndpointError::Disabled => Disconnected {},
}
}
}
async fn echo<'d, T: Instance + 'd>(class: &mut CdcAcmClass<'d, Driver<'d, T>>) -> Result<(), Disconnected> {
let mut buf = [0; 64];
loop {
let n = class.read_packet(&mut buf).await?;
let data = &buf[..n];
info!("data: {:x}", data);
class.write_packet(data).await?;
}
}

4
examples/stm32h7/Cargo.toml
View File

@ -19,8 +19,8 @@ defmt-rtt = "0.4"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
embedded-nal-async = "0.4.0"
panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }

4
examples/stm32h7/src/bin/flash.rs
View File

@ -14,12 +14,12 @@ async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(Default::default());
info!("Hello Flash!");
const ADDR: u32 = 0x08_0000;
const ADDR: u32 = 0; // This is the offset into bank 2, the absolute address is 0x8_0000
// wait a bit before accessing the flash
Timer::after(Duration::from_millis(300)).await;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank2_region;
info!("Reading...");
let mut buf = [0u8; 32];

2
examples/stm32l0/src/bin/flash.rs
View File

@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
const ADDR: u32 = 0x26000;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank1_region;
info!("Reading...");
let mut buf = [0u8; 8];

2
examples/stm32l1/src/bin/flash.rs
View File

@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
const ADDR: u32 = 0x26000;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank1_region;
info!("Reading...");
let mut buf = [0u8; 8];

4
examples/stm32l4/Cargo.toml
View File

@ -18,8 +18,8 @@ defmt-rtt = "0.4"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
panic-probe = { version = "0.3", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
heapless = { version = "0.7.5", default-features = false }

2
examples/stm32wl/Cargo.toml
View File

@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
embassy-sync = { version = "0.1.0", path = "../../embassy-sync", features = ["defmt"] }
embassy-executor = { version = "0.1.0", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32wl55jc-cm4", "time-driver-any", "memory-x", "subghz", "unstable-pac", "exti"] }
embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32wl55jc-cm4", "time-driver-any", "memory-x", "unstable-pac", "exti"] }
embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["stm32wl", "time", "defmt"] }
lorawan-device = { version = "0.8.0", default-features = false, features = ["async"] }

2
examples/stm32wl/src/bin/flash.rs
View File

@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
const ADDR: u32 = 0x36000;
let mut f = Flash::new(p.FLASH);
let mut f = Flash::new(p.FLASH).into_regions().bank1_region;
info!("Reading...");
let mut buf = [0u8; 8];

1
rust-toolchain.toml
View File

@ -9,5 +9,6 @@ targets = [
"thumbv6m-none-eabi",
"thumbv7em-none-eabihf",
"thumbv8m.main-none-eabihf",
"riscv32imac-unknown-none-elf",
"wasm32-unknown-unknown",
]

4
tests/rp/Cargo.toml
View File

@ -17,8 +17,8 @@ defmt-rtt = "0.4"
cortex-m = { version = "0.7.6" }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
panic-probe = { version = "0.3.0", features = ["print-defmt"] }
futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
embedded-io = { version = "0.4.0", features = ["async"] }

5
tests/stm32/Cargo.toml
View File

@ -11,6 +11,7 @@ stm32g071rb = ["embassy-stm32/stm32g071rb"] # Nucleo
stm32g491re = ["embassy-stm32/stm32g491re"] # Nucleo
stm32h755zi = ["embassy-stm32/stm32h755zi-cm7"] # Nucleo
stm32wb55rg = ["embassy-stm32/stm32wb55rg"] # Nucleo
stm32h563zi = ["embassy-stm32/stm32h563zi"] # Nucleo
stm32u585ai = ["embassy-stm32/stm32u585ai"] # IoT board
[dependencies]
@ -25,8 +26,8 @@ defmt-rtt = "0.4"
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.0"
embedded-hal = "0.2.6"
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
embedded-hal-async = { version = "=0.2.0-alpha.0" }
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
embedded-hal-async = { version = "=0.2.0-alpha.1" }
panic-probe = { version = "0.3.0", features = ["print-defmt"] }
[profile.dev]

2
tests/stm32/src/bin/gpio.rs
View File

@ -30,6 +30,8 @@ async fn main(_spawner: Spawner) {
let (mut a, mut b) = (p.PB6, p.PB7);
#[cfg(feature = "stm32u585ai")]
let (mut a, mut b) = (p.PD9, p.PD8);
#[cfg(feature = "stm32h563zi")]
let (mut a, mut b) = (p.PB6, p.PB7);
// Test initial output
{

19
tests/stm32/src/bin/spi.rs
View File

@ -17,22 +17,25 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
#[cfg(feature = "stm32f103c8")]
let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
#[cfg(feature = "stm32f429zi")]
let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
#[cfg(feature = "stm32h755zi")]
let (sck, mosi, miso) = (p.PA5, p.PB5, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PB5, p.PA6);
#[cfg(feature = "stm32g491re")]
let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
#[cfg(feature = "stm32g071rb")]
let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
#[cfg(feature = "stm32wb55rg")]
let (sck, mosi, miso) = (p.PA5, p.PA7, p.PA6);
let (spi, sck, mosi, miso) = (p.SPI1, p.PA5, p.PA7, p.PA6);
#[cfg(feature = "stm32u585ai")]
let (sck, mosi, miso) = (p.PE13, p.PE15, p.PE14);
let (spi, sck, mosi, miso) = (p.SPI1, p.PE13, p.PE15, p.PE14);
#[cfg(feature = "stm32h563zi")]
let (spi, sck, mosi, miso) = (p.SPI4, p.PE12, p.PE14, p.PE13);
info!("asdfa;");
let mut spi = Spi::new(
p.SPI1,
spi,
sck, // Arduino D13
mosi, // Arduino D11
miso, // Arduino D12

18
tests/stm32/src/bin/spi_dma.rs
View File

@ -16,22 +16,24 @@ async fn main(_spawner: Spawner) {
info!("Hello World!");
#[cfg(feature = "stm32f103c8")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH3, p.DMA1_CH2);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH3, p.DMA1_CH2);
#[cfg(feature = "stm32f429zi")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA2_CH3, p.DMA2_CH2);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA2_CH3, p.DMA2_CH2);
#[cfg(feature = "stm32h755zi")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PB5, p.PA6, p.DMA1_CH0, p.DMA1_CH1);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PB5, p.PA6, p.DMA1_CH0, p.DMA1_CH1);
#[cfg(feature = "stm32g491re")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
#[cfg(feature = "stm32g071rb")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
#[cfg(feature = "stm32wb55rg")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PA5, p.PA7, p.PA6, p.DMA1_CH1, p.DMA1_CH2);
#[cfg(feature = "stm32u585ai")]
let (sck, mosi, miso, tx_dma, rx_dma) = (p.PE13, p.PE15, p.PE14, p.GPDMA1_CH0, p.GPDMA1_CH1);
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI1, p.PE13, p.PE15, p.PE14, p.GPDMA1_CH0, p.GPDMA1_CH1);
#[cfg(feature = "stm32h563zi")]
let (spi, sck, mosi, miso, tx_dma, rx_dma) = (p.SPI4, p.PE12, p.PE14, p.PE13, p.GPDMA1_CH0, p.GPDMA1_CH1);
let mut spi = Spi::new(
p.SPI1,
spi,
sck, // Arduino D13
mosi, // Arduino D11
miso, // Arduino D12

2
tests/stm32/src/bin/usart.rs
View File

@ -32,6 +32,8 @@ async fn main(_spawner: Spawner) {
let (tx, rx, usart, irq) = (p.PB6, p.PB7, p.USART1, interrupt::take!(USART1));
#[cfg(feature = "stm32u585ai")]
let (tx, rx, usart, irq) = (p.PD8, p.PD9, p.USART3, interrupt::take!(USART3));
#[cfg(feature = "stm32h563zi")]
let (tx, rx, usart, irq) = (p.PB6, p.PB7, p.LPUART1, interrupt::take!(LPUART1));
let config = Config::default();
let mut usart = Uart::new(usart, rx, tx, irq, NoDma, NoDma, config);

9
tests/stm32/src/bin/usart_dma.rs
View File

@ -62,6 +62,15 @@ async fn main(_spawner: Spawner) {
p.GPDMA1_CH0,
p.GPDMA1_CH1,
);
#[cfg(feature = "stm32h563zi")]
let (tx, rx, usart, irq, tx_dma, rx_dma) = (
p.PB6,
p.PB7,
p.LPUART1,
interrupt::take!(LPUART1),
p.GPDMA1_CH0,
p.GPDMA1_CH1,
);
let config = Config::default();
let mut usart = Uart::new(usart, rx, tx, irq, tx_dma, rx_dma, config);