max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge #1014

Browse Source 
1014: Add memory barriers to H7 flash driver to mitigate PGSERR errors r=lulf a=matoushybl

The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.

Without the barrier, the PG bit is not set, when the writes are being done, resulting in an error.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
This commit is contained in:
bors[bot] 2022-10-19 07:29:12 +00:00 committed by GitHub
commit d9c773f475
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
embassy-stm32/src/flash/h7.rs
View File

@ -39,6 +39,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
w.set_psize(2); // 32 bits at once
});
cortex_m::asm::isb();
cortex_m::asm::dsb();
atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
let ret = {
let mut ret: Result<(), Error> = Ok(());
let mut offset = offset;
@ -64,6 +68,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error
bank.cr().write(|w| w.set_pg(false));
cortex_m::asm::isb();
cortex_m::asm::dsb();
atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst);
ret
}