nrf/qspi: set correct config for flash chip in the nrf52840dk
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3bd36dce76
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@ -24,16 +24,17 @@ struct AlignedBuf([u8; 4096]);
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#[embassy::main]
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async fn main(_spawner: Spawner, p: Peripherals) {
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let csn = p.P0_17;
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let sck = p.P0_19;
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let io0 = p.P0_20;
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let io1 = p.P0_21;
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let io2 = p.P0_22;
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let io3 = p.P0_23;
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// Config for the MX25R64 present in the nRF52840 DK
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let mut config = qspi::Config::default();
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config.read_opcode = qspi::ReadOpcode::READ4IO;
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config.write_opcode = qspi::WriteOpcode::PP4IO;
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config.write_page_size = qspi::WritePageSize::_256BYTES;
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let config = qspi::Config::default();
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let irq = interrupt::take!(QSPI);
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let mut q = qspi::Qspi::new(p.QSPI, irq, sck, csn, io0, io1, io2, io3, config).await;
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let mut q = qspi::Qspi::new(
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p.QSPI, irq, p.P0_19, p.P0_17, p.P0_20, p.P0_21, p.P0_22, p.P0_23, config,
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)
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.await;
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let mut id = [1; 3];
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q.custom_instruction(0x9F, &[], &mut id).await.unwrap();
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@ -27,7 +27,11 @@ async fn main(_spawner: Spawner, mut p: Peripherals) {
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let mut irq = interrupt::take!(QSPI);
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loop {
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// Config for the MX25R64 present in the nRF52840 DK
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let mut config = qspi::Config::default();
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config.read_opcode = qspi::ReadOpcode::READ4IO;
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config.write_opcode = qspi::WriteOpcode::PP4IO;
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config.write_page_size = qspi::WritePageSize::_256BYTES;
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config.deep_power_down = Some(qspi::DeepPowerDownConfig {
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enter_time: 3, // tDP = 30uS
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exit_time: 3, // tRDP = 35uS
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